Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Status of claim(s) to be treated in this office action:
a. Independent: 1, 16 and 20
b. Pending: 1-20
Per MPEP 2111 and 2111.01, the claims are given their broadest reasonable interpretation and the words of the claims are given their plain meaning consistent with the specification without importing claim limitations from the specification.
Priority
Acknowledgment is made of applicant's claim for foreign priority based on an application filed in Korea on 12/22/2023. It is noted, however, that applicant has not filed a certified copy of the Korean Patent Application No. 10-2023-0189173 application as required by 37 CFR 1.55.
Information Disclosure Statement
The information disclosure statements (IDS) are submitted on 6/6/2024 and 8/5/2024. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
The following title is suggested: Nonvolatile memory device and operating method based on program execution and/or erase execution time.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Independent claims 1, 16 and 20 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the enablement requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to enable one skilled in the art to which it pertains, or with which it is most nearly connected, to make and/or use the invention. Specification and Drawings both describe NAND Flash storage device. All the independent claims omit reciting this essential feature.
Dependent claims 2-8, 10-15 and 17-19 all carry the same deficit due to dependency chain and henceforth rejected.
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Independent claims 1, 16 and 20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being incomplete for omitting essential elements, such omission amounting to a gap between the elements. See MPEP § 2172.01. The omitted elements are: NAND Flash storage device, which is being used throughout Specification and Drawings.
Dependent claims 2-8, 10-15 and 17-19 all carry the same deficit due to dependency chain and henceforth rejected.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-20 are rejected under 35 U.S.C. 103 as being unpatentable over Nagashima (US 20150380094) in view of Yamada et al. (US 20020080649).
Regarding independent claim 1, Nagashima discloses a storage device (Figs. 1-16) comprising:
a nonvolatile memory device (20; Fig. 5) configured to receive a command and an address for a write operation or an erase operation via command-address pins (Fig. 4 and [0069] describes commands and addresses being received by memory device. Fig. 5 and [0083] describes that controller 10A and the NAND memory 20 are connected to each other by a control I/O line (Ctrl I/O) used to input and output commands, addresses, data, and so on), transmit and receive write data or read data via data pins ([0085] describes reading and writing data from and to the NAND memory 20), and generate degeneration information by measuring at least one of a program execution time to perform the write operation and an erase execution time to perform the erase operation ([0086], [0089] and [0096] describes measuring writing time WT necessary for the writing process, the erasing time ET necessary for the erasing time); and
a storage controller configured to receive the degeneration information from the nonvolatile memory device (Figs. 6A, 6B and [0108]-[0109] describes deterioration degree DL1, DL2 and so on), and control the nonvolatile memory device to adjust at least one of a program voltage of the write operation and an erase voltage of the erase operation based on the degeneration information ([0140] and [0155] describes changing value of writing and erasing voltage).
Nagashima does not explicitly disclose that nonvolatile memory device generates degeneration information;
However, controller being part of nonvolatile memory device is known technology in the art as also depicted in Fig. 13 of Yamada where controller 150 is placed together with local memory 140 and buffer memory 160.
It would have been obvious to one of ordinary skill in the art before the earliest effective filing date to apply the teachings of Yamada to Nagashima in order to shorten time taken to read data as taught by Yamada ([0009]).
Regarding claim 2, Nagashima and Yamada together disclose all the elements of claim 1 as above and through Yamada further the nonvolatile memory device is further configured to transmit the degeneration information to the storage controller via the command-address pins ([0035] describes pins for data and command).
It would have been obvious to one of ordinary skill in the art before the earliest effective filing date to apply the teachings of Yamada to modified Nagashima in order to shorten time taken to read data as taught by Yamada ([0009]).
Regarding claim 3, Nagashima and Yamada together disclose all the elements of claim 1 as above and through Nagashima further the storage controller is further configured to control the nonvolatile memory device to decrease the program voltage based on the degeneration information indicating a decrease in the program execution time ([0140] describes lowering writing voltage).
Regarding claim 4, Nagashima and Yamada together disclose all the elements of claim 1 as above and through Nagashima further the storage controller is further configured to control the nonvolatile memory device to increase the erase voltage based on the degeneration information indicating an increase in the erase execution time ([0155] describes increasing erase voltage).
Regarding claim 5, Nagashima and Yamada together disclose all the elements of claim 1 as above and through Nagashima further the nonvolatile memory device is further configured to update the degeneration information by measuring the program execution time and the erase execution time each time a program-erase count reaches any of a plurality of reference counts (Figs. 7A, 7B, 8A, 8B and [0110]-[0113] describes updating the degeneration information based on program and erase threshold count).
Regarding claim 6, Nagashima and Yamada together disclose all the elements of claim 1 as above and through Nagashima further the nonvolatile memory device is further configured to update the degeneration information by measuring the program execution time and the erase execution time based on a request from the storage controller (Fig. 5 and [0086] describes that monitoring unit 12 monitors the characteristics of the NAND device by the processes of writing and erasing the data to and from the NAND device. The monitored characteristics of the NAND device include at least one of, for example, the number Nw of times of the writing process, the number Ne of times of the erasing process, the writing time WT necessary for the writing process, the erasing time ET necessary for the erasing time, a repetition number (the loop number Lw at the writing time) of a writing operation and a verification operation of the writing process, and a repetition number (the loop number Le at the erasing moment) of an erasing operation and a verification operation of the erasing process).
Regarding claim 7, Nagashima and Yamada together disclose all the elements of claim 1 as above and through Nagashima further the nonvolatile memory device is further configured to provide, to the storage controller, a state signal that is activated at a first logic level indicating a ready state while in the ready state and deactivated at a second logic level indicating a busy state while performing internal operations for the write operation or the erase operation, and wherein the nonvolatile memory device is further configured to measure the program execution time or the erase execution time based on a time interval while the state signal is deactivated to the second logic level during the write operation or the erase operation ([0090]-[0098] describes using ready/busy signal (Ry/By)).
Regarding claim 8, Nagashima and Yamada together disclose all the elements of claim 7 as above and through Yamada further the nonvolatile memory device is further configured to receive the command and the address in synchronization with a command-address clock signal provided from the storage controller, and wherein the nonvolatile memory device is further configured to measure the program execution time by counting clock cycles of the command-address clock signal while the state signal is deactivated to the second logic level during the write operation ([0042] describes serial clock SC, so as to read the data of a row or word line held in the sense latch circuit 17 in synchronism with the clock SC, to send the data to an external unit, and to transfer a row of the programming data input from the external unit to the sense latch circuit 17 in synchronism with the clock SC).
It would have been obvious to one of ordinary skill in the art before the earliest effective filing date to apply the teachings of Yamada to modified Nagashima in order to shorten time taken to read data as taught by Yamada ([0009]).
Regarding claim 9, Nagashima and Yamada together disclose all the elements of claim 1 as above and through Nagashima further the nonvolatile memory device is a NAND flash memory device ([0034] describes NAND-type flash memory devices)
And Yamada teaches configured to operate according to Separate Command Address (SCA) protocol (Fig. 13 and [0090] describes a control bus 171, an address bus 172 and a data bus 173).
It would have been obvious to one of ordinary skill in the art before the earliest effective filing date to apply the teachings of Yamada to modified Nagashima in order to shorten time taken to read data as taught by Yamada ([0009]).
Regarding claim 10, Nagashima and Yamada together disclose all the elements of claim 1 as above and through Nagashima further the nonvolatile memory device is further configured to set at least one target wordline among wordlines of a memory block and measure the program execution time with respect to the at least one target wordline ([0091]-[0094] describes measuring individual page writing time or average writing time for blocks).
Regarding claim 11, Nagashima and Yamada together disclose all the elements of claim 1 as above and through Nagashima further the nonvolatile memory device is further configured to measure the program execution time with respect to each of a plurality of wordlines of a memory block to obtain a plurality of program execution times, and control the program voltage with respect to the memory block based on an average value of the plurality of program execution times ([0091]-[0094] describes measuring individual page writing time or average writing time for blocks).
Regarding claim 12, Nagashima and Yamada together disclose all the elements of claim 1 as above and through Nagashima further the nonvolatile memory device is further configured to: perform the write operation in accordance with incremental step pulse programming (ISPP); incrementally increase the program voltage as a program loop is repeated; and measure the program execution time based on a number of program loops performed to complete the write operation (Fig. 15 and [0099]-[0102]).
Regarding claim 13, Nagashima and Yamada together disclose all the elements of claim 1 as above and through Nagashima further the nonvolatile memory device is further configured to: perform the erase operation in accordance with an incremental step pulse erasing (ISPE), increase the erase voltage step by step as an erase loop is repeated; and measure the erase execution time based on a number of erase loops performed to complete the erase operation (Fig. 19B and [0103]-[0105]).
Regarding claim 14, Nagashima and Yamada together disclose all the elements of claim 1 as above and through Nagashima further the nonvolatile memory device is further configured to: perform the write operation in accordance with incremental step pulse programming (ISPP); incrementally increase the program voltage as a program loop is repeated (Fig. 15 and [0099]-[0102]); and decrease the program voltage of a first program loop of the ISPP based on the degeneration information indicating an increased degree of degeneration of the nonvolatile memory device ([0140] describes lowering writing voltage).
Regarding claim 15, Nagashima and Yamada together disclose all the elements of claim 1 as above and through Nagashima further the nonvolatile memory device is further configured to perform the erase operation in accordance with an incremental step pulse erasing (ISPE), and incrementally increase the erase voltage step by step as an erase loop is repeated (Fig. 19B and [0103]-[0105]), and wherein the storage controller is further configured to control the nonvolatile memory device to increase the erase voltage of a first erase loop of the ISPE based on the degeneration information indicating an increased degree of degeneration of the nonvolatile memory device ([0155] describes increasing erase voltage).
Regarding independent method claim 16, it recites the same claim limitations of independent device claim 1 in method format and henceforth rejected the same way.
Regarding method claim 17, it recites the same claim limitations of device claim 7 in method format and henceforth rejected the same way.
Regarding method claims 18-19, it recites the same claim limitations of device claims 3-4 respectively in method format and henceforth rejected the same way.
Regarding independent claim 20, Nagashima discloses a nonvolatile memory device (Figs. 1-20) comprising:
a memory cell array comprising a plurality of nonvolatile memory cells (Figs. 4-5 show memory cell array 201/NAND memory 20);
command-address pins configured to communicate a command and an address for a write operation or an erase operation (Fig. 4 and [0069] describes commands and addresses being received by memory device. Fig. 5 and [0083] describes that controller 10A and the NAND memory 20 are connected to each other by a control I/O line (Ctrl I/O) used to input and output commands, addresses, data, and so on);
data pins configured to communicate write data and readout data ([0085] describes reading and writing data from and to the NAND memory 20);
a state pin configured to communicate a state signal that is activated at a first logic level indicating a ready state while in the ready state and deactivated at a second logic level indicating a busy state while performing internal operations for the write operation or the erase operation (Fig. 5 shows dedicated pin Ry/By and [0090]-[0098] describes using ready/busy signal (Ry/By)), and
a degeneration detector circuit configured to generate degeneration information by identifying at least one of a program execution time to perform the write operation and an erase execution time to perform the erase operation, based on the state signal ([0086], [0089] and [0096] describes measuring writing time WT necessary for the writing process, the erasing time ET necessary for the erasing time. Figs. 6A, 6B and [0108]-[0109] describes deterioration degree DL1, DL2 and so on).
Conclusion
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/SULTANA BEGUM/Primary Examiner, Art Unit 2824 1/7/2026