DETAILED ACTION
This Action is responsive to the communication filed on 06/06/2024.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Specification
The specification is objected to as failing to provide proper antecedent basis for the claimed subject matter. See 37 CFR 1.75(d)(1) and MPEP § 608.01(o). Terms and phrases used in the claims presented in the application should find antecedent basis in the description so that the meaning of the terms in the claims may be ascertainable by reference to the description. Correction of the following is required: The claimed limitations recited as “intermedia dielectric layer” do not have antecedent basis in the specification.
Double Patenting
The non-statutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A non-statutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on non-statutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a non-statutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a Non-final Office action, see 37 CFR 1.111(a). For a reply to Final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 1-7, 11, 13-19 are rejected on the ground of non-statutory double patenting as being anticipated by Claims 1-7, 11, and 13-20 of U.S. Patent No. 12,074,105 (hereinafter, Zhu II).
Although the claims at issue are not identical, they are not patentably distinct from each other because Zhu II anticipates claims of the instant application.
Independent Claim 1 of the Instant Application is anticipated by Claim 1 of Zhu II, the limitations including an electronic device, comprising:
Instant Application
Patent No.12,074,105
a memory stack comprising interleaved conductive layers and dielectric layers;
a memory stack comprising interleaved conductive layers and dielectric layers;
a channel structure extending vertically through the memory stack;
a channel structure extending vertically through the memory stack, an upper end of a plug of the channel structure being coplanar with an upper surface of the memory stack;
a first dielectric layer having a first dielectric material in contact with the memory stack and a plug of the channel structure;
a first dielectric layer having a first dielectric material in contact with the memory stack and the plug;
an intermedia dielectric layer on the first dielectric layer and having a second dielectric material different from the first dielectric material;
an intermedia dielectric layer on the first dielectric layer and having a second dielectric material different from the first dielectric material;
a second dielectric layer on the intermedia dielectric layer;
a second dielectric layer on the intermedia dielectric layer;
a slit structure extending along a lateral direction to separate the memory stack;
a slit structure extending along a lateral direction to separate the memory stack, and comprising a lower portion having polysilicon and an upper portion having metal;
a first contact penetrating the intermedia dielectric layer and the first dielectric layer, the first contact being in contact with the plug of the channel structure, a first lateral dimension of an upper end of the first contact is not less than a second lateral dimension of a lower end of the first contact;
a first contact penetrating the intermedia dielectric layer and the first dielectric layer, the first contact being in contact with the plug of the channel structure, a first lateral dimension of an upper end of the first contact is not less than a second lateral dimension of a lower end of the first contact;
a second contact penetrating the second dielectric layer and in contact with at least the upper end of the first contact;
a second contact penetrating the second dielectric layer and in contact with at least the upper end of the first contact;
a third contact penetrating the intermedia dielectric layer and the first dielectric layer, the third contact being in contact with the slit structure;
a third contact penetrating the intermedia dielectric layer and the first dielectric layer, the third contact being in contact with the upper portion of the slit structure;
and a fourth contact penetrating the second dielectric layer and in contact with at least the upper end of the third contact.
and a fourth contact penetrating the second dielectric layer and in contact with at least the upper end of the third contact.
Claim 2
Instant Application
Patent No.12,074,105
wherein the second contact is further in contact with the intermedia dielectric layer.
wherein the second contact is further in contact with the intermedia dielectric layer.
Claim 3
Instant Application
Patent No.12,074,105
wherein a first area of a lower end of the second contact is less than a second area of the upper end of the first contact.
wherein a first area of a lower end of the second contact is less than a second area of the upper end of the first contact.
Claim 4
Instant Application
Patent No.12,074,105
a third area of a contacting region between the lower end of the second contact and the upper end of the first contact is less than the first area.
a third area of a contacting region between the lower end of the second contact and the upper end of the first contact is less than the first area.
Claim 5
Instant Application
Patent No.12,074,105
wherein the first dielectric layer and the second dielectric layer comprise a first dielectric material, and the intermedia dielectric layer comprises a second dielectric material different from the first dielectric material.
wherein the first dielectric layer and the second dielectric layer comprise a first dielectric material, and the intermedia dielectric layer comprises a second dielectric material different from the first dielectric material.
Claim 6
Instant Application
Patent No.12,074,105
wherein an etch selectivity between the first dielectric material and the second dielectric material is not less than about 5:1.
wherein an etch selectivity between the first dielectric material and the second dielectric material is not less than about 5:1.
Claim 7
Instant Application
Patent No.12,074,105
wherein: the first dielectric material comprises silicon oxide; and the second dielectric material comprises at least one of silicon nitride, silicon oxynitride, or high dielectric constant (high-k) dielectrics.
wherein: the first dielectric material comprises silicon oxide; and the second dielectric material comprises at least one of silicon nitride, silicon oxynitride, or high dielectric constant (high-k) dielectrics.
Independent Claim 11 of the Instant Application is anticipated by Claim 11 of Zhu II, the limitations including an electronic device, comprising:
Instant Application
Patent No.12,074,105
a memory stack comprising interleaved conductive layers and dielectric layers;
a memory stack comprising interleaved conductive layers and dielectric layers;
a channel structure penetrating the memory stack in a vertical direction, and including a plug embedded in the memory stack;
a channel structure penetrating the memory stack in a vertical direction, and including a plug embedded in the memory stack;
a dielectric stack on the memory stack, comprising: a first dielectric layer and a second dielectric layer having a first dielectric material, and an intermedia dielectric layer between the first dielectric layer and the second dielectric layer, and having a second dielectric material different from the first dielectric material;
a dielectric stack on the memory stack, comprising: a first dielectric layer and a second dielectric layer having a first dielectric material, and an intermedia dielectric layer between the first dielectric layer and the second dielectric layer, and having a second dielectric material different from the first dielectric material;
a slit structure extending along a lateral direction to separate the memory stack;
a slit structure extending along a lateral direction to separate the memory stack,
a first contact structure penetrating the dielectric stack and being in contact with the plug, the first contact structure comprising a lower contact portion penetrating the first dielectric layer and the intermedia dielectric layer, and an upper contact portion penetrating the second dielectric layer;
a first contact structure penetrating the dielectric stack and being in contact with the plug, the first contact structure comprising a lower contact portion penetrating the first dielectric layer and the intermedia dielectric layer, and an upper contact portion penetrating the second dielectric layer;
and a second contact structure penetrating the dielectric stack and being in contact with the slit structure, the second contact structure comprising a lower contact portion penetrating the first dielectric layer and the intermedia dielectric layer, and an upper contact portion penetrating the second dielectric layer.
and a second contact structure penetrating the dielectric stack and being in contact with the upper portion of the slit structure, the second contact structure comprising a lower contact portion penetrating the first dielectric layer and the intermedia dielectric layer, and an upper contact portion penetrating the second dielectric layer.
Claim 13
Instant Application
Patent No.12,074,105
wherein the lower contact portion includes a top surface in contact with a lower surface of the second dielectric layer.
wherein the lower contact portion includes a top surface in contact with a lower surface of the second dielectric layer.
Claim 14
Instant Application
Patent No.12,074,105
wherein the upper contact portion includes a bottom surface in contact with a top surface of the intermedia dielectric layer.
wherein the upper contact portion includes a bottom surface in contact with a top surface of intermedia dielectric layer.
Claim 15
Instant Application
Patent No.12,074,105
wherein the top surface of the lower contact portion and the bottom surface of the upper contact portion are flush with an interface between the intermedia dielectric layer and the second dielectric layer.
wherein the top surface of the lower contact portion and the bottom surface of the upper contact portion are flush with an interface between the intermedia dielectric layer and the second dielectric layer.
Claim 16
Instant Application
Patent No.12,074,105
wherein an etch selectivity between the first dielectric material and the second dielectric material is not less than about 5:1.
wherein an etch selectivity between the first dielectric material and the second dielectric material is not less than about 5:1.
Claim 17
Instant Application
Patent No.12,074,105
wherein: the first dielectric material comprises silicon oxide; and the second dielectric material comprises at least one of silicon nitride, silicon oxynitride, or high dielectric constant (high-k) dielectrics.
wherein: the first dielectric material comprises silicon oxide; and the second dielectric material comprises at least one of silicon nitride, silicon oxynitride, or high dielectric constant (high-k) dielectrics.
Claim 18 (of Instant Application) | Claim 19 (of Zhu II)
Instant Application
Patent No.12,074,105
wherein a side of the lower contact portion is straight smooth from an upper end to a lower end.
wherein a side of the lower contact portion is straight smooth from an upper end to a lower end.
Claim 19 (of Instant Application) | Claim 20 (of Zhu II)
Instant Application
Patent No.12,074,105
wherein the lower contact portion does not include a surface in contact with a top surface of the first dielectric layer or a bottom surface of the intermedia dielectric layer.
wherein the lower contact portion does not include a surface in contact with a top surface of the first dielectric layer or a bottom surface of the intermedia dielectric layer.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
Claims 1-20 are rejected under 35 U.S.C. 112(a) as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, at the time the application was filed, had possession of the claimed invention.
The requirements for "continuing" applications are set forth in MPEP §§ 201.07, § 201.08, and § 211. Applicants are entitled to claim the benefit of the filing date of earlier applications for later claimed inventions under 35 U.S.C. 120 only when the earlier application discloses that invention in the manner required by 35 U.S.C. 112(a). The claimed invention in a continuation application and in a divisional application must be disclosed in the original application.
Claims 1-2 and 5 use claim language which is not synonymous with the terminology used in the original disclosure. For example, “intermedia dielectric layer” is terminology which is not found in the original disclosure.
Claims 3-4 and 6-10 are rejected under 35 U.S.C. 112(a) as failing to comply with the written description requirement due to the claims’ dependency to Claim 1.
Claims 11, 14-15, and 19 use claim language which is not synonymous with the terminology used in the original disclosure. For example, “intermedia dielectric layer” is terminology which is not found in the original disclosure.
Claims 12-13, 16-18, and 20 are rejected under 35 U.S.C. 112(a) as failing to comply with the written description requirement due to the claims’ dependency to Claim 11.
Claim 9 is rejected under 35 U.S.C. 112(a) as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor at the time the application was filed, had possession of the claimed invention.
Claim 9 recites the limitation: “the first contact is straight smooth from the upper end to the lower end” (emphasis added). The claim contains subject matter which was not described in the specification.
Claim 12 is rejected under 35 U.S.C. 112(a) as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor at the time the application was filed, had possession of the claimed invention.
Claim 12 recites the limitation: “the upper contact portion has a second lateral dimension less than the average first lateral dimension” (emphasis added). The claim contains subject matter which was not described in the specification.
Claim 18 is rejected under 35 U.S.C. 112(a) as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor at the time the application was filed, had possession of the claimed invention.
Claim 18 recites the limitation: “a side of the lower contact portion is straight smooth from an upper end to a lower end” (emphasis added). The claim contains subject matter which was not described in the specification.
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
Claims 9 and 18 are rejected under 35 U.S.C. 112(b) as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor, regards as the invention.
Claim 9 recites the limitation: “the first contact is straight smooth from the upper end to the lower end” (emphasis added). The claimed limitation recited as “straight smooth” is indefinite because it is unclear as to the meaning of the term.
Claim 18 recites the limitation: “a side of the lower contact portion is straight smooth from an upper end to a lower end” (emphasis added). The claimed limitation recited as “straight smooth” is indefinite because it is unclear as to the meaning of the term.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ANTONIO CRITE whose telephone number is (571) 270-5267. The examiner can normally be reached Monday - Friday, 10:00 am - 6:30 pm.
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/ANTONIO B CRITE/Primary Examiner, Art Unit 2817
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