DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of group I in the reply filed on 8/28/2026 is acknowledged.
Claim Rejections - 35 USC § 102
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-2 is/are rejected under 35 U.S.C. 102a1 as being anticipated by Xie 20230268388 (cited on ids).
a. Xie teaches a semiconductor integrated circuit (IC) device comprising: a bottom source/drain region (bottom item 422 figure 6b associated with 406 above the top 414 figure 5a forming a transistor) and a top source/drain region stacked above the bottom source/drain region ( top pats associated with at least the top 406 forming a transistor) and; a conductive contact comprising a deep via that is adjacent to both the bottom source/drain region and the top source/drain region (item 432) and an extension region that laterally protrudes from the deep via (item 420); The structure forms :a first stacked transistor comprising a first bottom source/drain region and first top source/drain region stacked above the first bottom source/drain region; a second stacked transistor comprising a second bottom source/drain region and second top source/drain region stacked above the second bottom source/drain region (items 406 and 422) and an airgap spacer in contact with the bottom source/drain region (item 606 and 608), in contact with the top source/drain region (see item 606 and 608), and in contact with the deep via (see figure 6b item 606 and 608).
b. As to claim 2, Xie teaches further comprising: a common gate that controls respective charge carrier flow to/from both the bottom source/drain region and the top source/drain region; wherein the deep via is further adjacent to the common gate; and wherein the airgap spacer is further in contact with the common gate ( item 434 in contact with 606 and 608 figure 6b) .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 5-6 is/are rejected under 35 U.S.C. 103 as being unpatentable over Xie.
As to claim 5, Xie does not explicitly teach the device further comprising: a frontside gate contact connected to the common gate; and a frontside back end of line (BEOL) network connected to the frontside gate contact by a gate interconnect.
However, it was known to provide a frontside gate contact connected to the common gate; and a frontside back end of line (BEOL) network connected to the frontside gate contact by a gate interconnect to allow for interconnection of multiple devices
Thus, it would have obvious to one of ordinary skill in the art at the time of filing to
provide a frontside gate contact connected to the common gate; and a frontside back end of line (BEOL) network connected to the frontside gate contact by a gate interconnect.
To create interconnects creating a usable integrated circuit.
b. As to claim 6, a front contact would be directly on the top of 434 this is coplanar with the top of the airgap spacer thus Xie modified would suggest wherein a top surface of the airgap spacer is substantially coplanar with a bottom surface of the gate interconnect.
Allowable Subject Matter
Claims 12-19 are allowed.
Xie teaches Xie teaches A semiconductor integrated circuit (IC) device comprising: a bottom source/drain region (bottom item 422 figure 6b associated with 406 above the top 414 figure 5a forming a transistor) and a top source/drain region stacked above the bottom source/drain region ( top pats associated with at least the top 406 forming a transistor) and; a conductive contact comprising a deep via that is adjacent to both the bottom source/drain region and the top source/drain region (item 432) and an extension region that laterally protrudes from the deep via (item 420); The structure forms :a first stacked transistor comprising a first bottom source/drain region and first top source/drain region stacked above the first bottom source/drain region; a second stacked transistor comprising a second bottom source/drain region and second top source/drain region stacked above the second bottom source/drain region (items 406 and 422) and an airgap spacer in contact with the bottom source/drain region (item 606 and 608), in contact with the top source/drain region (see item 606 and 608), and in contact with the deep via (see figure 6b item 606 and 608).
While forming a second group of stacked transistors adjacent the first would be a duplication of parts there is no suggestion or teach to have n airgap spacer around the deep via and in contact with the first bottom source/drain region, in contact with the first top source/drain region, in contact with the second bottom source/drain region, and in contact with the second top source/drain region.
Claims 3-4 7-11 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
As to claim 3, Xie does not teach and or suggest wherein a top surface of the airgap spacer is above a top surface of the top source/drain region and a top surface of the common gate in conjunction with the other elements of claims 1-2 Xie teaches spacer is coplanar with the gate.
As to claim 7, Xie does not teach and or suggest further comprising: a shallow trench isolation (STI) region underneath the common gate and below and adjacent to the bottom source/drain region; wherein the deep via is further adjacent to the STI region; and wherein the airgap spacer is further in contact with the STI region in conjunction with the other elements of claims 1-2.
As to claim 10, Xie does not teach wherein the extension region is directly coupled against a top surface of the top source/drain region Xie teaches another via item 158 in conjunction with the other elements of claim 1.
As to claim 11 Xie does not teach and or suggest wherein the extension region is directly coupled against a bottom surface of the bottom source/drain region in conjunction with the other elements of claim 1, Xie teaches an insulating space between 420 and 422.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MATTHEW L REAMES whose telephone number is (571)272-2408. The examiner can normally be reached M-Th 6:00 am-4:00 pm EST.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, William F. Kraig can be reached at 571-272-8660. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/MATTHEW L. REAMES/
Primary Examiner
Art Unit 2896
/MATTHEW L REAMES/Primary Examiner, Art Unit 2896
Prosecution Insights