Prosecution Insights
Last updated: October 01, 2026
Application No. 18/736,228

SEMICONDUCTOR DEVICE

Non-Final OA §102§103§112
Filed
Jun 06, 2024
Priority
Dec 19, 2023 — RE 10-2023-0185613
Examiner
TYNES JR., LAWRENCE C
Art Unit
Tech Center
Assignee
Samsung Electronics Co., Ltd.
OA Round
1 (Non-Final)
86%
Grant Probability
Favorable
1-2
OA Rounds
0m
Est. Remaining
94%
With Interview

Examiner Intelligence

Grants 86% — above average
86%
Career Allowance Rate
676 granted / 791 resolved
+25.5% vs TC avg
Moderate +9% lift
Without
With
+8.8%
Interview Lift
resolved cases with interview
Typical timeline
2y 4m
Avg Prosecution
21 currently pending
Career history
813
Total Applications
across all art units

Statute-Specific Performance

§101
0.6%
-39.4% vs TC avg
§103
51.1%
+11.1% vs TC avg
§102
26.6%
-13.4% vs TC avg
§112
17.8%
-22.2% vs TC avg
Black line = Tech Center average estimate • Based on career data from 791 resolved cases

Office Action

§102 §103 §112
Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claim(s) 1,6-8,13 is/are rejected under 35 U.S.C. 102(A)(1) as being anticipated by Ding et al. (US-20220271045-A1; Ding). Regarding claim 1, Ding discloses a semiconductor device, comprising: a first active pattern (Fig. 3D, AP1; ¶34) that extends in a first direction (D2); a second active pattern (Fig. 3D, AP2; ¶34) spaced apart from the first active pattern in a second direction (D1) that crosses the first direction; a first source/drain pattern (Fig. 3D, SD1; ¶36) disposed on the first active pattern; a second source/drain pattern (Fig. 3D, SD2; ¶36) disposed on the second active pattern; a first active contact (Fig. 3D, AC OVER PR; ¶64) electrically connected to the first source/drain pattern; a second active contact (Fig. 3D, AC OVER NR; ¶64) electrically connected to the second source/drain pattern; and an insulating structure (Fig. 3D, 110/ST; ¶35/42) disposed between the first and second active contacts, wherein the insulating structure includes a first insulating layer (Fig. 3D, ST; ¶35 ) and a second insulating layer (Fig. 3D, 110 ; ¶ 42) disposed on the first insulating layer, and each of the first and second insulating layers is in contact with the first and second active contacts. Regarding claim 6, Ding discloses the semiconductor device of claim 1, wherein a level of a lowermost portion of the first insulating layer (Fig. 3D, ST; ¶35 ) is higher than a level of a lowermost portion of the first (Fig. 3D, AP1; ¶34) and second (Fig. 3D, AP2; ¶34) active contacts The lowermost portion of the first insulation layer is the portion aligned with trench TR. The lowermost portion has an upper surface above the lowermost portion of AP1/AP2 Regarding claim 7, Ding discloses the semiconductor device of claim 1, wherein the first insulating layer (Fig. 3D, ST; ¶35 ) comprises a material that has an etch selectivity with respect to the second insulating layer. (Fig. 3D, 110 ; ¶ 42) An etch selectivity with respect to the second insulating layer can be higher, lower, or equal. What does applicant intend by, “with respect” Regarding claim 8, Ding discloses the semiconductor device of claim 1, wherein a level of a lowermost portion of the first insulating layer (Fig. 3D, ST; ¶35 ) is lower than a level of a lowermost portion of the first (Fig. 3D, AP1; ¶34) and second (Fig. 3D, AP2; ¶34) active contacts. The lowermost portion of the first insulation layer is the portion aligned with trench TR. The lowermost portion has a lower surface below the lowermost portion of AP1/AP2 Regarding claim 13, Ding discloses a semiconductor device, comprising: a first active pattern (Fig. 3D, AP1; ¶34) that extends in a first direction (D2); a second active pattern (Fig. 3D, AP2; ¶34) spaced apart from the first active pattern in a second direction (D1) that crosses the first direction; a first source/drain pattern (Fig. 3D, SD1; ¶36) disposed on the first active pattern; a second source/drain pattern (Fig. 3D, SD2; ¶36) disposed on the second active pattern; a first active contact (Fig. 3D, AC OVER PR; ¶64) electrically connected to the first source/drain pattern; a second active contact (Fig. 3D, AC OVER NR; ¶64) electrically connected to the second source/drain pattern; and an insulating structure (Fig. 3D, 110/ST; ¶35/42) disposed between the first and second active contacts, wherein the insulating structure includes a first insulating layer (Fig. 3D, ST; ¶35) and a second insulating layer (Fig. 3D, 110; ¶ 42) disposed on the first insulating layer, wherein the second insulating layer comprises: a first surface in contact with the first insulating layer; and a second surface in contact with the first and second active contacts. Regarding claim 18, Ding discloses the semiconductor device of claim 13, wherein a level of the first surface (Fig. 3D, bottom of 110; ¶ 42) is lower than a level of the first (Fig. 3D, AC OVER PR; ¶64) and second (Fig. 3D, AC OVER NR; ¶64) active contacts. Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim(s) 2 is/are rejected under 35 U.S.C. 103 as being unpatentable over Ding et al. (US-20220271045-A1; Ding) in view of Deepak et al. (US-20180130786-A1; Deepak). Regarding claim 2, Ding discloses the semiconductor device of claim 1, but is silent on further comprising: a third active pattern disposed between the first active pattern and the second active pattern; and an intervening source/drain pattern disposed on the third active pattern, wherein the intervening source/drain pattern is spaced apart from the first and second active contacts. Deepak discloses first (Fig. 4, PR2; ¶57), second (Fig. 4, NR; ¶57), and third (Fig. 4, PR1; ¶57) active patterns, where the third pattern (Fig. 4, PR1; ¶57) is between first and second patterns without sharing active contacts (Fig. 4,AC; ¶57). Before the effective filing date of the invention, it would have been obvious to one having ordinary skill in the art to add a third active pattern for the benefit of increased reliability and multi-functional ability. object Allowable Subject Matter Claims 3-5, 9-12,14-17 objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Claim 4 is objected to due to dependence on claim 3. Claims 10-12 are objected to due to dependence on claim 9. Claims 15-17 are objected to due to dependence on claim 14. The following is an examiner’s statement of reasons for allowance, which paraphrases and summarizes the claimed invention without intending to be limited, wherein the legally defined scope of the claimed invention is defined by the allowed claims themselves in view of the written description under 35 USC 112. This statement is not intended to necessarily state all the reasons for allowance or all the details why the claims are allowed and has not been written to specifically or impliedly state that all the reasons for allowance are set forth (MPEP 1302.14). Regarding claim 3, the references of the Prior Art of record and considered pertinent to the applicant's disclosure and to the examiner’s knowledge does not teach or render obvious, at least to the skilled artisan, the instant invention regarding: " wherein the first insulating layer comprises a curved surface in contact with the intervening source/drain pattern.”, as recited in Claim 3, with the remaining features. Regarding claim 5, the references of the Prior Art of record and considered pertinent to the applicant's disclosure and to the examiner’s knowledge does not teach or render obvious, at least to the skilled artisan, the instant invention regarding: " wherein the intervening source/drain pattern comprises an upper portion in contact with the first insulating layer, and the upper portion of the intervening source/drain pattern is disposed between the first and second active contacts.”, as recited in Claim 5, with the remaining features. Regarding claim 9, the references of the Prior Art of record and considered pertinent to the applicant's disclosure and to the examiner’s knowledge does not teach or render obvious, at least to the skilled artisan, the instant invention regarding: " wherein the first insulating layer comprises a curved surface in contact with the second interlayer insulating layer.”, as recited in Claim 9, with the remaining features. Regarding claim 14, the references of the Prior Art of record and considered pertinent to the applicant's disclosure and to the examiner’s knowledge does not teach or render obvious, at least to the skilled artisan, the instant invention regarding: " further comprising: a third active pattern disposed between the first active pattern and the second active pattern; and a first intervening source/drain pattern disposed on the third active pattern, wherein the first insulating layer includes a first curved surface in contact with the first intervening source/drain pattern.”, as recited in Claim 14, with the remaining features. Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.” Claims 19-20 are allowed. The following is an examiner’s statement of reasons for allowance, which paraphrases and summarizes the claimed invention without intending to be limiting, wherein the legally defined scope of the claimed invention is defined by the allowed claims themselves in view of the written description under 35 USC 112. This statement is not intended to necessarily state all the reasons for allowance or all the details why the claims are allowed and has not been written to specifically or impliedly state that all the reasons for allowance are set forth (MPEP 1302.14). Regarding claim 19, the references of the Prior Art of record and considered pertinent to the applicant's disclosure and to the examiner’s knowledge does not teach or render obvious, at least to the skilled artisan, the instant invention regarding: " a curved surface in contact with the first and second interlayer insulating layers; and a connection surface that connects the inner surface to the curved surface,”, as recited in Claim 19, with the remaining features. Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.” Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to LAWRENCE C TYNES JR. whose telephone number is (571)270-7606. The examiner can normally be reached 9AM-5PM. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Zandra Smith can be reached at 571-272-2429. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /LAWRENCE C TYNES JR./Examiner, Art Unit 2899
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Prosecution Timeline

Jun 06, 2024
Application Filed
Aug 26, 2026
Non-Final Rejection mailed — §102, §103, §112 (current)

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Prosecution Projections

1-2
Expected OA Rounds
86%
Grant Probability
94%
With Interview (+8.8%)
2y 4m (~0m remaining)
Median Time to Grant
Low
PTA Risk
Based on 791 resolved cases by this examiner. Grant probability derived from career allowance rate.

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