Prosecution Insights
Last updated: September 17, 2026
Application No. 18/736,242

MICRO-DISPLAY LED CHIP STRUCTURE AND MANUFACTURING METHOD FOR THE SAME

Non-Final OA §103
Filed
Jun 06, 2024
Priority
Dec 08, 2021 — CN 202111489530.3 +1 more
Examiner
VALENZUELA, PATRICIA D
Art Unit
Tech Center
Assignee
Raysolve Optoelectronics (Suzhou) Co. Ltd.
OA Round
1 (Non-Final)
90%
Grant Probability
Favorable
1-2
OA Rounds
0m
Est. Remaining
92%
With Interview

Examiner Intelligence

Grants 90% — above average
90%
Career Allowance Rate
648 granted / 718 resolved
+30.3% vs TC avg
Minimal +2% lift
Without
With
+2.1%
Interview Lift
resolved cases with interview
Typical timeline
2y 2m
Avg Prosecution
80 currently pending
Career history
803
Total Applications
across all art units

Statute-Specific Performance

§101
1.4%
-38.6% vs TC avg
§103
67.5%
+27.5% vs TC avg
§102
16.1%
-23.9% vs TC avg
§112
6.4%
-33.6% vs TC avg
Black line = Tech Center average estimate • Based on career data from 718 resolved cases

Office Action

§103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Election/Restrictions Applicant’s election without traverse of claims 1-13 in the reply filed on 08/05/26 is acknowledged. Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim(s) 1-13 is/are rejected under 35 U.S.C. 103 as being unpatentable over Wi(USPGPUB DOCUMENT: 2017/0170152, hereinafter Wi) in view of Chen (USPGPUB DOCUMENT: 2018/0090058, hereinafter Chen). Re claim 1 Wi discloses in Fig 6 & 17 a micro-display Light-Emitting Diode (LED) chip structure, comprising: a first substrate(4010); and an LED semiconductor layer(4033/130) disposed on the first substrate(4010), wherein the LED semiconductor layer(4033/130) comprises a plurality of LED units(left/right/middle4050) arranged in an array, wherein the first substrate(4010) comprises a driving circuit(4020)[0162], the driving circuit(4020)[0162] is provided with a plurality of contacts(left/right/middle4020/4034), each contact(4020/4034) of the plurality of contacts(left/right/middle4020/4034) corresponds to an LED unit in the plurality of LED units(left/right/middle4050), the contact(4020/4034) is located in an orthographic projection region(since 4020/4034 has a layout or pattern, this may be interpreted as a projection), on the first substrate(4010), of the LED unit corresponding to the contact(4020/4034), and the contact(4020/4034) is electrically connected to the LED unit corresponding to the contact(4020/4034). Wi does not discloses adjacent LED units(left/right/middle4050) of the plurality of LED units(left/right/middle4050) are capable of being driven independently, Chen discloses adjacent LED units of the plurality of LED units are capable of being driven independently[claim 1], It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to apply the teachings of Sanders to the teachings of Sukumaran in order to minimize impacting the performance of the system [0004, Chen]. Re claim 2 Wi and Chen disclose the micro-display LED chip structure according to claim 1, wherein the contact(4020/4034) is located in a central region of the orthographic projection region, on the first substrate(4010), of the LED unit corresponding to the contact(4020/4034). Re claim 3 Wi and Chen disclose the micro-display LED chip structure according to claim 1, wherein the LED semiconductor layer(4033/130) comprises a first doping type semiconductor layer, an active layer and a second doping type semiconductor layer which are sequentially stacked on the first substrate(4010), a through hole corresponding to a position of the contact(4020/4034) is provided on the LED semiconductor layer(4033/130), and the through hole penetrates through the LED semiconductor layer(4033/130), wherein the micro-display LED chip structure further comprises: a passivation layer disposed on the second doping type semiconductor layer, wherein the passivation layer further covers a sidewall of the through hole, the passivation layer is provided with a first opening and a second opening, the first opening exposes the contact(4020/4034), and the second opening exposes the second doping type semiconductor layer; and an electrode layer disposed on the passivation layer and covering the first opening and the second opening, wherein the electrode layer is electrically connected to the contact(4020/4034) through thefirst opening, and is electrically connected to the second doping type semiconductor layer through the second opening. Re claim 4 Wi and Chen disclose the micro-display LED chip structure according to claim 3, wherein the LED unit is provided with a step structure, and the adjacent LED units(left/right/middle4050) are electrically isolated by the step structure to enable the adjacent LED units(left/right/middle4050) to be driven independently. Re claim 5 Wi and Chen disclose the micro-display LED chip structure according to claim 4, wherein the step structure is formed on the second doping type semiconductor layer, a height of the step structure is greater than or equal to a thickness of the second doping type semiconductor layer and less than a thickness of the LED semiconductor layer(4033/130), and the step structure at least electrically isolates second doping type semiconductor layers corresponding to the adjacent LED units(left/right/middle4050). Re claim 6 Wi and Chen disclose the micro-display LED chip structure according to claim 4, wherein the step structure is formed on the second doping type semiconductorlayer, a height of the step structure is equal to a thickness of the LED semiconductorlayer, and the step structure electrically isolates active layers corresponding to the adjacent LED units(left/right/middle4050), and electrically isolates first doping type semiconductor layers corresponding to the adjacent LED units(left/right/middle4050). Re claim 7 Wi and Chen disclose the micro-display LED chip structure according to claim 3, wherein an isolation material layer(318 of Chen) is provided between the adjacent LED units(left/right/middle4050), and the adjacent LED units(left/right/middle4050) are electrically isolated by the isolation material layer(318 of Chen) to enable the adjacent LED units(left/right/middle4050) to be driven independently. Re claim 8 Wi and Chen disclose the micro-display LED chip structure according to claim 7, wherein the isolation material layer(318 of Chen) is formed in the second doping type semiconductor layer, a thickness of the isolation material layer(318 of Chen) is greater than or equal to a thickness of the second doping type semiconductor layer, and the isolation material layer(318 of Chen) at least electrically isolates second doping type semiconductor layers corresponding to the adjacent LED units(left/right/middle4050). Re claim 9 Wi and Chen disclose the micro-display LED chip structure according to claim 8, wherein a materialof the isolation material layer(318 of Chen) comprises an ion implantation material, and the ion implantation material comprises any one or a combination of at least two of hydrogen, helium, nitrogen, oxygen, fluorine, magnesium, silicon, and argon. Re claim 10 Wi and Chen disclose the micro-display LED chip structure according to claim 3, wherein first doping type semiconductor layers corresponding to the plurality of LED units(left/right/middle4050) are a common first doping type semiconductor layer. Re claim 11 Wi and Chen disclose the micro-display LED chip structure according to claim 3, wherein one of the first doping type semiconductor layer and the second doping type semiconductor layer is a P-type semiconductor layer, and the other of the first doping type semiconductor layer and the second doping type semiconductor layer is an N-type semiconductor layer(153/152). Re claim 12 Wi and Chen disclose the micro-display LED chip structure according to claim 3, wherein a bonding layer is disposed between the first substrate(4010) and the first doping type semiconductor layer. Re claim 13 Wi and Chen disclose the micro-display LED chip structure according to claim 12, wherein the bonding layer is provided with an etched hole at a position corresponding to the contact(4020/4034) and the first opening, and theclectrode layerelectrically connects the second doping type semiconductor layer to the contact(4020/4034) through the first opening and the etched hole. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to PATRICIA D VALENZUELA whose telephone number is (571)272-9242. The examiner can normally be reached Monday-Friday 10am-6pm EST. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, William Partridge can be reached at 571-270-1402. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /PATRICIA D VALENZUELA/Primary Examiner, Art Unit 2812
Read full office action

Prosecution Timeline

Jun 06, 2024
Application Filed
Aug 26, 2026
Non-Final Rejection mailed — §103 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
90%
Grant Probability
92%
With Interview (+2.1%)
2y 2m (~0m remaining)
Median Time to Grant
Low
PTA Risk
Based on 718 resolved cases by this examiner. Grant probability derived from career allowance rate.

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