DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 1-20 are provisionally rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-20 of copending Application No. 18/951528 (reference application). Although the claims at issue are not identical, they are not patentably distinct from each other because the claims of the copending application contain one extra limitation but otherwise are identical to the claims of the instant application.
This is a provisional nonstatutory double patenting rejection because the patentably indistinct claims have not in fact been patented.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 11-15 and 18 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Mun (U.S. PGPub 2024/0120280).
Regarding claim 11, Mun teaches a package (Fig. 9, [0090]), comprising:
a metallization portion (110, [0027]),
an integrated device coupled to the metallization portion (120, [0038]-[0040]),
a substrate (160, [0047]),
a plurality of post interconnects coupled to the substrate and the metallization portion (155, [0045]); and
an encapsulation layer coupled to the metallization portion, wherein the encapsulation layer at least partially encapsulates the integrated device, the plurality of post interconnects and the substrate (151, [0042]-[0043]).
Regarding claim 12, Mun teaches wherein the substrate includes an interposer (Mun, Fig. 9, 160, [0046]-[0047]).
Regarding claim 13, Mun teaches wherein the substrate comprises at least one substrate dielectric layer and a plurality of interconnects (161/163, [0047]-[0049]), and wherein the metallization portion comprises at least one dielectric layer and a plurality of metallization interconnects (111/113, [0027]-[0029]).
Regarding claim 14, the combination of Mun and Chen teaches wherein the plurality of post interconnects are coupled to the plurality of interconnects and the plurality of metallization interconnects (Fig. 9).
Regarding claim 15, Mun teaches another integrated device or another package, coupled to the substrate through a plurality of solder interconnects (181, 183, [0055]-[0056]).
Regarding claim 18, Mun teaches a heat sink, wherein the integrated device is coupled to the heat sink through a thermal interface material (TIM) and/or an adhesive (Mun, 185, 187, [0058]).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1-5 and 8 are rejected under 35 U.S.C. 103 as being unpatentable over Mun (U.S. PGPub 2024/0120280) in view of Chen (U.S. PGPub 2022/0084925).
Regarding claim 1, Mun teaches a package (Fig. 9, [0090]), comprising:
a metallization portion (110, [0027]),
an integrated device coupled to the metallization portion (120, [0038]-[0040]),
a substrate (160, [0047]),
a plurality of vertical connection conductors coupled to the substrate and the metallization portion (155, [0045]); and
an encapsulation layer coupled to the metallization portion, wherein the encapsulation layer at least partially encapsulates the integrated device, the plurality of vertical connection conductors and the substrate (151, [0042]-[0043]).
Mun does not explicitly teach wherein the plurality of vertical connection conductors are a plurality of wire bonds. Mun is silent on the method of formation of the vertical connection conductors.
Chen teaches wherein a plurality of vertical connection conductors coupling two redistribution layers are a plurality of wire bonds (500, [0058]-[0059]).
Therefore it would have been obvious to a person having ordinary skill in the art before the time of the effective filing date to combine the teachings of Chen with Mun such that the plurality of vertical connection conductors are a plurality of wire bonds for the purpose of implementing the vertical connection conductors of Mun according to a known suitable method (Chen, [0058]).
Regarding claim 2, the combination of Mun and Chen teaches wherein the substrate includes an interposer (Mun, Fig. 9, 160, [0046]-[0047]). It would have been obvious to a person having ordinary skill in the art to further combine the teachings of Mun and Chen for the reasons set forth in the rejection of claim 1.
Regarding claim 3, the combination of Mun and Chen teaches wherein the substrate comprises at least one substrate dielectric layer and a plurality of interconnects (Mun, 161/163, [0047]-[0049]), and wherein the metallization portion comprises at least one dielectric layer and a plurality of metallization interconnects (Mun, 111/113, [0027]-[0029]). It would have been obvious to a person having ordinary skill in the art to further combine the teachings of Mun and Chen for the reasons set forth in the rejection of claim 1.
Regarding claim 4, the combination of Mun and Chen teaches wherein the plurality of wire bonds are coupled to the plurality of interconnects and the plurality of metallization interconnects (Mun, Fig. 9; Chen, Fig. 21). It would have been obvious to a person having ordinary skill in the art to further combine the teachings of Mun and Chen for the reasons set forth in the rejection of claim 1.
Regarding claim 5, the combination of Mun and Chen teaches another integrated device or another package, coupled to the substrate through a plurality of solder interconnects (Mun, 181, 183, [0055]-[0056]). It would have been obvious to a person having ordinary skill in the art to further combine the teachings of Mun and Chen for the reasons set forth in the rejection of claim 1.
Regarding claim 8, the combination of Mun and Chen teaches a heat sink, wherein the integrated device is coupled to the heat sink through a thermal interface material (TIM) and/or an adhesive (Mun, 185, 187, [0058]). It would have been obvious to a person having ordinary skill in the art to further combine the teachings of Mun and Chen for the reasons set forth in the rejection of claim 1.
Claims 6-7 are rejected under 35 U.S.C. 103 as being unpatentable over Mun (U.S. PGPub 2024/0120280) in view of Chen (U.S. PGPub 2022/0084925) and further in view of Kim (U.S. PGPub 2022/0102236).
Regarding claim 6, the combination of Mun and Chen does not explicitly teach wherein the integrated device is coupled to the substrate through a thermal interface material (TIM) and/or an adhesive.
Kim teaches wherein an integrated device is coupled to a substrate comprising heat dissipation vias through an adhesive layer (Fig. 1B, 120, 190, 199, 130, [0034], [0043], [0047]).
Therefore it would have been obvious to a person having ordinary skill in the art before the time of the effective filing date to combine the teachings of Kim with Mun and Chen such that the integrated device is coupled to the substrate through a thermal interface material (TIM) and/or an adhesive for the purpose of improving adhesion (Kim, [0034]).
Regarding claim 7, the combination of Mun, Chen, and Kim teaches wherein the substrate comprises a plurality of heat sink interconnects configured as a heat sink (Mun, 172, [0091]-[0092]; Kim, [0047]). It would have been obvious to a person having ordinary skill in the art to further combine the teachings of Mun, Chen, and Kim for the reasons set forth in the rejection of claim 6.
Claims 9-10 are rejected under 35 U.S.C. 103 as being unpatentable over Lin (U.S. PGPub 2025/0096066) in view of Lee (U.S. PGPub 2023/0069490).
Regarding claim 9, Lin teaches a package (Fig. 4, [0061]), comprising:
a metallization portion (100, [0062]),
a first integrated device coupled to the metallization portion (300, [0063]),
a second integrated device (500, [0062]),
a heat sink coupled to the first integrated device through a thermal interface material (TIM) and/or an adhesive (400/430, [0064]),
a plurality of package interconnects coupled to the second integrated device and the metallization portion (380, [0064]), and
an encapsulation layer coupled to the metallization portion, wherein the encapsulation layer at least partially encapsulates the first integrated device, the plurality of package interconnects and the heat sink (391, [0064]).
Lin does not explicitly teach wherein the encapsulation layer at least partially encapsulates the second integrated device.
Lee teaches a package (Fig. 6, [0107]), comprising a metallization portion (100, [0108]), a first integrated device coupled to the metallization portion (210, [0108]), a second integrated device (220, [0108]), a plurality of package interconnects coupled to the second integrated device and the metallization portion (250, [0118]), and an encapsulation layer coupled to the metallization portion, wherein the encapsulation layer at least partially encapsulates the first integrated device, the second integrated device, and the plurality of package interconnects (300, [0103]).
Therefore it would have been obvious to a person having ordinary skill in the art before the time of the effective filing date to combine the teachings of Lee with Lin such that the encapsulation layer at least partially encapsulates the second integrated device because the prior art teaches every element, a person of ordinary skill could have combined them as claimed and in combination each element performs the same function as it does separately, and the combination w have yielded predictable results to one of ordinary skill in the art before the time of the invention. See MPEP 2143(I)A.
Regarding claim 10, the combination of Lin and Lee teaches wherein the plurality of package interconnects comprise a plurality of wire bonds or a plurality of post interconnects (Lin, [0069]). It would have been obvious to a person having ordinary skill in the art to further combine the teachings of Lin and Lee for the reasons set forth in the rejection of claim 9.
Claims 16-17 are rejected under 35 U.S.C. 103 as being unpatentable over Mun (U.S. PGPub 2024/0120280) in view of Kim (U.S. PGPub 2022/0102236).
Regarding claim 16, Mun does not explicitly teach wherein the integrated device is coupled to the substrate through a thermal interface material (TIM) and/or an adhesive.
Kim teaches wherein an integrated device is coupled to a substrate comprising heat dissipation vias through an adhesive layer (Fig. 1B, 120, 190, 199, 130, [0034], [0043], [0047]).
Therefore it would have been obvious to a person having ordinary skill in the art before the time of the effective filing date to combine the teachings of Kim with Mun such that the integrated device is coupled to the substrate through a thermal interface material (TIM) and/or an adhesive for the purpose of improving adhesion (Kim, [0034]).
Regarding claim 17, the combination of Mun and Kim teaches wherein the substrate comprises a plurality of heat sink interconnects configured as a heat sink (Mun, 172, [0091]-[0092]; Kim, [0047]). It would have been obvious to a person having ordinary skill in the art to further combine the teachings of Mun and Kim for the reasons set forth in the rejection of claim 6.
Claim 20 is rejected under 35 U.S.C. 103 as being unpatentable over Mun (U.S. PGPub 2024/0120280) in view of Lin 2016 (U.S. PGPub 2016/0322330).
Regarding claim 20, Mun does not explicitly teach wherein the package is incorporated in a device from a group consisting one of a music player, a video player, an entertainment unit, a navigation device, a communications device, a mobile device, a mobile phone, a smartphone, a personal digital assistant, a fixed location terminal, a tablet computer, a computer, a wearable device, a laptop computer, a server, an internet of things (IoT) device, and a device in an automotive vehicle.
Lin 2016 teaches wherein an integrated device package may be used for mobile computing, a wearable device, or an IoT device ([0012]).
Therefore it would have been obvious to a person having ordinary skill in the art before the time of the effective filing date to combine the teachings of Lin 2016 with Mun such that the package is incorporated in a device from a group consisting one of a music player, a video player, an entertainment unit, a navigation device, a communications device, a mobile device, a mobile phone, a smartphone, a personal digital assistant, a fixed location terminal, a tablet computer, a computer, a wearable device, a laptop computer, a server, an internet of things (IoT) device, and a device in an automotive vehicle for the purpose of utilizing the device of Mun in an electronic device (Mun, [0003]).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ALIA SABUR whose telephone number is (571)270-7219. The examiner can normally be reached M-F 9:30-5:30.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Christine S. Kim can be reached at 571-272-8458. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/ALIA SABUR/ Primary Examiner, Art Unit 2812
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