THIN FILM TRANSISTOR SUBSTRATE, MANUFACTURING METHOD THEREOF AND DISPLAY APPARATUS COMPRISING THE SAME

§102 §103

DETAILED ACTION Election/Restrictions A restriction requirement was mailed on 6/15/26 Applicant’s election without traverse of Group II (device claims 1-18 and 22-37) in the reply filed on 8/14/26 is acknowledged. Claims 19-21 are withdrawn. Foreign Priority Acknowledgment is made of applicant’s claim for foreign priority under 35 U.S.C. 119 (a)-(d). Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55. Information Disclosure Statement The information disclosure statement (IDS) submitted on 8/5/25 is in compliance with the provisions of 37 CFR 1.97 and 1.98. Accordingly, the information disclosure statement has been considered by the examiner. The information disclosure statement (IDS) submitted on 2/14/25 is in compliance with the provisions of 37 CFR 1.97 and 1.98. Accordingly, the information disclosure statement has been considered by the examiner. The information disclosure statement (IDS) submitted on 6/6/24 is in compliance with the provisions of 37 CFR 1.97 and 1.98. Accordingly, the information disclosure statement has been considered by the examiner. Specification The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed. The following title is suggested: Oxide semiconductor transistor channels having amorphous and crystalline layers The abstract of the disclosure is objected to because it exceeds the length of 150 words. See MPEP § 608. Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102, some of which form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention. (a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention. Claim(s) 22-24 is/are rejected under 35 U.S.C. 102(a)(1) and 102(a)(2) as being anticipated by US 2014/0042437 A1 (“Yamazaki 437”). Yamazaki 437 teaches, for example: PNG media_image1.png 507 641 media_image1.png Greyscale PNG media_image2.png 307 275 media_image2.png Greyscale Yamazaki 437 teaches: 22. A thin film transistor (see e.g. para 18; also see e.g. Fig. 5B) comprising: an active layer (e.g. “oxide semiconductor stack” in para 18; e.g. 408 in Fig. 5B); and a gate electrode (e.g. “gate electrode overlapping…”, in para 18; e.g. 402 and/or 416 in Fig. 5B) spaced apart from the active layer and overlapping at least part of the active layer; wherein the active layer includes: a first oxide semiconductor layer (e.g. “first oxide semiconductor” in para 18; e.g. 408a in Fig. 5B, also see e.g. para 101, 123, etc.); a second oxide semiconductor layer (e.g. “second oxide semiconductor” in para 18; e.g. 408b in Fig. 5B, also see e.g. 101, 124, etc.) disposed on the first oxide semiconductor layer; and a third oxide semiconductor layer (e.g. “third oxide semiconductor” in para 18; e.g. 408c in Fig. 5B, also see e.g. para 101, 125, etc.) disposed on the second oxide semiconductor layer; and the first oxide semiconductor layer and the third oxide semiconductor have an amorphous structure, and the second oxide semiconductor layer has a crystalline structure (see e.g. para 18 “The oxide semiconductor stack includes at least a first oxide semiconductor layer having an amorphous structure, a second oxide semiconductor layer having a crystalline structure over the first oxide semiconductor layer, and a third oxide semiconductor layer having an amorphous structure over the second oxide semiconductor layer”; see also para 101 “the oxide semiconductor stack 408 includes a first oxide semiconductor layer 408a having an amorphous structure, a second oxide semiconductor layer 408b having a crystalline structure over the first oxide semiconductor layer 408a, and a third oxide semiconductor layer 408c over the second oxide semiconductor layer 408b”; see e.g. para 18 ). 23. The thin film transistor of claim 22, wherein the first oxide semiconductor layer and the third oxide semiconductor layer each include at least one of (see e.g. para 118, wherein 408a and 408c may be IGZO) an IZO (InZnO)-based, an IGZO (InGaZnO)-based, an IGZTO (InGaZnSnO)-based, a GZTO (GaZnSnO)-based, or a GZO (GaZnO)-based oxide semiconductor material, and the second oxide semiconductor layer includes at least one of an IZO (InZnO)-based oxide semiconductor material, in which a concentration of In is 50% or more compared to a total concentration of In and Zn (see e.g. para 120 and 124, wherein 408b may be IZO with a ratio of In:Zn of 2:1, so the concentration of In to the concentration of In+Zn is 2/3), an IGO (InGaO)-based oxide semiconductor material, in which a concentration of In is 70% or more compared to a total concentration of In and Ga, an IGZO (InGaZnO)-based oxide semiconductor material, in which a concentration of In is 50% or more compared to a total concentration of In, Ga, and Zn, an ITO (InSnO)-based oxide semiconductor material, in which a concentration of In is 80% or more compared to a total concentration of In and Sn, an IGZTO (InGaZnSnO)-based oxide semiconductor material, in which a sum of concentration of In and Sn is 45% or more compared to a total concentration of In, Ga, Zn, and Sn, and an ITZO (InSnZnO)-based oxide semiconductor material, in which a sum of concentration of In and Sn is 45% or more compared to a total concentration of In, Sn, Zn based on atomic number. 24. The thin film transistor of claim 23, wherein the second oxide semiconductor layer further includes a dopant in the oxide semiconductor material, and the dopant includes at least one of beryllium (Be), boron (B), carbon (C), aluminum (C), aluminum (Al), silicon (Si), iron (Si), calcium (Ca), tin (Sn), titanium (Ti), tantalum (Ta), vanadium (V), yttrium (Y), zirconium (Zr), hafnium (Hf), lanthanum (La), or germanium (Ge) (see e.g. para 60 and 62, wherein a silicon or carbon impurity donor may be present). Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim(s) 1-7, 16-18, 25-26, and 35-37 is/are rejected under 35 U.S.C. 103 as being unpatentable over US 2014/0042437 A1 (“Yamazaki 437”). Yamazaki 437 teaches and/or would have suggested as obvious to one of ordinary skill in the art at the time of invention: 1. A thin film transistor structure (see e.g. Fig. 6A; and single transistors as shown in e.g. Figs. 2B, 5B, etc.; in Fig. 6A, two transistors 803 and 804, each having an oxide semiconductor stack and being “similar” to the transistor of earlier embodiments exist in a logic circuit, see e.g. para 209) comprising: a first thin film transistor (e.g. a transistor such as shown in e.g. Fig. 5B) and a second thin film transistor (e.g. another transistor such as shown in e.g. Fig. 5B) on a base substrate (e.g. 400, see e.g. Fig. 5B), wherein the first thin film transistor includes: a first active layer (e.g. “oxide semiconductor stack” in para 18; e.g. 408 in Fig. 5B) disposed on the base substrate; and a first gate electrode (e.g. “gate electrode overlapping…”, in para 18; e.g. 402 and/or 416 in Fig. 5B) spaced apart from the first active layer and overlapping at least part of the first active layer; the second thin film transistor includes: a second active layer (e.g. “oxide semiconductor stack” in para 18; e.g. 408 in Fig. 5B) disposed on the base substrate; and a second gate electrode (e.g. “gate electrode overlapping…”, in para 18; e.g. 402 and/or 416 in Fig. 5B) spaced apart from the second active layer and overlapping at least part of the second active layer; the first active layer includes: a first oxide semiconductor layer (e.g. “first oxide semiconductor” in para 18; e.g. 408a in Fig. 5B, also see e.g. para 101, 123, etc.); and a second oxide semiconductor layer (e.g. “second oxide semiconductor” in para 18; e.g. 408b in Fig. 5B, also see e.g. 101, 124, etc.) disposed on the first oxide semiconductor layer; the second active layer includes: a first oxide semiconductor layer (e.g. “first oxide semiconductor” in para 18; e.g. 408a in Fig. 5B, also see e.g. para 101, 123, etc.); a second oxide semiconductor layer (e.g. “second oxide semiconductor” in para 18; e.g. 408b in Fig. 5B, also see e.g. 101, 124, etc.) disposed on the first oxide semiconductor layer; a third oxide semiconductor layer (e.g. “third oxide semiconductor” in para 18; e.g. 408c in Fig. 5B, also see e.g. para 101, 125, etc.) disposed on the second oxide semiconductor layer; the first oxide semiconductor layer of the first active layer has an amorphous structure, the second oxide semiconductor layer of the first active layer has a crystalline structure, the first oxide semiconductor layer and the third oxide semiconductor layer of the second active layer have an amorphous structure, and the second oxide semiconductor layer of the second active layer has a crystalline structure (see e.g. para 18 “The oxide semiconductor stack includes at least a first oxide semiconductor layer having an amorphous structure, a second oxide semiconductor layer having a crystalline structure over the first oxide semiconductor layer, and a third oxide semiconductor layer having an amorphous structure over the second oxide semiconductor layer”; see also para 101 “the oxide semiconductor stack 408 includes a first oxide semiconductor layer 408a having an amorphous structure, a second oxide semiconductor layer 408b having a crystalline structure over the first oxide semiconductor layer 408a, and a third oxide semiconductor layer 408c over the second oxide semiconductor layer 408b”; see e.g. para 18 ). Combining two embodiments (see e.g. Fig. 6A; and single transistors as shown in e.g. Figs. 2B, 5B) disclosed adjacent to each other in a prior art patent does not require a leap of inventiveness (Boston Scientific Scimed, Inc. v. Cordis Corp., No. 08-1073 (Fed. Cir. Jan. 15, 2009)), especially given the disclosure that the transistors as “similar” to those previously disclosed. “Like the combination of two side-by-side embodiments in Boston Scientific, we view the combination of elements from the optimal and sub-optimal embodiments as a ‘predictable variation’ that does not ‘require a leap of inventiveness.’ ” Paice LLC v. Ford Motor Co., 2016-1412, 21 (Fed. Cir. Mar. 7, 2017). It has been established that “the [obviousness] analysis need not seek out precise teachings directed to the specific subject matter of the challenged claim” because the Office or “a court can take account of the inferences and creative steps that a person of ordinary skill in the art would employ.” KSR Int’ Co. v. Teleflex Inc., 550 U.S. 398, 418 (2007). It is also well settled that a reference stands for all of the specific teachings thereof as well as the inferences one of ordinary skill in the art would have reasonably been expected to draw therefrom. See In re Fritch, 972 F.2d 1260, 1264-65 (Fed. Cir. 1992). 2. The thin film transistor structure of claim 1, wherein the first oxide semiconductor layer of the first active layer is made of a same material as the first oxide semiconductor layer of the second active layer (given the teachings that the transistors are “similar”, it would have been obvious that they could be identical in at least the materials of the channel layers). 3. The thin film transistor structure of claim 1, wherein the second oxide semiconductor layer of the first active layer is made of a same material as the second oxide semiconductor layer of the second active layer and has a same crystalline structure (given the teachings that the transistors are “similar”, it would have been obvious that they could be identical in at least the materials of the channel layers).. 4. The thin film transistor substrate of claim 1, wherein the first oxide semiconductor layer of the first active layer, the first oxide semiconductor layer of the second active layer, and the third oxide semiconductor layer of the second active layer each includes at least one of (see e.g. para 118, wherein 408a and 408c may be IGZO) an IZO (InZnO)-based, an IGZO (InGaZnO)-based, an IGZTO (InGaZnSnO)-based, a GZTO (GaZnSnO)-based, or a GZO (GaZnSnO)-based oxide semiconductor material, and the second oxide semiconductor layer of the first active layer and the second oxide semiconductor layer of the second active layer each includes at least one of an IZO (InZnO)-based oxide semiconductor material, in which a concentration of In is 50% or more compared to a total concentration of In and Zn (see e.g. para 120 and 124, wherein 408b may be IZO with a ratio of In:Zn of 2:1, so the concentration of In to the concentration of In+Zn is 2/3), an IGO (InGaO)-based, in which a concentration of In is 70% or more compared to a total concentration of In and Ga, an IGZO (InGaZnO)-based oxide semiconductor material, in which a concentration of In is 50% or more compared to a total concentration of In, Ga, and Zn, an ITO (InSnO)-based oxide semiconductor material, in which a concentration of In is 80% or more compared to a total concentration of In and Sn, an IGZTO (InGaZnSnO)-based oxide semiconductor material, in which a sum of concentration of In and Sn is 45% or more compared to a total concentration of In, Ga, Zn, and Sn, or an ITZO (InSnZnO)-based oxide semiconductor material, in which a sum of concentration of In and Sn is 45% or more compared to the total concentration of In, Sn, Zn based on atomic number. 5. The thin film transistor structure of claim 4, wherein each of the second oxide semiconductor layer of the first active layer and the second oxide semiconductor layer of the second active layer further includes a dopant in the oxide semiconductor material, and the dopant includes at least one of beryllium (Be), boron (B), carbon (C), aluminum (Al), silicon (Si), iron (Fe), calcium (Ca), tin (Sn), titanium (Ti), tantalum (Ta), vanadium (V), yttrium (Y), zirconium (Zr), hafnium (Hf), lanthanum (La), or germanium (Ge) (see e.g. para 60 and 62, wherein a silicon or carbon impurity donor may be present). 6. The thin film transistor structure of claim 5, wherein the dopant included in the second oxide semiconductor layer of the first active layer has a concentration in a range from 0.1 to 10 atomic%, inclusive, based on a total number of atoms of the second oxide semiconductor layer of the first active layer, and the dopant included in the second oxide semiconductor layer of the second active layer has a concentration in a range from 0.1 to 10 atomic%, inclusive, based on a total number of atoms of the second oxide semiconductor layer of the second active layer (see e.g. para 20-21, 58, 62, wherein the dopant concentration is lower or equal to 3*1018 cm-3). It has been held that when claimed ranges “overlap or lie inside ranges disclosed by the prior art" a prima facie case of obviousness exists. In re Wertheim, 541 F.2d 257, 191 USPQ 90 (CCPA 1976); In re Woodruff, 919 F.2d 1575, 16 USPQ2d 1934 (Fed. Cir. 1990). It has been held that when claimed ranges and disclosed ranges do not overlap, but “are close enough such that one skilled in the art would have expected them to have the same properties”, a prima facie case of obviousness exists. In re Peterson, 315 F.3d 1325, 1330, 65 USPQ2d 1379,1382-83 (Fed. Cir. 2003), citing In re Geisler, 116 F.3d 1465, 43 USPQ2d 1362 (Fed. Cir. 1997); In re Woodruff, 919 F.2d 1575, 16 USPQ2d 1934 (Fed. Cir. 1990); Titanium Metals Corp. v. Banner, 778 F.2d 775, 227 USPQ 773 (Fed. Cir. 1985); and In re Malagari, 499 F.2d 1297, 182 USPQ 549 (CCPA 1974)). See also MPEP 2144.05. Applicant has not disclosed that the claimed range is for a particular unobvious purpose, produces an unexpected result, or is otherwise critical. To overcome a prima facie case of obviousness, Applicant must show factual evidence that the particular range is critical or achieves unexpected results relative to the prior art range. See, e.g., Gardner v. TEC Sys., Inc., 725 F.2d 1338, 220 USPQ 777 (Fed.Cir. 1984); In re Boesch, 617 F.2d 272, 205 USPQ 215 (CCPA 1980); In re Ornitz, 351 F.2d 1013, 147 USPQ 283 (CCPA 1965); In re Aller, 220 F.2d 454, 105 USPQ 233 (CCPA 1955). It is clearly within the skill level of one of ordinary skill in the art to discover the claimed range given the overlap of the claimed and disclosed range. It has been established that the Office or “a court can take account of the inferences and creative steps that a person of ordinary skill in the art would employ.” KSR Int’ Co. v. Teleflex Inc., 550 U.S. 398, 418 (2007). It is also well settled that a reference stands for all of the specific teachings thereof as well as the inferences one of ordinary skill in the art would have reasonably been expected to draw therefrom. See In re Fritch, 972 F.2d 1260, 1264-65 (Fed. Cir. 1992). 7. The thin film transistor structure of claim 1, wherein the first oxide semiconductor layer of the first active layer and the first oxide semiconductor layer of the second active layer each have a thickness in a range from 1 to 10 nm, inclusive (see e.g. para 123, wherein the thickness may be 10-40 nm), the second oxide semiconductor layer of the first active layer and the second oxide semiconductor layer of the second active layer each have a thickness in a range from 10 to 50 nm, inclusive (see e.g. para 124, wherein the thickness may be 5-10 nm), and the third oxide semiconductor layer of the second active layer has a thickness in a range from 1 to 20 nm, inclusive (see e.g. para 125, wherein the thickness may be 10-40 nm). It has been held that when claimed ranges “overlap or lie inside ranges disclosed by the prior art" a prima facie case of obviousness exists. In re Wertheim, 541 F.2d 257, 191 USPQ 90 (CCPA 1976); In re Woodruff, 919 F.2d 1575, 16 USPQ2d 1934 (Fed. Cir. 1990). Applicant has not disclosed that the claimed ranges are for a particular unobvious purpose, produce an unexpected result, or are otherwise critical. To overcome a prima facie case of obviousness, Applicant must show factual evidence that the particular range is critical or achieves unexpected results relative to the prior art range. See, e.g., Gardner v. TEC Sys., Inc., 725 F.2d 1338, 220 USPQ 777 (Fed.Cir. 1984); In re Boesch, 617 F.2d 272, 205 USPQ 215 (CCPA 1980); In re Ornitz, 351 F.2d 1013, 147 USPQ 283 (CCPA 1965); In re Aller, 220 F.2d 454, 105 USPQ 233 (CCPA 1955). It is clearly within the skill level of one of ordinary skill in the art to discover the claimed range given the overlap of the claimed and disclosed range. It has been established that the Office or “a court can take account of the inferences and creative steps that a person of ordinary skill in the art would employ.” KSR Int’ Co. v. Teleflex Inc., 550 U.S. 398, 418 (2007). It is also well settled that a reference stands for all of the specific teachings thereof as well as the inferences one of ordinary skill in the art would have reasonably been expected to draw therefrom. See In re Fritch, 972 F.2d 1260, 1264-65 (Fed. Cir. 1992). It has been established that “the [obviousness] analysis need not seek out precise teachings directed to the specific subject matter of the challenged claim” because the Office or “a court can take account of the inferences and creative steps that a person of ordinary skill in the art would employ.” KSR Int’ Co. v. Teleflex Inc., 550 U.S. 398, 418 (2007). It is also well settled that a reference stands for all of the specific teachings thereof as well as the inferences one of ordinary skill in the art would have reasonably been expected to draw therefrom. See In re Fritch, 972 F.2d 1260, 1264-65 (Fed. Cir. 1992). 16. The thin film transistor structure of claim 1, wherein an s-factor of the second thin film transistor is greater than an s-factor of the first thin film transistor, and a carrier mobility of the first thin film transistor is greater than a carrier mobility of the second thin film transistor (see e.g. para 11, wherein if there are more trap states, they change the S-factor value and the carrier mobility; see e.g. para 54, where in Yamazaki 437 teaches that the first and third oxide layers suppress the traps; see e.g. para 55, wherein the carriers are trapped in localized states; hence one of ordinary skill in the art would recognize that differences in the two transistors will cause them to have different S-factor values and different mobilities, and because the locations of the transistors are not claimed, and because it is well known to have millions of transistors in memories and displays, one of ordinary skill in the art would understand that the transistors in an array will have slightly differing properties, thus resulting in some transistors having different s-factors and mobilities than others, leading to the claimed limitation.). It has been established that “the [obviousness] analysis need not seek out precise teachings directed to the specific subject matter of the challenged claim” because the Office or “a court can take account of the inferences and creative steps that a person of ordinary skill in the art would employ.” KSR Int’ Co. v. Teleflex Inc., 550 U.S. 398, 418 (2007). It is also well settled that a reference stands for all of the specific teachings thereof as well as the inferences one of ordinary skill in the art would have reasonably been expected to draw therefrom. See In re Fritch, 972 F.2d 1260, 1264-65 (Fed. Cir. 1992). 17. A display apparatus comprising the thin film transistor structure of claim 1 (see e.g. para 249-267 and Figs. 6A-11B). 18. The display apparatus of claim 17, further including a gate driver (see e.g. 916, see e.g. para 249) and a pixel driving circuit (see e.g. Figs. 6A-11B which contain many circuits used to control the pixels of the display; see e.g. “logic circuit” or “driver circuit”, e.g. para 244) on the base substrate, the first thin film transistor is included in the gate driver or is a switching transistor of the pixel driving circuit, and the second thin film transistor is a driving transistor of the pixel driving circuit (it would have been obvious to use the disclosed transistor in both circuits). 25. The thin film transistor of claim 24, wherein the dopant included in the second oxide semiconductor layer has a concentration in a range from 0.1 to 10 atomic%, inclusive, based on a total number of atoms in the second oxide semiconductor layer (see e.g. para 20-21, 58, 62, wherein the dopant concentration is lower or equal to 3*1018 cm-3). It has been held that when claimed ranges “overlap or lie inside ranges disclosed by the prior art" a prima facie case of obviousness exists. In re Wertheim, 541 F.2d 257, 191 USPQ 90 (CCPA 1976); In re Woodruff, 919 F.2d 1575, 16 USPQ2d 1934 (Fed. Cir. 1990). It has been held that when claimed ranges and disclosed ranges do not overlap, but “are close enough such that one skilled in the art would have expected them to have the same properties”, a prima facie case of obviousness exists. In re Peterson, 315 F.3d 1325, 1330, 65 USPQ2d 1379,1382-83 (Fed. Cir. 2003), citing In re Geisler, 116 F.3d 1465, 43 USPQ2d 1362 (Fed. Cir. 1997); In re Woodruff, 919 F.2d 1575, 16 USPQ2d 1934 (Fed. Cir. 1990); Titanium Metals Corp. v. Banner, 778 F.2d 775, 227 USPQ 773 (Fed. Cir. 1985); and In re Malagari, 499 F.2d 1297, 182 USPQ 549 (CCPA 1974)). See also MPEP 2144.05. Applicant has not disclosed that the claimed range is for a particular unobvious purpose, produces an unexpected result, or is otherwise critical. To overcome a prima facie case of obviousness, Applicant must show factual evidence that the particular range is critical or achieves unexpected results relative to the prior art range. See, e.g., Gardner v. TEC Sys., Inc., 725 F.2d 1338, 220 USPQ 777 (Fed.Cir. 1984); In re Boesch, 617 F.2d 272, 205 USPQ 215 (CCPA 1980); In re Ornitz, 351 F.2d 1013, 147 USPQ 283 (CCPA 1965); In re Aller, 220 F.2d 454, 105 USPQ 233 (CCPA 1955). It is clearly within the skill level of one of ordinary skill in the art to discover the claimed range given the overlap of the claimed and disclosed range. It has been established that the Office or “a court can take account of the inferences and creative steps that a person of ordinary skill in the art would employ.” KSR Int’ Co. v. Teleflex Inc., 550 U.S. 398, 418 (2007). It is also well settled that a reference stands for all of the specific teachings thereof as well as the inferences one of ordinary skill in the art would have reasonably been expected to draw therefrom. See In re Fritch, 972 F.2d 1260, 1264-65 (Fed. Cir. 1992). Re claim 26, Yamazaki 437 teaches and/or would have suggested as obvious to one of ordinary skill in the art at the time of invention: wherein the first oxide semiconductor layer has a thickness in a range from 1 to 10 nm, inclusive (see e.g. para 123, wherein the thickness may be 10-40 nm), the second oxide semiconductor layer has a thickness in a range from 10 to 50 nm, inclusive (see e.g. para 124, wherein the thickness may be 5-10 nm), and the third oxide semiconductor layer has a thickness in a range from 1 to 20 nm, inclusive (see e.g. para 125, wherein the thickness may be 10-40 nm). It has been held that when claimed ranges “overlap or lie inside ranges disclosed by the prior art" a prima facie case of obviousness exists. In re Wertheim, 541 F.2d 257, 191 USPQ 90 (CCPA 1976); In re Woodruff, 919 F.2d 1575, 16 USPQ2d 1934 (Fed. Cir. 1990). Applicant has not disclosed that the claimed ranges are for a particular unobvious purpose, produce an unexpected result, or are otherwise critical. To overcome a prima facie case of obviousness, Applicant must show factual evidence that the particular range is critical or achieves unexpected results relative to the prior art range. See, e.g., Gardner v. TEC Sys., Inc., 725 F.2d 1338, 220 USPQ 777 (Fed.Cir. 1984); In re Boesch, 617 F.2d 272, 205 USPQ 215 (CCPA 1980); In re Ornitz, 351 F.2d 1013, 147 USPQ 283 (CCPA 1965); In re Aller, 220 F.2d 454, 105 USPQ 233 (CCPA 1955). It is clearly within the skill level of one of ordinary skill in the art to discover the claimed range given the overlap of the claimed and disclosed range. It has been established that the Office or “a court can take account of the inferences and creative steps that a person of ordinary skill in the art would employ.” KSR Int’ Co. v. Teleflex Inc., 550 U.S. 398, 418 (2007). It is also well settled that a reference stands for all of the specific teachings thereof as well as the inferences one of ordinary skill in the art would have reasonably been expected to draw therefrom. See In re Fritch, 972 F.2d 1260, 1264-65 (Fed. Cir. 1992). It has been established that “the [obviousness] analysis need not seek out precise teachings directed to the specific subject matter of the challenged claim” because the Office or “a court can take account of the inferences and creative steps that a person of ordinary skill in the art would employ.” KSR Int’ Co. v. Teleflex Inc., 550 U.S. 398, 418 (2007). It is also well settled that a reference stands for all of the specific teachings thereof as well as the inferences one of ordinary skill in the art would have reasonably been expected to draw therefrom. See In re Fritch, 972 F.2d 1260, 1264-65 (Fed. Cir. 1992). Re claim 35, Yamazaki 437 teaches and/or would have suggested as obvious to one of ordinary skill in the art at the time of invention: A structure (see e.g. Fig. 6A; and single transistors as shown in e.g. Figs. 2B, 5B, etc.; in Fig. 6A, two transistors 803 and 804, each having an oxide semiconductor stack and being “similar” to the transistor of earlier embodiments exist in a logic circuit, see e.g. para 209) comprising: a first layer (e.g. substrate 400, and/or 412), and a first semiconductor structure (e.g. a transistor such as shown in e.g. Fig. 5B; or parts thereof, including e.g. only the channel) and a second semiconductor structure (e.g. another transistor such as shown in e.g. Fig. 5B, or parts thereof, including e.g. only the channel) directly on the first layer, the first semiconductor structure including a first amorphous semiconductor layer e.g. “first oxide semiconductor” in para 18; e.g. 408a in Fig. 5B, also see e.g. para 101, 123, etc.) and a first crystalline semiconductor layer (e.g. “second oxide semiconductor” in para 18; e.g. 408b in Fig. 5B, also see e.g. 101, 124, etc.) on the first amorphous semiconductor layer (see e.g. para 18 “The oxide semiconductor stack includes at least a first oxide semiconductor layer having an amorphous structure, a second oxide semiconductor layer having a crystalline structure over the first oxide semiconductor layer, and a third oxide semiconductor layer having an amorphous structure over the second oxide semiconductor layer”; see also para 101 “the oxide semiconductor stack 408 includes a first oxide semiconductor layer 408a having an amorphous structure, a second oxide semiconductor layer 408b having a crystalline structure over the first oxide semiconductor layer 408a, and a third oxide semiconductor layer 408c over the second oxide semiconductor layer 408b”; see e.g. para 18 ), and the second semiconductor structure including a second amorphous semiconductor layer (e.g. “first oxide semiconductor” in para 18; e.g. 408a in Fig. 5B, also see e.g. para 101, 123, etc.), a second crystalline semiconductor layer (e.g. “second oxide semiconductor” in para 18; e.g. 408b in Fig. 5B, also see e.g. 101, 124, etc.) on the second amorphous semiconductor layer, and a third amorphous semiconductor layer (e.g. “third oxide semiconductor” in para 18; e.g. 408c in Fig. 5B, also see e.g. para 101, 125, etc.) on the second crystalline semiconductor layer (see e.g. para 18 “The oxide semiconductor stack includes at least a first oxide semiconductor layer having an amorphous structure, a second oxide semiconductor layer having a crystalline structure over the first oxide semiconductor layer, and a third oxide semiconductor layer having an amorphous structure over the second oxide semiconductor layer”; see also para 101 “the oxide semiconductor stack 408 includes a first oxide semiconductor layer 408a having an amorphous structure, a second oxide semiconductor layer 408b having a crystalline structure over the first oxide semiconductor layer 408a, and a third oxide semiconductor layer 408c over the second oxide semiconductor layer 408b”; see e.g. para 18 ); and a second layer on the first crystalline semiconductor layer of the first semiconductor structure and on the third amorphous semiconductor layer of the second semiconductor structure (see e.g. Fig. 5B, wherein insulating layer 414 is on the top of the transistor, thus being on the second layer and on the third layer). Combining two embodiments disclosed adjacent to each other in a prior art patent does not require a leap of inventiveness (Boston Scientific Scimed, Inc. v. Cordis Corp., No. 08-1073 (Fed. Cir. Jan. 15, 2009)), especially given the disclosure that the transistors as “similar” to those previously disclosed. “Like the combination of two side-by-side embodiments in Boston Scientific, we view the combination of elements from the optimal and sub-optimal embodiments as a ‘predictable variation’ that does not ‘require a leap of inventiveness.’ ” Paice LLC v. Ford Motor Co., 2016-1412, 21 (Fed. Cir. Mar. 7, 2017). It has been established that “the [obviousness] analysis need not seek out precise teachings directed to the specific subject matter of the challenged claim” because the Office or “a court can take account of the inferences and creative steps that a person of ordinary skill in the art would employ.” KSR Int’ Co. v. Teleflex Inc., 550 U.S. 398, 418 (2007). It is also well settled that a reference stands for all of the specific teachings thereof as well as the inferences one of ordinary skill in the art would have reasonably been expected to draw therefrom. See In re Fritch, 972 F.2d 1260, 1264-65 (Fed. Cir. 1992). 36. The structure of claim 35, wherein the first layer and the second layer are insulating layers (see e.g. para 132 wherein 412 in insulating; see e.g. para 158 wherein 414 is insulating). 37. The structure of claim 35, wherein the second amorphous semiconductor layer, the second crystalline semiconductor layer, and the third amorphous semiconductor layer are oxide semiconductor layers (see e.g. para 118, 120, 124, 209). Claim(s) 8, 9, 27, and 28 is/are rejected under 35 U.S.C. 103 as being unpatentable over US 2014/0042437 A1 (“Yamazaki 437”) in view of US 2020/0303561 A1 (“Abe”). Yamazaki 437 teaches claims 1 and 22, as discussed above, but does not explicitly teach: 8. The thin film transistor structure of claim 1, wherein the second oxide semiconductor layer of the first active layer and the second oxide semiconductor layer of the second active layer have at least one of a (400) crystal plane, a (222) crystal plane, a (220) crystal plane, a (311) crystal plane, or a (0016) crystal plane. 27. The thin film transistor of claim 22, wherein the second oxide semiconductor layer has at least one of a (400) crystal plane, a (222) crystal plane, a (220) crystal plane, a (311) crystal plane, or a (0016) crystal plane. 9. The thin film transistor structure of claim 1, wherein the second oxide semiconductor layer of the first active layer and the second oxide semiconductor layer of the second active layer each have at least one of a Cubic crystal structure, a Bixbyite crystal structure, a Spinel crystal structure, or a hexagonal crystal structure. 28. The thin film transistor of claim 22, wherein the second oxide semiconductor layer has at least one of a Cubic crystal structure, a Bixbyite crystal structure, a Spinel crystal structure, or a Hexagonal crystal structure. Abe teaches and/or would have suggested as obvious to one of ordinary skill in the art at the time of invention, in combination with Yamazaki 437: 8. The thin film transistor structure of claim 1, wherein the second oxide semiconductor layer of the first active layer and the second oxide semiconductor layer of the second active layer have at least one of a (400) crystal plane, a (222) crystal plane, a (220) crystal plane, a (311) crystal plane, or a (0016) crystal plane (see e.g. para 8, 36, 38, 50, 175). 27. The thin film transistor of claim 22, wherein the second oxide semiconductor layer has at least one of a (400) crystal plane, a (222) crystal plane, a (220) crystal plane, a (311) crystal plane, or a (0016) crystal plane (see e.g. para 8, 36, 38, 50, 175). 9. The thin film transistor structure of claim 1, wherein the second oxide semiconductor layer of the first active layer and the second oxide semiconductor layer of the second active layer each have at least one of a Cubic crystal structure, a Bixbyite crystal structure, a Spinel crystal structure, or a hexagonal crystal structure (see e.g. para 8, 36, 38, 50, 175). 28. The thin film transistor of claim 22, wherein the second oxide semiconductor layer has at least one of a Cubic crystal structure, a Bixbyite crystal structure, a Spinel crystal structure, or a Hexagonal crystal structure (see e.g. para 8, 36, 38, 50, 175). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to add the invention of Abe to the invention of Yamazaki 437. The motivation to do so is that the combination produces the predictable results of using a indium oxide material having effectively working substitutional doping (see e.g. para 38) in high mobility films (see e.g. para 30-33). Claim(s) 10 and 29 is/are rejected under 35 U.S.C. 103 as being unpatentable over US 2014/0042437 A1 (“Yamazaki 437”) in view of US 2019/0252416 A1 (“Yamazaki 416”). Yamazaki 437 teaches claims 1 and 22, as discussed above, but does not explicitly teach: 10. The thin film transistor structure of claim 1, wherein the second oxide semiconductor layer of the first active layer and the second oxide semiconductor layer of the second active layer each include crystal grains having a particle diameter in a range from 3 to 500 nm, inclusive. 29. The thin film transistor of claim 22, wherein the second oxide semiconductor layer includes a crystal grain having a particle diameter in a range from 3 nm to 500 nm, inclusive. Yamazaki 416 teaches and/or would have suggested as obvious to one of ordinary skill in the art at the time of invention, in combination with Yamazaki 437: 10. The thin film transistor structure of claim 1, wherein the second oxide semiconductor layer of the first active layer and the second oxide semiconductor layer of the second active layer each include crystal grains having a particle diameter in a range from 3 to 500 nm, inclusive (see e.g. para 108-109). 29. The thin film transistor of claim 22, wherein the second oxide semiconductor layer includes a crystal grain having a particle diameter in a range from 3 nm to 500 nm, inclusive (see e.g. para 108-109). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to add the invention of Yamazaki 416 to the invention of Yamazaki 437. The motivation to do so is that the combination produces the predictable results of using an indium oxide with microcrystals or nanocrystals with a particle size between 1-20 nm (see e.g. para 68) having good properties (see e.g. para 68, 159). Allowable Subject Matter Claim(s) 11-15 and 30-34 is/are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. The following is a statement of reasons for the indication of allowable subject matter: the prior art does not explicitly teach, or reasonably suggest as obvious to one of ordinary skill in the art, an invention having all of the limitations of claim 11 or 30, including: (claim 11) wherein: the first active layer includes: a third oxide semiconductor layer disposed between the first oxide semiconductor layer and the second oxide semiconductor layer of the first active layer and having a crystalline structure; and a fourth oxide semiconductor layer disposed on the second oxide semiconductor layer of the first active layer and having a crystalline structure; and the second active layer includes: a fourth oxide semiconductor layer disposed between the first oxide semiconductor layer and the second oxide semiconductor layer of the second active layer and having a crystalline structure; and a fifth oxide semiconductor layer disposed between the second oxide semiconductor layer and the third oxide semiconductor layer of the second active layer and having a crystalline structure. (claim 30) wherein the active layer further includes: a fourth oxide semiconductor layer disposed between the first oxide semiconductor layer and the second oxide semiconductor layer and having a crystalline structure; and a fifth oxide semiconductor layer disposed between the second oxide semiconductor layer and the third oxide semiconductor layer and having a crystalline structure. The other claims 12-15 and 31-34 each depend from one of these claims, and each would be allowable for the same reasons as the claim from which it depends. Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.” Conclusion Conclusion / Prior Art The prior art made of record, because it is considered pertinent to applicant's disclosure, but which is not relied upon specifically in the rejections above, is listed on the Notice of References Cited. US 2014/0014947 A1 (“Yamazaki”) contains many of the same teachings as Yamazaki 437. Conclusion / Contact Information Any inquiry concerning this communication or earlier communications from the examiner should be directed to Kevin Parendo who can be contacted by phone at (571) 270-5030 or by direct fax at (571) 270-6030. The examiner can normally be reached Monday-Friday from 9 am to 4 pm ET. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Billy Kraig, can be reached at (571) 272-8660. The fax number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /Kevin Parendo/Primary Examiner, Art Unit 2896