DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-11 and 18-19 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 1 recite “discrete leads” in line 3, “the leads” in line 4, “a lead” in line 5-6, “the leads” in line 6, “the leads” in line 7… The limitations are confusing. It is under if “the leads” and “the discrete leads” are the same things, and if the “a lead” is a part of “the leads”, or a part of “the discrete leads”, or “a lead” is another claimed element and not belong to “plurality of discrete leads”. Please change “the leads” to “the discrete leads”, “a lead” to “a discrete lead of the plurality of discrete leads”.
Claims 2-11 are rejected since they inherit the confusions from claim 1.
Claim 17 recite “discrete initial leads” in line 4 and “an initial lead” in line 5-6. It is under if “an initial lead” is a part of “discrete initial leads”. Please change “an initial lead” to “a discrete initial lead of the plurality of discrete initial leads”.
Claims 18-19 are rejected since they inherit the confusions from claim 17.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 3-7, and 9-10 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Chew et al. (U.S. Patent No. 5,973,388).
Regarding to claim 1, Chew teaches a package structure, comprising:
a die pad (Figs. 3-6, element 2);
a plurality of discrete leads disposed on either side of or around the die pad (Figs. 3-6, element 7), wherein each of the leads comprises an upper surface and a lower surface that are opposite to each other (Figs. 3-6), a trench extending through a portion of the lower surface and a portion of an outer sidewall surface of a lead being formed in a region, away from the die pad, of the lead (Figs. 3-6, element 9), a lateral hole being formed in the lead on a side surface of the trench, and the lateral hole being communicated with the trench to form a step (Figs. 3-6, region under element 10);
a first molding layer filling the gaps between the leads and the die pad (Fig. 3, portion of mold 1 between element 2 and element 7);
a semiconductor chip disposed on an upper surface of the die pad, wherein the semiconductor chip is electrically connected to an upper surface of the lead (Fig. 3, element 3); and
a second molding layer disposed on an upper surface of the first molding layer, the lead, and the die pad, wherein the second molding layer encapsulates the semiconductor chip (Fig. 3, portion of mold 1 on top surfaces of element 2 and element 7).
Regarding to claim 3, Chew teaches the trench is square, and the lateral hole extends in the lead from a bottom corner of the trench towards the die pad (Fig. 3).
Regarding to claim 4, Chew teaches the lateral hole extends in the lead from the bottom corner of the trench towards the die pad in a pattern of being parallel to the upper surface of the lead or forming an angle with the upper surface of the lead (Fig. 3).
Regarding to claim 5, Chew teaches the lateral hole is square, circular, or elliptical (Fig. 6).
Regarding to claim 6, Chew teaches the die pad is made of same or different materials from the lead (this limitation is inherently met).
Regarding to claim 7, Chew teaches the semiconductor chip comprises a functional surface (Fig. 3, top surface of die 3) and a back surface (Fig. 3, bottom surface of die 3) that are opposite to each other, wherein a pad is arranged on the functional surface (Fig. 3, Fig. 10, the pad which connects to the wire), and the back surface of the semiconductor chip is attached to the upper surface of the die pad (Fig. 3), the pad on the functional surface of the semiconductor chip being electrically connected to the lead via a wire (Fig. 3).
Regarding to claim 9, Chew teaches the trench is square (Fig. 6), and the lateral hole extends in the lead from a bottom corner of the trench towards the die pad (Fig. 3).
Regarding to claim 10, Chew teaches the semiconductor chip comprises a functional surface (Fig. 3, top surface of die 3) and a back surface (Fig. 3, bottom surface of die 3) that are opposite to each other, wherein a pad is arranged on the functional surface (Fig. 3, Fig. 10, the pad which connects to the wire), and the back surface of the semiconductor chip is attached to the upper surface of the die pad (Fig. 3), the pad on the functional surface of the semiconductor chip being electrically connected to the lead via a wire (Fig. 3).
Claims 1, 3-7, 9-10, and 17-18 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Makino (U.S. Patent No. 9,601,415).
Regarding to claim 1, Makino teaches a package structure, comprising:
a die pad (Fig 5, Fig. 31, please see the attached figures with annotations);
a plurality of discrete leads disposed on either side of or around the die pad (Fig 5, Fig. 31, please see the attached figures with annotations), wherein each of the leads comprises an upper surface and a lower surface that are opposite to each other (Fig 5, Fig. 31, please see the attached figures with annotations), a trench extending through a portion of the lower surface and a portion of an outer sidewall surface of a lead being formed in a region, away from the die pad, of the lead (Fig 5, Fig. 31, please see the attached figures with annotations), a lateral hole being formed in the lead on a side surface of the trench, and the lateral hole being communicated with the trench to form a step (Fig 5, Fig. 31, please see the attached figures with annotations);
a first molding layer filling the gaps between the leads and the die pad (Fig 5, Fig. 31, please see the attached figures with annotations, portion of mold MR1 between the leads and the die pad);
a semiconductor chip disposed on an upper surface of the die pad, wherein the semiconductor chip is electrically connected to an upper surface of the lead (Fig 5, Fig. 31, element CHP); and
a second molding layer disposed on an upper surface of the first molding layer, the lead, and the die pad, wherein the second molding layer encapsulates the semiconductor chip (Fig 5, Fig. 31, please see the attached figures with annotations, portion of mold MR1 encapsulating the semiconductor chip).
PNG
media_image1.png
688
1352
media_image1.png
Greyscale
PNG
media_image2.png
548
1185
media_image2.png
Greyscale
Regarding to claim 3, Makino teaches the trench is square, and the lateral hole extends in the lead from a bottom corner of the trench towards the die pad (Fig 5, Fig. 31).
Regarding to claim 4, Makino teaches the lateral hole extends in the lead from the bottom corner of the trench towards the die pad in a pattern of being parallel to the upper surface of the lead or forming an angle with the upper surface of the lead (Fig 5, Fig. 31).
Regarding to claim 5, Makino teaches the lateral hole is square, circular, or elliptical (Fig 5, Fig. 31).
Regarding to claim 6, Makino teaches the die pad is made of same or different materials from the lead (column 9, lines 18-10).
Regarding to claim 7, Makino teaches the semiconductor chip comprises a functional surface (Fig 5, Fig. 31, top surface of the chip) and a back surface (Fig 5, Fig. 31, bottom surface of the chip) that are opposite to each other, wherein a pad is arranged on the functional surface (Fig 5, Fig. 31, element PD), and the back surface of the semiconductor chip is attached to the upper surface of the die pad (Fig 5, Fig. 31), the pad on the functional surface of the semiconductor chip being electrically connected to the lead via a wire (Fig 5, Fig. 31, element BW).
Regarding to claim 9, Makino teaches the trench is square (Fig. 6), and the lateral hole extends in the lead from a bottom corner of the trench towards the die pad (Fig 5, Fig. 31).
Regarding to claim 10, Makino teaches the semiconductor chip comprises a functional surface (Fig 5, Fig. 31, top surface of the chip) and a back surface (Fig 5, Fig. 31, bottom surface of the chip) that are opposite to each other, wherein a pad is arranged on the functional surface (Fig 5, Fig. 31, element PD), and the back surface of the semiconductor chip is attached to the upper surface of the die pad (Fig 5, Fig. 31), the pad on the functional surface of the semiconductor chip being electrically connected to the lead via a wire (Fig 5, Fig. 31, element BW).
Regarding to claim 17, Makino teaches a method for forming a package structure, comprising (the method steps are not claimed to impart in a specific order):
providing a metal frame (Fig. 31, element DP), wherein the metal frame comprises several discrete die pads and a plurality of discrete initial leads disposed on either side of or around the discrete die pads, each of the plurality of discrete initial leads comprising an upper surface and a lower surface that are opposite to each other, an initial trench extending through a portion of the lower surface of an initial lead, wherein a first molding layer is filled between the plurality of discrete initial leads and between the initial lead and a die pad (Fig. 31, please see the attached figures with annotations);
etching the initial lead from a bottom corner of the initial trench towards the die pad (Fig. 31), and
forming a lateral hole communicated with the initial trench in the initial lead (Fig. 31, please see the attached figures with annotations);
mounting a semiconductor chip onto an upper surface of the die pad, wherein the semiconductor chip is electrically connected to an upper surface of the initial lead (Fig. 31, element CHP);
forming a second molding layer on an upper surface of the first molding layer, the upper surface of the initial lead, and the upper surface of the die pad (Fig. 31, please see the attached figures with annotations, portion of mold MR1 encapsulating the semiconductor chip); and
dividing along a direction of a central axis of the initial trench to form several discrete package structures, wherein each of the plurality of discrete initial leads is divided into two leads, the two leads are respectively disposed in adjacent two of the discrete package structures, and correspondingly the initial trench is divided into two trenches, each of the trenches being communicated with a corresponding lateral hole (Fig. 33, Fig. 5).
PNG
media_image3.png
583
1193
media_image3.png
Greyscale
Regarding to claim 18, Makino teaches the initial lead is etched from the bottom comer of the initial trench towards the die pad by an isotropic dry etching process or an isotropic wet etching process (column 28, lines 4-6).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 2 is rejected under 35 U.S.C. 103 as being unpatentable over Makino (U.S. Patent No. 9,601,415), as applied to claim 1 above.
Regarding to claim 2, Makino teaches depth of the trench is less than a thickness of the lead (Fig. 31). Makino is silent as to dimension ranges in the text. However, it would have been obvious to one having ordinary skill in the art at the time the invention was filed to configure an aperture size of the lateral hole to be less than the depth of the trench in order to prevent chipping, since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art. In re Aller, 105 USPQ 233 (CCPA 1955).
Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over Makino (U.S. Patent No. 9,601,415), as applied to claim 1 above, in view of Baello et al. (U.S. Patent No. 12,132,027).
Regarding to claim 8, Makino does not disclose a solder bump protrudes from the functional surface, and the semiconductor chip is flip-mounted over the upper surface of the die pad, the solder bump on the functional surface of the semiconductor chip being soldered to the lead. Baello discloses a semiconductor chip comprises a functional surface and a back surface that are opposite to each other, wherein a solder bump protrudes from the functional surface, and the semiconductor chip is flip-mounted over the upper surface of the die pad, the solder bump on the functional surface of the semiconductor chip being soldered to the lead (Fig. 2A). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Makino in view of Baello to flip-mount the semiconductor chip over the upper surface of the die pad, the solder bump on the functional surface of the semiconductor chip being soldered to the lead, in order to make structure useful for more applications.
Claim 11 is rejected under 35 U.S.C. 103 as being unpatentable over Makino (U.S. Patent No. 9,601,415), as applied to claims 1 and 6 above, in view of Baello et al. (U.S. Patent No. 12,132,027).
Regarding to claim 11, Makino does not disclose a solder bump protrudes from the functional surface, and the semiconductor chip is flip-mounted over the upper surface of the die pad, the solder bump on the functional surface of the semiconductor chip being soldered to the lead. Baello discloses a semiconductor chip comprises a functional surface and a back surface that are opposite to each other, wherein a solder bump protrudes from the functional surface, and the semiconductor chip is flip-mounted over the upper surface of the die pad, the solder bump on the functional surface of the semiconductor chip being soldered to the lead (Fig. 2A). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Makino in view of Baello to flip-mount the semiconductor chip over the upper surface of the die pad, the solder bump on the functional surface of the semiconductor chip being soldered to the lead, in order to make structure useful for more applications.
Allowable Subject Matter
Claims 12-16 are allowed.
Claim 19 would be allowable if rewritten to overcome the rejection(s) under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), 2nd paragraph, set forth in this Office action and to include all of the limitations of the base claim and any intervening claims. The following is a statement of reasons for the indication of allowable subject matter:
Regarding to claim 12, the prior art fails to anticipate or render obvious the claimed limitations including “forming a first isolation sacrificial layer covering an upper surface of the carrier plate including isolation regions and an upper surface of the carrier plate including a portion of lead regions, wherein a plurality of remaining lead regions not covered by the first isolation sacrificial layer are discrete, an upper surface of the first metal layer is flush with an upper surface of the first isolation sacrificial layer, forming a second metal layer on the upper surface of the first metal layer on either side of the second isolation sacrificial layer and the first step sacrificial layer, forming a third metal layer on the upper surface of the second metal layer on either side of the third isolation sacrificial layer and the second step sacrificial layer, wherein an upper surface of the third metal layer is flush with the upper surface of the third isolation sacrificial layer, the first metal layer, the second metal layer, and the third metal layer of the die pad region constitute a die pad, and the first metal layer, the second metal layer, and the third metal layer of the lead region constitute a plurality of discrete initial leads; removing the first step sacrificial layer and the second step sacrificial layer to form an inverted "T"-shaped trench” in combination with the rest of limitations recited in claim 12.
Regarding to claim 19, the prior art fails to anticipate or render obvious the claimed limitations including “prior to etching the initial lead from the bottom comer of the initial trench towards the die pad, the method further comprises forming a protective sidewall on a sidewall surface of the initial trench” in combination with the limitations recited in claims 17-18.
Pertinent Art
For the benefits of the Applicant, US-11562948-B2, US-11562948-B2, US-6204554-B1, US-6399415-B1, US-7339258-B2, US-8174096-B2, US-6437429-B1, US-11456261-B2 US-9773960-B2, and US-9631481-B1, are cited on the record as being pertinent to significant disclosure through some but not all claimed features of the defined invention. These references fail to disclose the limitations including “a lateral hole being formed in the lead on a side surface of the trench, and the lateral hole being communicated with the trench to form a step”.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to VU A VU whose telephone number is (571)270-7467. The examiner can normally be reached M-F: 8:00AM - 5:00PM.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, CHAD M DICKE can be reached at (571) 270-7996. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/VU A VU/Primary Examiner, Art Unit 2897
Prosecution Insights