DETAILED ACTION
1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Cross-Reference to Related Applications
2. This application claims benefit of 63/471,982 06/09/2023.
Oath/Declaration
3. The oath/declaration is not in the record and as required under 371 CFR 1.63(d).
Information Disclosure Statement
4. The office acknowledges receipt of the following items from the applicant:
Information Disclosure Statement (IDS) filed on 04/18/2025, 07/25/2025, 04/29/2026 and 09/09/2026.
Specification
5. The specification is objected to for the following reason: The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed (see MPEP 606.01).
A title such as -- COMPLEMENTARY METAL-OXIDE-SEMICONDUCTOR CIRCUIT INCLUDING A FIRST AND SECOND LOCALIZED ISOLATION LAYER -- or is suggested by the applicant.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
6. Claim 1 is rejected under 35 U.S.C. 103(a) as being unpatentable over JI Y (CN-103325672-A) in view of STAMPER A (CN-114597261-A).
Regarding claim 1, JI Y discloses a CMOS (complementary metal-oxide-semiconductor) circuit, comprising:
a bulk semiconductor substrate (20, see substrate 102, para [0035, Fig. 2] in Huang (U.S. Publication No. 2024/0072049 A1) with an original semiconductor surface;
a first active region (HV) and a second active region (LV) formed based on the bulk semiconductor substrate (20);
a first type transistor (DMOS. P-type) formed based on the first active region (HV) and having a first doped body (31, P-type or N-type);
a second type transistor (NMOS, N-type) formed based on the second active region (LV) and having a second doped body (32, P-type or N-type (Fig. 3G and English Text).
JI Y discloses the features of the claimed invention as discussed above, but does not disclose a first localized isolating layer under the first type transistor and at least isolating the first doped body from the bulk semiconductor substrate; and a second localized isolating layer under the second type transistor and at least partially isolating the second doped body from the bulk semiconductor substrate.
STAMPER A, however, discloses a first localized isolating layer (Left 18) under the first type transistor (left transistor) and at least isolating the first doped body (Left 30) from the bulk semiconductor substrate (10); and a second localized isolating layer (Right 18) under the second type transistor (Right transistor) and at least partially isolating the second doped body (Right 30) from the bulk semiconductor substrate (10) (Fig. 1 and para [0045]-[0054]).
It would have been obvious to one having ordinary skilled in the art before the effective filing date of the claimed invention to modify the teaching of JI Y to provide a first localized isolating layer under the first type transistor and at least isolating the first doped body from the bulk semiconductor substrate; and a second localized isolating layer under the second type transistor and at least partially isolating the second doped body from the bulk semiconductor substrate as taught by STAMPER A for a purpose of reducing the leakage current between the semiconductor device and the substrate.
7. Claim 12 is rejected under 35 U.S.C. 103(a) as being unpatentable over JI Y and STAMPER A in view of 홍형석 (KR-20120128531-A).
JI Y and STAMPER A discloses the features of the claimed invention as discussed above, but does not disclose wherein a channel length of the first type transistor is the same or substantially a channel length of the second type transistor
홍형석, however, discloses wherein a channel length (L1) of the first type transistor (Left transistor) is the same or substantially a channel length (L2) of the second type transistor (Right transistor) (Fig. 32 and English Text).
It would have been obvious to one having ordinary skilled in the art before the effective filing date of the claimed invention to modify the teaching of JI Y and STAMPER A to provide wherein a channel length of the first type transistor is the same or substantially a channel length of the second type transistor as taught by 홍형석 for a purpose of providing the same driving capability of the first and second transistor.
Allowable Subject Matter
8. The following is a statement of reason for the indication of allowable subject matter:
Regarding claim 1, JI Y (CN-103325672-A) discloses a CMOS (complementary metal-oxide-semiconductor) circuit, comprising:
a bulk semiconductor substrate (20, see substrate 102, para [0035, Fig. 2] in Huang (U.S. Publication No. 2024/0072049 A1) with an original semiconductor surface;
a first active region (HV) and a second active region (LV) formed based on the bulk semiconductor substrate (20);
a first type transistor (DMOS. P-type) formed based on the first active region (HV) and having a first doped body (31, P-type or N-type) and a first channel (301);
a second type transistor (NMOS, N-type) formed based on the second active region (LV) and having a second doped body (32, P-type or N-type and a second channel (302) (Fig. 3G and English Text).
STAMPER A (CN-114597261-A) discloses a first localized isolating layer (Left 18) under the first type transistor (left transistor) and at least isolating the first doped body (Left 30) from the bulk semiconductor substrate (10); and a second localized isolating layer (Right 18) under the second type transistor (Right transistor) and at least partially isolating the second doped body (Right 30) from the bulk semiconductor substrate (10) (Fig. 1 and para [0045]-[0054]).
It would have been an obvious matter of the design choice to modify the PMOS transistor instead of the DMOS in order to improve the performance of the CMOS circuit, since it has been held to be within the general skill of the worker in the art to select any type of the transistor on the basis of its suitability for the intended use as a matter of obvious design choice. In re Leshin, 125 USPQ 416.
홍형석 discloses wherein a channel length (L1) of the first type transistor (Left transistor) is the same or substantially a channel length (L2) of the second type transistor (Right transistor) (Fig. 32 and English Text).
JI Y, STAMPER A and 홍형석, however, either alone or together in any combination, do not disclose, teach, or otherwise suggest a feature of “a first shallow trench isolation region surrounding the first active region and the first localized isolating layer; and a second shallow trench isolation region surrounding the second active region and the second localized isolating layer” as cited in the independent claim 13.
Claims 14-18 are directly or indirectly depend on the independent claim 13, then, they are also being allowed.
Claims 2-11 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Cited Prior Arts
8. The prior art made of record and not relied upon is considered pertinent to applicant’s disclosure.
LU Z (CN-105609557-A) discloses a CMOS circuit, comprising a substrate 100 may include a first active region 100a and second active region 100b. In addition, the first active region 100a and second active region 100b may be isolated from each other by forming the first isolation region 100 in the substrate 103. In other words, the first active region 100a and second active region 100b may be formed by the first isolation region 103 is defined
Conclusion
9. Any inquiry concerning this communication or earlier communications from the examiner should be directed to Phuc T. Dang whose telephone number is 571-272-1776. The examiner can normally be reached on 8:00 am-5:00 pm.
If attempts to reach the examiner by telephone are unsuccessful, the examiner's supervisor, Jacob Choi can be reached on 469-295-9060. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/PHUC T DANG/Primary Examiner, Art Unit 2897
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