Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 29 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 29 recites the limitation "the first point" and “the second point” in lines 2 and 3. There is insufficient antecedent basis for this limitation in the claim.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 14 and 17 are rejected under 35 U.S.C. 103 as being unpatentable over Gomm et al. (US 20070030754 A1 and Gomm hereinafter) in view of Bae et al. (US 7456673 and Bae hereinafter.).
Regarding claim 14, Gomm discloses an integrated circuit [fig. 6], comprising: a divider stage [46], configured to divide a frequency of an input clock signal [40] and generate a first clock signal [18]; a frequency trimming stage [12], configured to add a first delay to the first clock signal to generate a second clock signal [44]; a voltage control stage [14], configured to repeatedly adjust a second delay of the second clock signal [para. 13] according to a control signal generated by a feedback path [delay of 14 controlled via 48] to generate a third clock signal [20]. Gomm does not explicitly disclose a first single-to-differential circuit, configured to convert the first clock signal into first differential clock signals; a second single-to-differential circuit, configured to convert the third clock signal into second differential clock signals; and a logic stage, configured to perform a logic operation using the first differential clock signals and the second differential clock signals to generate an output clock signal.
However, Bae discloses [fig. 5] a first single-to-differential circuit [530], configured to convert the first clock signal [from 510] into first differential clock signals [A and /A]; a second single-to-differential circuit [540], configured to convert the third clock signal [from 520] into second differential clock signals [B and /B]; and a logic stage [570], configured to perform a logic operation using the first differential clock signals [integrated from 550] and the second differential clock signals [integrated from 560] to generate an output clock signal [OUT]. Therefore, it would have been obvious to one of the ordinary skill in the art before the effective filing date to modify the invention as described by Gomm to include the first single-to-differential circuit, the second single-to-differential circuit and logic stage as taught by Bae to improve operational speed of a clocking circuit.
Regarding claim 17, Gomm in view of Bae discloses further wherein the feedback path is an analog feedback path configured to generate an analog voltage control signal as the control signal [CASE LAW], and the voltage control stage comprises a voltage-controlled delay line [Gomm, 14 controlled via 24] to adjust the second delay of the second clock signal to generate the third clock signal according to the control signal [Gomm, para. 7].
Claim 26 is rejected under 35 U.S.C. 103 as being unpatentable over Gomm in view of Bae further in view of Qi et al. (US 11804828 B2 and Qi hereinafter.).
Regarding claim 26, Gomm in view of Bae discloses all the features regarding claim 14 as indicated above. Gomm in view of Bae discloses further wherein the divider stage comprises: a clock divider [Gomm, 46 divides clock in 18 by 2], configured to divide the frequency of the input clock signal by 2 [as shown] to generate the first clock signal [as shown]. Gomm in view of Bae does not explicitly disclose a first buffer, configured to buffer the first clock signal.
However, Qi discloses a first buffer, configured to buffer the first clock signal [col 4 lines 54-56]. Therefore, it would have been obvious to one of the ordinary skill in the art before the effective filing date to modify the invention as described by Gomm in view of Bae to include the buffer as taught by Qi to improve duty cycle distortion in a clocking circuit.
Claim 27 is rejected under 35 U.S.C. 103 as being unpatentable over Gomm in view of Bae further in view of Moindron et al. (US 20070247198 and Moindron hereinafter.) further in view of Chao et al. (TW 200427224 A and Chao hereinafter.).
Regarding claim 27, Gomm in view of Bae discloses all the features regarding claim 14 as indicated above. Gomm in view of Bae does not explicitly disclose wherein the logic stage comprises: a logic gate, configured to perform the logic operation using the first differential clock signals and the second differential clock signals to generate the output clock signal; and an inverter chain, configured to buffer the output clock signal.
However, Moindron discloses [fig. 7] wherein the logic stage comprises: a logic gate [23], configured to perform the logic operation using the first differential signals [via differential amp 31] and the second differential signals [via differential amp 32] to generate the output signal [out of 23]. Therefore, it would have been obvious to one of the ordinary skill in the art before the effective filing date to modify the invention as described by Gomm in view of Bae to include the logic gate as taught by Moindron to improve protection measures in a switching circuit.
Moindron does not explicitly disclose the first and second differential signals as being clocking signals. Moindron describes circuitry and methods for using comparators for use in failure detections of AC switching circuits [para. 3]. This is inline with applicants proposed invention of a high speed switching circuit with variations in operating temperature [para. 1 of applicant specs]. It would have been obvious to one having ordinary skill in the art before the effective filing date to use have the first and second differential signals as being clocking signals, as taught by Moindron in order to improve protection measures in a switching circuit.
Gomm in view of Bae further in view of Moindron does not explicitly disclose an inverter chain, configured to buffer the output clock signal.
However, Chao discloses [fig. 6] an inverter chain [614 and 64], configured to buffer the output clock signal [CLKOUT]. Therefore, it would have been obvious to one of the ordinary skill in the art before the effective filing date to modify the invention as described by Gomm in view of Bae further in view of Moindron to include the inverter chain as taught by Chao to improve clock sensitivity in a circuit.
Claims 28-29 are rejected under 35 U.S.C. 103 as being unpatentable over Gomm in view of Bae further in view of Moindron further in view of Chao.
Regarding claim 28, Gomm in view of Bae further in view of Moindron further in view of Chao discloses further wherein the inverter chain comprises a first inverter [Chao, 614 shown in fig. 6], a second inverter [Chao, 64 shown in fig. 6]. Gomm in view of Bae further in view of Moindron further in view of Chao does not explicitly disclose a third inverter, and a fourth inverter connected in series.
However, It would have been obvious to one having ordinary skill in the art before the effective filing date to replace two inverters with four inverters connected in series and still maintain a reliable output clocking signal since it has been held that mere duplication of the essential working parts of a device involves only routine skill in the art. St. Regis Paper Co. v. Bemis Co., 193 USPQ 8.
Regarding claim 29, Gomm in view of Bae further in view of Moindron further in view of Chao discloses further wherein: the first point corresponds to an output terminal of the second inverter [Chao, output of 614 in fig. 6]; the second point corresponds to an output terminal of the third inverter [Chao, output of 64 in fig. 6]. Gomm in view of Bae further in view of Moindron further in view of Chao does not explicitly disclose output clock signal is obtained at an output terminal of the fourth inverter.
However, It would have been obvious to one having ordinary skill in the art before the effective filing date to have two inverters connected in series at the output of 614 [the second inverter] to have the CLKOUT signal still be in phase with the output of 614 thereby ensuring proper operation of the system. Furthermore it has been held that mere duplication of the essential working parts of a device involves only routine skill in the art. St. Regis Paper Co. v. Bemis Co., 193 USPQ 8.
Claim 21 is rejected under 35 U.S.C. 103 as being unpatentable over Gomm in view of Chao.
Regarding claim 21, Gomm discloses an integrated circuit [fig. 6], comprising: a divider stage [46], configured to generate a first clock signal [40] by dividing a frequency of an input clock signal [18]; a frequency trimming stage [12], configured to add a first delay to the first clock signal to generate a second clock signal [44]; a voltage control stage [14], configured to repeatedly adjust a second delay of the second clock signal [para. 13] according to a control signal [via 24] to generate a third clock signal [20] Gomm does not explicitly disclose a logic stage, configured to perform a logic operation according to the first clock signal and the third clock signal to generate an output clock signal; and a comparison stage, configured to generate the control signal according to a first intermediate signal and a second intermediate signal from the logic stage.
However, Chao discloses a logic stage [fig. 6, exclusive NOR gate 614], configured to perform a logic operation according to the first clock signal [output of 611] and the third clock signal [output of 613] to generate an output clock signal [CLKOUT]; and a comparison stage [85], configured to generate the control signal [output of 85 into 812] according to a first intermediate signal [a first output of 83 into 85] and a second intermediate signal [a second output of 83 into 85] from the logic stage. Therefore, it would have been obvious to one of the ordinary skill in the art before the effective filing date to modify the invention as described by Gomm to include the logic and comparison stage as taught by Chao to improve clock sensitivity in a circuit.
Claim 22 is rejected under 35 U.S.C. 103 as being unpatentable over Gomm in view of Chao further in view of Bae.
Regarding claim 22, Gomm in view of Chao discloses all the features regarding claim 21 as indicated above. Gomm in view of Chao does not explicitly disclose further comprising: a first single-to-differential circuit, configured to convert the first clock signal into first differential clock signals; and a second single-to-differential circuit, configured to convert the third clock signal into second differential clock signals, wherein the logic stage is configured to perform the logic operation using the first differential clock signals and the second differential clock signals to generate the output clock signal.
However, Bae discloses [fig. 5] further comprising: a first single-to-differential circuit [530], configured to convert the first clock signal [from 510] into first differential clock signals [A and /A]; and a second single-to-differential circuit [540], configured to convert the third clock signal [from 520] into second differential clock signals [B and /B], wherein the logic stage [570] is configured to perform the logic operation using the first differential clock signals [integrated from 550] and the second differential clock signals [integrated from 560] to generate the output clock signal [OUT]. Therefore, it would have been obvious to one of the ordinary skill in the art before the effective filing date to modify the invention as described by Gomm in view of Chao to include the first single-to-differential circuit, the second single-to-differential circuit and logic stage as taught by Bae to improve operational speed of a clocking circuit.
Claim 23 is rejected under 35 U.S.C. 103 as being unpatentable over Gomm in view of Chao further in view of Lin et al. (US 20240039520 A1 and Lin hereinafter.).
Regarding claim 23, Gomm in view of Chao discloses all the features regarding claim 21 as indicated above. Gomm in view Chao discloses further wherein the comparison stage comprises: a first low-pass filter [Chao, 62] and a second low-pass filter [Chao, 63] configured to filter the first intermediate signal [Chao, inverted CLKOUT] and the second intermediate signal [Chao, CLKOUT] to generate a first filtered signal and a second filtered signal [Chao, inputs on 65], respectively; an operational amplifier [Chao, 65], configured to compare the first filtered signal and the second filtered signal to generate the control signal [Chao, output of 65 onto 613] Gomm in view of Chao does not explicitly disclose a loop filer, coupled to an output terminal of the operational amplifier, and configured to stabilize the control signal generated by the operational amplifier.
However, Lin discloses [fig. 2] a loop filer [110], coupled to an output terminal of the operational amplifier [108], and configured to stabilize the control signal generated by the operational amplifier [para. 35]. Therefore, it would have been obvious to one of the ordinary skill in the art before the effective filing date to modify the invention as described by Gomm in view of Chao to include the loop filter as taught by Lin to improve duty cycle errors in a clocking circuit.
Allowable Subject Matter
Claims 1-6, 9-10, 24 and 25 are allowed.
The following is an examiner’s statement of reasons for allowance:
Claim 1 is allowed because the prior art of record teaches “An integrated circuit, comprising: a divider stage, configured to generate a first clock signal by dividing a frequency of an input clock signal; a frequency trimming stage, configured to add a first delay to the first clock signal to generate a second clock signal; a voltage control stage, configured to repeatedly adjust a second delay of the second clock signal according to a control signal generated by a feedback path to generate a third clock signal; and a logic stage, configured to perform a logic operation according to the first clock signal and the third clock signal to generate an output clock signal”. However, it does not disclose nor render obvious “wherein the logic stage comprises: a logic gate, configured to perform the logic operation according to the first clock signal and the third clock signal to generate the output clock signal; and an inverter chain, configured to buffer the output clock signal, wherein the feedback path comprises: a first low-pass filter and a second low-pass filter configured to filter a first signal and a second signal obtained from a first point and a second point within the inverter chain to generate a first filtered signal and a second filtered signal, respectively; and a comparison circuit, configured to compare the first filtered signal and the second filtered signal to generate the control signal.” as cited with the rest of the claimed limitation.
Dependent claims 2-6, 9-10, 13, 24 and 25 are allowed.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Response to Arguments
Applicant's arguments filed 02/11/2026 have been fully considered but they are not persuasive.
Regarding claim 14, applicant argues [pg. 3 of Remarks] Bae does not explicitly disclose a first single-to-differential circuit configured to convert the first clock signal and a second single-to-differential circuit configured to convert the third clock signal. Specifically first and second single-to-differential circuits of Bae take inputs from OR gates and not first and third clock signals. Examiner respectfully disagrees.
An OR gate passes either or both logic signals on its inputs. The OR gates of Bae take clock signals on their respective inputs. Therefore, Bae reads on the claims and the rejection still stands.
Regarding claim 14, applicant argues [pg. 4 of Remarks] Bae does not explicitly disclose a logic stage configured to perform a logic operation using the first and second differential clock signals. Examiner respectfully disagrees.
The integrators in conjunction with the comparator of Bae create the logical output clock signal OUT. The use of integrators in logic operations are well known in the art for use as signal delays. Therefore, Bae reads on the claims and the rejection still stands.
Regarding claim 21, applicant argues [pg. 6 of remarks] Chao does not explicitly disclose “… a comparison stage, configured to generate the control signal according to a first intermediate signal and a second intermediate signal from the logic stage.”. Examiner respectfully disagrees.
An intermediate signal is a signal situated or occurring between two points or stages. The comparison stage [65 of fig. 6 and 85 off fig. 8] outputs control signals onto voltage control delay circuits [611/613 or 814/861] according to a first and second intermediate signal from logic stage [614 or 813] with the first and second intermediate signals being an inverted and noninverted version of the logic stage output processed by filters [62/63 or 82/83]. Therefore, Chao reads on the claims and the rejection still stands.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's
disclosure, Marcu (US 10873335 B2) is cited to teach a programable clock dividing circuit.
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JAMES G YEAMAN whose telephone number is (571)272-5580. The examiner can normally be reached Mon - Fri 954 Schedule.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Taelor Kim can be reached at (571) 270-7166. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/JAMES G YEAMAN/Examiner, Art Unit 2836
/TAELOR KIM/Supervisory Patent Examiner, Art Unit 2836
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