DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over LInk(USPGPUB DOCUMENT: 2020/0168356, hereinafter Link) in view of Shimizu (USPGPUB DOCUMENT: 2015/0245473, hereinafter Shimizu).
Re claim 1 Link discloses in Fig 2 a semiconductor package structure, comprising: a package substrate comprising: a first core structure(156) having a first surface(top/bottom) and a second surface(top/bottom) opposite the first surface(top/bottom); a plurality of first dielectric layers(118’s within 162) and a plurality of second dielectric layers(118’s within 164) alternatingly stacked on the second surface(top/bottom) of the first core structure(156), wherein a number of second dielectric layers(118’s within 164) is less than a number of first dielectric layers(118’s within 162).
Link does not discloses a plurality of first metal layers alternatingly stacked on the first surface(top/bottom) of the first core structure(156); and a plurality of second metal layers alternatingly stacked
Shimizu discloses a plurality of first metal layers(23/32/34/24/42/44) alternatingly stacked on the first surface(top/bottom) of the first core structure(20); and a plurality of second metal layers alternatingly stacked
It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to apply the teachings of Shimizu to the teachings of Link in order to minimize warp of the wiring substrate [0004, Shimizu].
Re claim 2 Link and Shimizu disclose the semiconductor package structure as claimed in claim 1, wherein the package substrate further comprises: a plurality of prepreg layers alternatingly stacked with some of the second metal layers(23/32/34/24/42/44).
Re claim 3 Link and Shimizu disclose the semiconductor package structure as claimed in claim 2, wherein a number of second metal layers(23/32/34/24/42/44) is equal to a number of first metal layers(23/32/34/24/42/44).
Re claim 4 Link and Shimizu disclose the semiconductor package structure as claimed in claim 2, wherein a minimum distance between the first core structure(156) and the second dielectric layers(118’s within 164) is greater than a maximum distance between the first core structure(156) and the prepreg layers.
Re claim 5 Link and Shimizu disclose the semiconductor package structure as claimed in claim 2, wherein a maximum distance between the first core structure(156) and the second dielectric layers(118’s within 164) is less than a minimum distance between the first core structure(156) and the prepreg layers.
Re claim 6 Link and Shimizu disclose the semiconductor package structure as claimed in claim 1, wherein a number of second metal layers(23/32/34/24/42/44) is less than a number of first metal layers(23/32/34/24/42/44).
Re claim 7 Link and Shimizu disclose the semiconductor package structure as claimed in claim 1, wherein the package substrate further comprises: a second core structure(156) having a third surface(top/bottom) adjacent to the second metal layers(23/32/34/24/42/44) and a fourth surface(top/bottom) opposite the third surface(top/bottom); and a plurality of third dielectric layers and a plurality of third metal layers(23/32/34/24/42/44) alternatingly stacked on the fourth surface(top/bottom) of the second core structure(156).
Re claim 8 Link and Shimizu disclose the semiconductor package structure as claimed in claim 1, further comprising a plurality of bump structures disposed between two of the second metal layers(23/32/34/24/42/44).
Re claim 9 Link and Shimizu disclose the semiconductor package structure as claimed in claim 1, wherein one of the second dielectric layers(118’s within 164) is thicker than the other second dielectric layer.
Re claim 10 Link and Shimizu disclose the semiconductor package structure as claimed in claim 1, wherein the package substrate further comprises a solder layer disposed between two of the second metal layers(23/32/34/24/42/44).
Re claim 11 Link and Shimizu disclose the semiconductor package structure as claimed in claim 1, wherein the package substrate further comprises an adhesive layer disposed between two of the second dielectric layers(118’s within 164).
Re claim 12 Link discloses in Fig 2 a a semiconductor package structure, comprising: a package substrate[0020] comprising: a core structure(156); a plurality of first dielectric layers(118’s within 162) stacked below the core structure(156); and a plurality of second dielectric layers(118’s within 164) stacked over the core structure(156), wherein a thickness of each of the second metal layers(metal within 164) is different from a thickness of each of the first metal layers(metal within 162).
Link does not discloses a plurality of first dielectric layers(118’s within 162) and a plurality of first metal layers(metal within 162) alternatingly stacked below the core structure(156); and a plurality of second dielectric layers(118’s within 164) and a plurality of second metal layers(metal within 164) alternatingly stacked over the core structure(156),
Shimizu discloses a plurality of first metal layers(23/32/34/24/42/44 of Shimizu) alternatingly stacked below the core structure(20);
It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to apply the teachings of Shimizu to the teachings of Link in order to minimize warp of the wiring substrate [0004, Shimizu]. In doing so, a plurality of first dielectric layers(118’s within 162) and a plurality of first metal layers(23/32/34/24/42/44 of Shimizu) alternatingly stacked below the core structure(20 of Shimizu); and a plurality of second dielectric layers(118’s within 164) and a plurality of second metal layers(23/32/34/24/42/44 of Shimizu) alternatingly stacked over the core structure(156),
Re claim 13 Link and Shimizu disclose the semiconductor package structure as claimed in claim 12, wherein a thickness of each of the second metal layers(metal within 164) is greater than a thickness of each of the first metal layers(metal within 162).
Re claim 14 Link and Shimizu disclose the semiconductor package structure as claimed in claim 13, wherein a ratio of the thickness of each of the second metal layers(metal within 164) to the thickness of each of the first metal layers(metal within 162) is in a range of about 1.05 to about 1.30.
Re claim 15 Link and Shimizu disclose the semiconductor package structure as claimed in claim 13, wherein a thickness of each of the second dielectric layers(118’s within 164) is less than a thickness of each of the first dielectric layers(118’s within 162).
Re claim 16 Link and Shimizu disclose the semiconductor package structure as claimed in claim 15, wherein a total thickness of the second metal layers(metal within 164) and the second dielectric layers(118’s within 164) is greater than a total thickness of the first metal layers(metal within 162) and the first dielectric layers(118’s within 162).
Re claim 17 Link and Shimizu disclose the semiconductor package structure as claimed in claim 12, wherein a thickness of each of the second metal layers(metal within 164) is less than a thickness of each of the first metal layers(metal within 162).
Re claim 18 Link and Shimizu disclose the semiconductor package structure as claimed in claim 12, wherein the package substrate[0020] further comprises protective layers covering the plurality of first metal layers(metal within 162) and the plurality of second metal layers(metal within 164).
Re claim 19 Link and Shimizu disclose the semiconductor package structure as claimed in claim 12, further comprising: a semiconductor die disposed over the package substrate[0020]; a frame surrounding the semiconductor die; and a plurality of conductive terminals disposed below the package substrate[0020].
Re claim 20 Link and Shimizu disclose the semiconductor package structure as claimed in claim 12, wherein a thickness of the core structure(156) is in a range of about 200 μm to about 2000 μm.
Conclusion
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/PATRICIA D VALENZUELA/Primary Examiner, Art Unit 2812
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