DETAILED ACTION
General Remarks
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the limitation “…wherein the etch stop pattern is completely surrounded by the interlayer insulating layer in a plan view”, (There is not a Figure showing a plan view related to the etch stop pattern and the interlayer insulating layer), must be shown or the feature(s) canceled from the claim(s). No new matter should be entered.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
Claim 4 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as
being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Re: claim 4, it recites the limitation “…wherein the etch stop pattern is completely surrounded by the interlayer insulating layer in a plan view…”. It is not clear how the etch stop layer is completely surrounded by the interlayer insulating layer in a plan view. This limitation is not explained and it does not show in the drawings. Therefore, it is indefinite. For the examination purpose and according to Fig. 4, the limitation “…wherein the etch stop pattern is completely surrounded by the interlayer insulating layer in a plan view…” is interpreted as “…wherein the etch stop pattern is completely surrounded by the interlayer insulating layer…”.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Notes: when present, semicolon separated fields within the parenthesis (; ;) represent, for example, as (30A; Fig 2B; [0128]) = (element 30A; Figure No. 2B; Paragraph No. [0128]). For brevity, the texts “Element”, “Figure No.” and “Paragraph No.” shall be excluded, though; additional clarification notes may be added within each field. The number of fields may be fewer or more than three indicated above. These conventions are used throughout this document.
Claims 1-7, 9-11,13-16, 18-19 are rejected under 35 U.S.C. 102 (a)(1) as being anticipated by Peng et al. (US 20220068930 A1, hereinafter Peng).
Re: Independent Claim 1, Peng teaches an integrated circuit device (Fig. 1K), comprising:
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Peng’s Figure 1K-Annotated.
a substrate (100 in [0012], Fig. 1K) having a memory cell area (R1 memory array region in [0012], Fig. 1K) and a peripheral circuit area (R2 peripheral circuit region in [0012], Fig. 1K) extending around the memory cell area (R1) when viewed in a plan view (as a 3D-dimensional device, the peripheral side around the memory cell area);
a plurality of cell transistors (transistors in [0012]) in the memory cell area (R1);
a peripheral circuit transistor (active devices as transistors in [0012]) in the peripheral circuit area (R2);
a capacitor structure (102 in [0013], Fig. 1K) including lower electrodes (104 in [0013], Fig. 1K) on the plurality of cell transistors (transistors in [0012]), a dielectric layer (108 in [0013], Fig. 1K) on a surface of the lower electrodes (104), an upper material layer (106b a conductive layer made of a B-doped SiGe layer in [0013], Fig. 1K) on the dielectric layer (108), and a metal plate layer (106a a conductive layer in [0013], Fig. 1K) on the upper material layer (106b);
an interlayer insulating layer (110-114a insulating layers 110, 114 made of SiO2 in [0014, 0016], Fig. 1K) on the metal plate layer (106a) in the memory cell area (R1) and on the peripheral circuit transistor (active devices as transistors in [0012]) in the peripheral circuit area (R2); and
an etch stop pattern (112 a stop layer made of silicon nitride or silicon oxynitride in [0015, 0016], Fig. 1K) in the interlayer insulating layer (110-114) at a boundary portion (Fig. 1K-Annotated) of the memory cell area (R1) and the peripheral circuit area (R2), the etch stop pattern (112) being spaced apart from a sidewall of the metal plate layer (106a) in a first direction (horizontal-direction, Fig. 1K-Annotated) parallel to an upper surface of the substrate (100) and extending in a second direction (vertical-direction, Fig. 1K-Annotated) perpendicular to the first direction.
Re: Claim 2, Peng discloses the integrated circuit device of claim 1, wherein a first level of an uppermost surface of the etch stop pattern (112) is higher (Fig. 1K-Annotated), relative to the upper surface of the substrate (100), than a second level of an uppermost surface of the metal plate layer (106a), a third level of a lowermost surface of the etch stop pattern (112) is higher (Fig. 1K-Annotated), relative to the upper surface of the substrate (100), than a fourth level of a lowermost surface of the metal plate layer (106a), and the first level is lower (Fig. 1K-Annotated), relative to the upper surface of the substrate (100), than a fifth level of an uppermost surface of the interlayer insulating layer (110-114).
Re: Claim 3, Peng discloses the integrated circuit device of claim 1, wherein, in the first direction (horizontal-direction, Fig. 1K-Annotated), a sidewall of the etch stop pattern (112) is arranged to face the sidewall of the metal plate layer (106a), and in the second direction (vertical-direction, Fig. 1K-Annotated), the etch stop pattern (112) is arranged to at least partially overlap the metal plate layer (106a).
Re: Claim 4, Peng discloses the integrated circuit device of claim 1, wherein the etch stop pattern (112) is completely surrounded (as a 3D-dimensional device, 112 is surrounded by 110-114) by the interlayer insulating layer (110-114).
Re: Claim 5, Peng discloses the integrated circuit device of claim 1, further comprising: a metal contact (126a in [0026], Fig. 1K) that extends through the interlayer insulating layer (110-114) in the second direction (vertical-direction, Fig. 1K-Annotated) and is electrically connected to the metal plate layer (106a) in the memory cell area (R1); and a peripheral circuit contact (126b in [0026], Fig. 1K) that extends through the interlayer insulating layer (110-114) in the second direction (vertical-direction, Fig. 1K-Annotated) and is electrically connected to the peripheral circuit transistor ([0012]) in the peripheral circuit area (R2).
Re: Claim 6, Peng discloses the integrated circuit device of claim 5, wherein a first level of a lowermost surface of the metal contact (126a in [0026], Fig. 1K) is lower, relative to the upper surface of the substrate (100), than a second level of an uppermost surface of the etch stop pattern (112), and a third level of a lowermost surface of the peripheral circuit contact (126b in [0026], Fig. 1K) is lower, relative to the upper surface of the substrate (100), than a fourth level of a lowermost surface of the etch stop pattern (112).
Re: Claim 7, Peng discloses the integrated circuit device of claim 5, wherein a length of the peripheral circuit contact (126b in [0026], Fig. 1K) in the second direction (vertical-direction, Fig. 1K-Annotated) is greater than a length of the metal plate layer (106a) in the second direction.
Re: Claim 9, Peng discloses the integrated circuit device of claim 1, wherein the etch stop pattern (112) includes a material (made of silicon nitride or silicon oxynitride in [0015, 0016, 0024]) having an etch selectivity (etching process in [0024]) with respect to the interlayer insulating layer (110-114).
Re: Claim 10, Peng discloses the integrated circuit device of claim 9, wherein the interlayer insulating layer (110-114) includes silicon oxide (made of SiO2 in [0014, 0016]) and the etch stop pattern (112) includes at least one of amorphous silicon, silicon nitride, silicon oxynitride, silicon carbonitride, and silicon germanium (made of silicon nitride or silicon oxynitride in [0015, 0016]).
Re: Independent Claim 11, Peng teaches an integrated circuit device (Fig. 1K), comprising:
a substrate (100 in [0012], Fig. 1K) having a memory cell area (R1 memory array region in [0012], Fig. 1K) and a peripheral circuit area (R2 peripheral circuit region in [0012], Fig. 1K) extending around the memory cell area (R1) when viewed in a plan view (as a 3D-dimensional device, the peripheral side around the memory cell area);
a plurality of cell transistors (transistors in [0012]) in the memory cell area (R1);
a peripheral circuit transistor (active devices as transistors in [0012]) in the peripheral circuit area (R2);
a capacitor structure (102 in [0013], Fig. 1K) including lower electrodes (104 in [0013], Fig. 1K) on the plurality of cell transistors (transistors in [0012]), a dielectric layer (108 in [0013], Fig. 1K) on a surface of the lower electrodes (104), an upper material layer (106b a conductive layer made of a B-doped SiGe layer in [0013], Fig. 1K) on the dielectric layer (108), and a metal plate layer (106a a conductive layer in [0013], Fig. 1K) on the upper material layer (106b);
an interlayer insulating layer (110-114a insulating layers 110, 114 made of SiO2 in [0014, 0016], Fig. 1K) over the metal plate layer (106a) in the memory cell area (R1) and over the peripheral circuit transistor (active devices as transistors in [0012]) in the peripheral circuit area (R2);
a first etch stop pattern (112-1 a stop layer made of silicon nitride or silicon oxynitride in [0015, 0016], Fig. 1K) in the interlayer insulating layer (110-114) at a boundary portion (Fig. 1K-Annotated) of the memory cell area (R1) and the peripheral circuit area (R2), the first etch stop pattern (112) spaced apart from a sidewall of the metal plate layer (106a) in a first direction (horizontal-direction, Fig. 1K-Annotated) parallel to an upper surface of the substrate (100) and extending in a second direction (vertical-direction, Fig. 1K-Annotated) perpendicular to the first direction; and
a second etch stop pattern (112-2 a portion of the stop layer 112 made of silicon nitride or silicon oxynitride in [0015, 0016], Fig. 1K) on the interlayer insulating layer (110-114) in the memory cell area (R1), the second etch stop pattern (112-2) spaced apart from an uppermost surface of the metal plate layer (106a) in the second direction (vertical-direction, Fig. 1K-Annotated) and extending in the first direction (horizontal-direction, Fig. 1K-Annotated).
Re: Claim 13, Peng discloses the integrated circuit device of claim 11, further comprising: a metal contact (126a in [0026], Fig. 1K) that extends through the second etch stop pattern (112-2) and the interlayer insulating layer (110-114) in the second direction (vertical-direction, Fig. 1K-Annotated) and is electrically connected to the metal plate layer (106a) in the memory cell area (R1); and a peripheral circuit contact (126b in [0026], Fig. 1K) that extends through the interlayer insulating layer (110-114) in the second direction (vertical-direction, Fig. 1K-Annotated) and is electrically connected to the peripheral circuit transistor ([0012]) in the peripheral circuit area (R2).
Re: Claim 14, Peng discloses the integrated circuit device of claim 13, wherein a sidewall of the metal contact (126a in [0026], Fig. 1K) contacts the second etch stop pattern (112-2) and the interlayer insulating layer (110-114), and, a sidewall of the peripheral circuit contact (126b in [0026], Fig. 1K) contacts the interlayer insulating layer (110-114), and the sidewall of the peripheral circuit contact (126b) does not contact the second etch stop pattern (112-2).
Re: Claim 15, Peng discloses the integrated circuit device of claim 11, wherein the interlayer insulating layer (110-114) includes silicon oxide (made of SiO2 in [0014, 0016]) and the first (112-1) and second (112-2) etch stop patterns include a same material as each other (in [0015,0016]), and each of the first and second etch stop patterns includes at least one of amorphous silicon, silicon nitride, silicon oxynitride, silicon carbonitride, and silicon germanium (made of silicon nitride or silicon oxynitride in [0015, 0016]).
Re: Independent Claim 16, Peng teaches an integrated circuit device (Fig. 1K), comprising:
a substrate (100 in [0012], Fig. 1K) including a memory cell area (R1 memory array region in [0012], Fig. 1K) and a peripheral circuit area (R2 peripheral circuit region in [0012], Fig. 1K) on at least one side of the memory cell area (R1);
a plurality of cell transistors (transistors in [0012]) in the memory cell area (R1);
a peripheral circuit transistor (active devices as transistors in [0012]) in the peripheral circuit area (R2);
a capacitor structure (102 in [0013], Fig. 1K) including lower electrodes (104 in [0013], Fig. 1K) on the plurality of cell transistors (transistors in [0012]), a dielectric layer (108 in [0013], Fig. 1K) on a surface of the lower electrodes (104), an upper material layer (106b a conductive layer made of a B-doped SiGe layer in [0013], Fig. 1K) on the dielectric layer (108), and a metal plate layer (106a a conductive layer in [0013], Fig. 1K) on the upper material layer (106b);
an interlayer insulating layer (110-114a insulating layers 110, 114 made of SiO2 in [0014, 0016], Fig. 1K) over the metal plate layer (106a) in the memory cell area (R1) and over the peripheral circuit transistor (active devices as transistors in [0012]) in the peripheral circuit area (R2);
a first etch stop pattern (112-1 a stop layer made of silicon nitride or silicon oxynitride in [0015, 0016], Fig. 1K) in the interlayer insulating layer (110-114) at a boundary portion (Fig. 1K-Annotated) of the memory cell area (R1) and the peripheral circuit area (R2), the first etch stop pattern (112) spaced apart from a sidewall of the metal plate layer (106a) in a first direction (horizontal-direction, Fig. 1K-Annotated) parallel to an upper surface of the substrate (100) and extending in a second direction (vertical-direction, Fig. 1K-Annotated) perpendicular to the first direction;
a metal contact (126a in [0026], Fig. 1K) that extends through the interlayer insulating layer (110-114) in the second direction (vertical-direction, Fig. 1K-Annotated) and is electrically connected to the metal plate layer (106a) in the memory cell area (R1); and a peripheral circuit contact (126b in [0026], Fig. 1K) that extends through the interlayer insulating layer (110-114) in the second direction (vertical-direction, Fig. 1K-Annotated) and is electrically connected to the peripheral circuit transistor ([0012]) in the peripheral circuit area (R2), wherein the first etch stop pattern (112-1) includes a material ([0015,0016]) having an etch selectivity ([0021]) with respect to the interlayer insulating layer (110-114).
Re: Claim 18, Peng discloses the integrated circuit device of claim 16, further comprising
a second etch stop pattern (112-2 a portion of the stop layer 112 made of silicon nitride or silicon oxynitride in [0015, 0016], Fig. 1K) on the interlayer insulating layer (110-114) in the memory cell area (R1), the second etch stop pattern (112-2) spaced apart from an uppermost surface of the metal plate layer (106a) in the second direction (vertical-direction, Fig. 1K-Annotated) and extending in the first direction (horizontal-direction, Fig. 1K-Annotated), wherein the second etch stop pattern (112-2) and the first etch stop pattern (112-1) include a same material as each other (in [0015,0016]).
Re: Claim 19, Peng discloses the integrated circuit device of claim 18, wherein the first etch stop pattern (112-1) is completely surrounded (112-1 is surrounded by 110-114 in horizontal direction and y-direction as a three-dimensional device) by the interlayer insulating layer (110-114), and the second etch stop pattern (112-2) is on the interlayer insulating layer (110-114).
Claim Rejections - 35 USC § 103
The following is a quotation of AIA 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 17 is/are rejected under AIA 35 U.S.C. 103 as being unpatentable over Peng.
Re: Claim 17, Peng discloses the integrated circuit device of claim 16, wherein a first level of an uppermost surface of the metal plate layer (106a) is lower, relative to the upper surface of the substrate (100), than a second level of an uppermost surface of the first etch stop pattern (112-1), and a fourth level of a lowermost surface of the peripheral circuit contact (126b) is lower, relative to the upper surface of the substrate (100), than a fifth level of a lowermost surface of the first etch stop pattern (112-1).
Peng does not disclose a third level of a lowermost surface of the metal contact is lower, relative to the upper surface of the substrate, than the first level.
However, the Applicant has not presented persuasive evidence that the claimed
“third level of a lowermost surface of the metal contact is lower, relative to the upper surface of the substrate, than the first level” is for a particular purpose that is critical to the overall claimed invention (i.e. the invention would not work without the specific claimed third level of a lowermost surface of the metal contact is lower, relative to the upper surface of the substrate, than the first level). Also, the applicant has not shown that the claimed “difference of third level of a lowermost surface of the metal contact lower, relative to the upper surface of the substrate, than the first level” produces a result that was new or unexpected enough to patentably distinguish the claimed invention over the cited prior art. At meantime, Peng discloses “third level of a lowermost surface of the metal contact is similar, relative to the upper surface of the substrate, than the first level (of an uppermost surface of the metal plate layer)”, therefore, the level relation between the metal plate layer and the metal contact layer is a result effective variable. It has been held that is not inventive to discover the optimum level relation between the metal plate layer and the metal contact layer by routine experimentation (In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955), MPEP 2144.05 II).
Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to add a third level of a lowermost surface of the metal contact lower, relative to the upper surface of the substrate, than the first level to the rest of the claimed invention to improve the electrical performance of the semiconductor device ([0005]).
Claim(s) 8, 20 is/are rejected under AIA 35 U.S.C. 103 as being unpatentable over Peng in view of Kim (US 20220157928 A1, hereinafter Kim).
Re: Claim 8, Peng discloses the integrated circuit device of claim 1, wherein the upper material layer (106b) and the metal plate layer (106a) are an upper electrode of the capacitor structure (102), the upper material layer (106b) includes a silicon germanium layer (made of SiGe layer in [0013]).
Peng does not expressly disclose the metal plate layer includes tungsten.
However, in the same semiconductor device field of endeavor, Kim discloses a metal plate layer (110 an upper electrode in [0032]) includes tungsten (made of tungsten in [0032]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include the Kim’s feature of a metal plate layer includes tungsten to Peng’s device to tune the electrical properties of the connection having a low-resistivity electrode ([0032], Kim).
Re: Claim 20, Peng discloses the integrated circuit device of claim 18, wherein the upper material layer (106b) includes a silicon germanium layer (made of SiGe layer in [0013]), the interlayer insulating layer (110-114) includes silicon oxide (made of SiO2 in [0014, 0016]), and each of the second (112-2) and first (112-1) etch stop patterns includes at least one of amorphous silicon, silicon nitride, silicon oxynitride, silicon carbonitride, and silicon germanium (made of silicon nitride or silicon oxynitride in [0015, 0016]).
Peng does not expressly disclose the metal plate layer includes tungsten.
However, in the same semiconductor device field of endeavor, Kim discloses a metal plate layer (110 an upper electrode in [0032]) includes tungsten (made of tungsten in [0032]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include the Kim’s feature of a metal plate layer includes tungsten to Peng’s device to tune the electrical properties of the connection having a low-resistivity electrode ([0032], Kim).
Claim(s) 12 is/are rejected under AIA 35 U.S.C. 103 as being unpatentable over Peng in view of Kishida (US 20070272963 A1, hereinafter Kishida) and further in view of Ohuchi (US 7122463 B2, hereinafter Ohuchi).
Re: Claim 12, Peng discloses the integrated circuit device of claim 11, wherein in the first direction (horizontal direction, Fig. 1K), a sidewall of the first etch stop pattern (112-1) faces the sidewall of the metal plate layer (106a), and in the second direction (horizontal direction, Fig. 1K), a lower surface of the second etch stop pattern (112-2) faces the uppermost surface of the metal plate layer (106a).
Peng does not expressly disclose wherein the first etch stop pattern and the second etch stop pattern are spaced apart from each other in the second direction.
However, in the same semiconductor device field of endeavor, Kishida discloses a connection (236a a conductor plug in [0060], Fig. 4) disposed at a boundary between the memory cell region and a peripheral circuit region (Fig. 4).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include the Kishida’s feature of a connection disposed at a boundary between the memory cell region and a peripheral circuit region to Peng’s device to add more connections of the device ([0062], Kishida).
Peng modified by Kishida does not expressly disclose wherein the first etch stop pattern and the second etch stop pattern are spaced apart from each other in the second direction.
However, in the same semiconductor device field of endeavor, Ohuchi discloses a hole to form a connector, including an etch stop layer (103 in Col. 7, lines 40-43, Fig.1), wherein after etching a corner portion of the etch stop layer (103) is removed (Fig. 1, (5))
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include the Ohuchi’s feature of a hole to form a connector, including an etch stop layer, wherein after etching a corner portion of the etch stop layer is removed to Peng’s device for forming an opening in an insulating film overlying a semiconductor substrate (Col. 1, lines 5-9, Ohuchi).
The combination of Peng, Kishida and Ohuchi results in wherein the first etch stop pattern (Peng’s 112-1) and the second etch stop pattern (Peng’s 112-1) are spaced apart (Kishida’s connector applied to Peng, to form the additional connection and after etching, a corner of 112-1 is removed, as showed in Ohuchi’s device, then Peng’s 112-1 and Peng’s 112-2 are spaced apart) from each other in the second direction (vertical direction, Peng).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
Huang et al. (US 20190319030 A1) teaches “SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME”. This document is related to a semiconductor structure comprising a substrate having a memory region and a logic region; forming a stack structure on the memory region and a gate structure on the logic region; forming a first cap layer on the stack structure and the gate structure; performing an oxidation process to form an oxide layer on the first cap layer; forming a second cap layer on the oxide layer; and removing part of the second cap layer, part of the oxide layer, and part of the first cap layer on the logic region to form a spacer adjacent to the gate structure.
Kim et al. (US 20100244110 A1) teaches “SEMICONDUCTOR DEVICE”. This document is related to a semiconductor device including a first transistor, a second transistor, an insulation interlayer pattern and a capacitor. The first transistor is formed in a first region of a substrate. The first transistor has a pillar protruding upwardly from the substrate and an impurity region provided in an upper portion of the pillar. The second transistor is formed in a second region of the substrate. The insulation interlayer pattern is formed on the first region and the second region to cover the second transistor and expose an upper surface of the pillar. The insulation interlayer pattern has an upper surface substantially higher than the upper surface of the pillar in the first region. The capacitor is formed on the impurity region in the upper portion of the pillar and is electrically connected to the impurity region.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SANDRA M RODRIGUEZ VILLANUEVA whose telephone number is (571)272-1936. The examiner can normally be reached Monday to Friday 8:00am-5:00pm (EST).
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jessica Manno can be reached at (571) 272-2339. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/SANDRA MILENA RODRIGUEZ VILLANUEVA/Examiner, Art Unit 2898
/JESSICA S MANNO/SPE, Art Unit 2898
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