DETAILED ACTION
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 3/25/26 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1-5 are rejected under 35 U.S.C. 102(a)(1) and 102(a)(2) as being anticipated by Su (US 2021/0335792).
As to claim 1, Su teaches a semiconductor device structure (see annotated fig. 24 below), comprising:
a first dielectric layer (143/147) disposed over a semiconductor substrate (101, [0074]);
a second dielectric layer (157) disposed over the first dielectric layer (143/147, [0081]);
a first conductive plug (149/151) disposed in the first dielectric layer (143/147, [0075]),
wherein an upper portion (149A/151A) of the first conductive plug (149/151) extends into the second dielectric layer (157, [0078] – [0079]);
a silicide layer (155) disposed in the second dielectric layer (157) and covering a top surface and sidewalls of the upper portion (149A/151A) of the first conductive plug (149/151, [0079]); and
a second conductive plug (159) disposed in the second dielectric layer (157) and directly over the first conductive plug (149/151) and the silicide layer (155, [0081]).
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As to claim 2, Su further teaches the silicide layer (155) is in direct contact with the first conductive plug (149/151, see fig. above).
As to claim 3, Su further teaches the silicide layer (155) is in direct contact with the first dielectric layer (147, the bottom surface of the silicide contacts the top surface of the first dielectric layer.).
As to claim 4, Su further teaches a first liner (151) separating the first conductive plug (149/151) from the first dielectric layer (143/147) and the semiconductor substrate (101, see fig above).
As to claim 5, Su further teaches the first liner (151) extends between the silicide layer (155) and the sidewalls of the upper portion (149A/151A) of the first conductive plug (149/151, see fig. above).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 6 and 7 are rejected under 35 U.S.C. 103 as being unpatentable over Su.
As to claim 6, Su doesn’t explicitly teach a second liner separating the second conductive plug from the second dielectric layer and the silicide layer. However, depositing liners between a plug and the surrounding dielectric layer is known in the art and would have been obvious so as to prevent diffusion of the metal ions into the dielectric layer.
As to claim 7, Su further teaches the second liner is in direct contact with the silicide layer (see annotated figure above, the liner would be similar to the one shown in the first conductive plug, therefore the silicide would be in direct contact with it.).
Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over Su in view of Pandit (US 2022/0375898).
As to claim 8, Su does not teach a third conductive plug disposed in the first dielectric layer and penetrating through the second dielectric layer, wherein the first conductive plug, the silicide layer and the second conductive plug are disposed in a pattern-dense region, and the third conductive plug is disposed in a pattern-loose region; and a third liner separating the third conductive plug from the semiconductor substrate, the first dielectric layer and the second dielectric layer.
However, the first and second conductive plugs of Su are contacts that connect to a pattern-dense region (i.e. they connect to source/drain regions of a transistor, [0075]). Su only shows the pattern-dense region that contains the active circuitry. Su is silent on the pattern-loose region (i.e. where there is no active circuitry to connect to).
However, in the same field of endeavor, Pandit teaches first and second conductive plugs in a pattern-dense region in first and second dielectric layers and a third conductive plug in a pattern-loose region penetrating the second dielectric layer (see annotated fig. 1B below).
Therefore, it would have been obvious to one of ordinary skill in the art at the time the invention was filed that there would be a third conductive plug in a pattern-loose region of Su so as to enable electrical coupling between the metallization layers and the device/package substrate, as taught by Pandit ([0043]).
Pandit doesn’t explicitly teach a third liner separating the third conductive plug from the surrounding dielectric layers. However, liners are very well-known in the art and would have been obvious so as to prevent metal diffusion into the dielectric layers.
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Conclusion
Any response to this Office Action should be faxed to (571) 273-8300 or mailed to:
Commissioner for Patents
P.O. Box 1450
Alexandria, VA 22313-1450
Hand-Delivered responses should be brought to:
Customer Service Window
Randolph Building
401 Dulany Street
Alexandria, VA 22313
Any inquiry concerning this communication or earlier communications from the examiner should be directed to KAREN M KUSUMAKAR whose telephone number is (571)270-3520. The examiner can normally be reached on Monday – Friday from 7:30a – 4:30p EST.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Fernando Toledo can be reached on 571-272-1867. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/KAREN KUSUMAKAR/
Primary Examiner, Art Unit 2897
9/18/26
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