DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of claims 1 through 8 in the reply filed on 7/15/26 is acknowledged.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 10/31/2024 was filed. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1 through 7 is/are rejected under 35 U.S.C. 102a1 as being anticipated by Van (US 2015/0084063)
Regarding claim 1.
Van teaches:
A transistor (fig 5:60; [para 0053]) comprising: a substrate (fig 5:64; [para 0053]);
a drain layer (fig 5:64; [para 0055]) formed within the substrate (fig 5:64,66,68; [para 0055]) at a first side of the substrate (fig 5:64,66,68; [para 0055]);
a first well implant (fig 5:76; [para 0053]) formed within the substrate (fig 5:64,66,68; [para 0055]) at a second side of the substrate (fig 5:64,66,68; [para 0055]), the first well implant having a first implant depth;
a second well implant (fig 5 annotated; [para 0053]) formed within the substrate (fig 5:64,66,68; [para 0055]) at the second side of the substrate (fig 5:64,66,68; [para 0055]), the second well implant (fig 5 annotated; [para 0053]) having a second implant depth, wherein the second implant depth is greater than the first implant depth (fig 5);
a third well implant (fig 5 annotated; [para 0053]) formed within the substrate (fig 5:64,66,68; [para 0055]) at the second side of the substrate (fig 5:64,66,68; [para 0055]), the third well implant having a third implant depth, wherein the third implant depth is greater than the second implant depth;
and a gate (fig 5:84; [para 0054]) formed at the second side of the substrate (fig 5:64,66,68; [para 0055]), wherein the gate (fig 5:84; [para 0054]) overlaps the first well implant (fig 5:76; [para 0053]) by a first distance, the gate (fig 5:84; [para 0054]) overlaps the second well implant by a second distance and the gate (fig 5:84; [para 0054]) overlaps the third well implant by a third distance.
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Regarding claim 2.
Van teaches the transistor of claim 1,
wherein the first distance is greater than the second distance (fig 5 annotated).
Regarding claim 3.
Van teaches the transistor of claim 2,
wherein the second distance is greater than the third distance (fig 5 annotated).
Regarding claim 4
Van teaches the transistor of claim 1,
wherein the substrate (fig 5:64,66,68; [para 0055]) comprises a first type dopant (fig 5:N) and the first well implant, the second well implant and the third well implant comprises a second type dopant (fig 5:P).
Regarding claim 5
Van teaches the transistor of claim 4,
wherein the substrate (fig 5:64,66,68; [para 0055]) comprises a first concentration (N) of the first type dopant and the drain layer (fig 5:64; [para 0055]) comprises a second concentration (N+) of the first type dopant.
Regarding claim 6
Van teaches the transistor of claim 5,
wherein the second concentration (fig 5, N+) is greater than the first concentration (fig 5, N).
Regarding claim 7.
Van teaches the transistor of claim 6,
wherein the first type dopant comprises an n-type dopant (fig 5:N) and the second type dopant comprises a p-type dopant (fig 5:P).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 8 is/are rejected under 35 U.S.C. 103 as being unpatentable over Van (US 2015/0084063) as applied to claim 6 and further in view Ryu (US 2010/0301335)
Regarding claim 8.
Van teaches the transistor of claim 6,
Van does not teach the first type dopant comprises a p-type dopant and the second type dopant comprises an n-type dopant.
Ryu teaches:
the first type dopant (fig 4:140,145,150,155; [para 0046]) comprises a p-type dopant (fig 4:P; [para 0046]) and the second type dopant (fig 4:160; [para 0046]) comprises an n-type dopant (fig 4:N; [para 0046]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention for the first type dopant comprises a p-type dopant and the second type dopant comprises an n-type dopant in order to provide more flexibility in circuit design by enabling the formation of complementary transistor devices.
Conclusion
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/D.J.G/Examiner, Art Unit 2817 /NICHOLAS J TOBERGTE/Primary Examiner, Art Unit 2817
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