DETAILED ACTION
1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Cross-Reference to Related Applications
2. This application is a CON of PCT/JP2022/043169 11/22/2022.
Preliminary amendment
3. Preliminary amendment filed on 06/14/2024 has been acknowledged and considered.
In the Preliminary amendment, the applicants have been amended the specification and claims 3, 7-8 and 11-15, canceled claims 16-20 and added new claims 21-22.
Claims 1-15 and 21-22 are currently pending in the application.
Oath/Declaration
4. The oath/declaration filed on 06/14/2024 is acceptable.
Priority
5. Receipt is acknowledged of papers submitted under 35 U.S.C. 119(a)-(d), which papers have been placed of record in the file.
Information Disclosure Statement
6. The office acknowledges receipt of the following items from the applicant:
Information Disclosure Statement (IDS) filed on 06/07/2024 and 06/14/2024.
Specification
7. The specification is objected to for the following reason: The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed (see MPEP 606.01).
Claim Objection
8. Claims 1-15 are objected to because of the following reasons:
In claim 1, line 10, insert of -- : -- after “includes”.
Claims 2-15 are depend on claim 1, then, they are also being objected.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
9. Claims 1, 10, 15 and 21-22 are rejected under 35 U.S.C. 103(a) as being unpatentable over OKADA H (JP-201010262-A) in view of HAMADA K (CN-105723499-A)
Regarding claim 1, OKADA discloses a semiconductor device comprising:
a PN junction diode (6) disposed over a silicon carbide substrate (1, see substrate 502, Fig. 5 in Jeon et al. (U. S. Publication No. 2019/0305123 A1)); and
a high electron mobility transistor disposed over the PN junction diode (6),
the high electron mobility transistor includes:
a channel layer (5) including a first nitride semiconductor layer,
a barrier layer (3) including a second nitride semiconductor layer in contact with the channel layer,
a buffer layer (2) including a third nitride semiconductor layer (Note: the OKADA H reference lacks an explanation of the feature of 3/5/2 numeral references. However, the examiner should be certain of these features by comparing to the features of 508/506/504 in Fig. 5 of Jeon et al. (U.S. Publication No. 2019/0305123 A1)
a source electrode (S) in contact with a first region of the barrier layer (3),
a drain electrode (D) in contact with a second region of the barrier layer (3), and
a gate electrode (G) provided between the source electrode (S) and the drain electrode (D) (Fig. 1(b) and English Text).
OKADA H discloses the features of the claimed invention as discussed above, but does not disclose wherein: the PN junction diode includes:
a silicon carbide epitaxial layer of a first conduction type disposed over the silicon carbide substrate; and
an electric field relaxation region of a second conduction type formed in the silicon carbide epitaxial layer, the second conduction type being configured to flow current in a direction opposite being to that of the first conduction type;
a buffer layer including a third nitride semiconductor layer provided between the channel layer and the silicon carbide epitaxial layer, the buffer layer having a bandgap larger than that of the silicon carbide epitaxial layer; and the silicon carbide epitaxial layer is electrically connected to the source electrode;
the electric field relaxation region is electrically connected to the drain electrode; and in a plan view, the electric field relaxation region includes a region extended from the drain electrode.
HAMADA K, however, discloses the PN junction diode (10) includes:
a silicon carbide epitaxial layer (12) of a first conduction type (P-type) disposed over the silicon carbide substrate (11); and
an electric field relaxation region (14) of a second conduction type (N-type) formed in the silicon carbide epitaxial layer (12), the second conduction type (N-type) being configured to flow current in a direction opposite being to that of the first conduction type (P-type) (Fig. 5 and English Text).
It would have been obvious to one having ordinary skilled in the art before the effective filing date of the claimed invention to modify the teaching of OKADA H to provide wherein: the PN junction diode includes:
a silicon carbide epitaxial layer of a first conduction type disposed over the silicon carbide substrate; and
an electric field relaxation region of a second conduction type formed in the silicon carbide epitaxial layer, the second conduction type being configured to flow current in a direction opposite being to that of the first conduction type as taught by HAMADA K for a purpose of improving the performance of the semiconductor device.
OKADA H and HAMADA K (citations to OKADA H unless otherwise noted) discloses a buffer layer (2) including a third nitride semiconductor layer will be obviously provided between the channel layer (5) and the silicon carbide epitaxial layer (12) and the silicon carbide epitaxial layer (12) will be obviously electrically connected to the source electrode; the electric field relaxation region (14) will be obviously electrically connected to the drain electrode (S); and in a plan view, the electric field relaxation region (14) includes a region extended from the drain electrode (D) (Fig. 5 in HAMADA K).
OKADA H and HAMADA K disclose the features of the claimed invention as discussed above, but does not disclose the buffer layer having a bandgap larger than that of the silicon carbide epitaxial layer.
However, it would have been an obvious matter of design choice to form the buffer layer having a bandgap larger than that of the silicon carbide epitaxial layer, since such a modification as discussed above would have involved a mere change in the size of a component. A change in size is generally recognized as being within the level of ordinary skill in the art. In re Rose, 105 USPQ 237 (CCPA 1955).
Therefore, claim 1 is obviously rendered over OKADA H and HAMADA K.
Regarding claim 10, OKADA H and HAMADA K (citations to OKADA H unless otherwise noted) discloses wherein the first conduction type is a p type, the second conduction type is an n type, and the PN junction diode (6) is a lateral diode having a dominant current path in a direction parallel to a main plane of the silicon carbide epitaxial layer (12, Fig. 5 in HAMADA K).
Regarding claim 15, OKADA H and HAMADA K (citations to OKADA H unless otherwise noted) discloses the PN junction diode (6) is a lateral diode having a dominant current path in a direction parallel to a main plane of the silicon carbide epitaxial layer (12, Fig. 5 in HAMADA K).
Regarding claim 21, OKADA H discloses a semiconductor device comprising:
a PN junction diode (6) disposed over a silicon carbide substrate (1, see substrate 502, Fig. 5 in Jeon et al. (U. S. Publication No. 2019/0305123 A1)); and
a high electron mobility transistor disposed over the PN junction diode (6),
the high electron mobility transistor includes:
a channel layer (5) including a first nitride semiconductor layer,
a barrier layer (3) including a second nitride semiconductor layer in contact with the channel layer,
a buffer layer (2) including a third nitride semiconductor layer (Note: the OKADA H reference lacks an explanation of the feature of 3/5/2 numeral references. However, the examiner should be certain of these features by comparing to the features of 508/506/504 in Fig. 5 of Jeon et al. (U.S. Publication No. 2019/0305123 A1)
a source electrode (S) in contact with a first region of the barrier layer (3),
a drain electrode (D) in contact with a second region of the barrier layer (3), and
a gate electrode (G) provided between the source electrode (S) and the drain electrode (D) (Fig. 1(b) and English Text).
OKADA H discloses the features of the claimed invention as discussed above, but does not disclose wherein: the PN junction diode includes:
a silicon carbide epitaxial layer of a first conduction type disposed over the silicon carbide substrate; and
an electric field relaxation region of a second conduction type formed in the silicon carbide epitaxial layer, the second conduction type being configured to flow current in a direction opposite being to that of the first conduction type;
a buffer layer including a third nitride semiconductor layer provided between the channel layer and the silicon carbide epitaxial layer; and the silicon carbide epitaxial layer is electrically connected to the source electrode;
the electric field relaxation region is electrically connected to the drain electrode; and the PN junction diode is a lateral diode having a dominant current path in a direction parallel to a main plane of the silicon carbide epitaxial layer.
HAMADA K, however, discloses the PN junction diode (10) includes:
a silicon carbide epitaxial layer (12) of a first conduction type (P-type) disposed over the silicon carbide substrate (11); and
an electric field relaxation region (14) of a second conduction type (N-type) formed in the silicon carbide epitaxial layer (12), the second conduction type (N-type) being configured to flow current in a direction opposite being to that of the first conduction type (P-type) (Fig. 5 and English Text).
It would have been obvious to one having ordinary skilled in the art before the effective filing date of the claimed invention to modify the teaching of OKADA H to provide wherein: the PN junction diode includes:
a silicon carbide epitaxial layer of a first conduction type disposed over the silicon carbide substrate; and
an electric field relaxation region of a second conduction type formed in the silicon carbide epitaxial layer, the second conduction type being configured to flow current in a direction opposite being to that of the first conduction type as taught by HAMADA K for a purpose of improving the performance of the semiconductor device.
OKADA H and HAMADA K (citations to OKADA H unless otherwise noted) discloses a buffer layer (2) including a third nitride semiconductor layer will be obviously provided between the channel layer (5) and the silicon carbide epitaxial layer (12) and the silicon carbide epitaxial layer (12) will be obviously electrically connected to the source electrode; the electric field relaxation region (14) will be obviously electrically connected to the drain electrode (S); and the PN junction diode (6) is a lateral diode having a dominant current path in a direction parallel to a main plane of the silicon carbide epitaxial layer (12) (Fig. 5 in HAMADA K).
Therefore, claim 21 is obviously rendered over OKADA H and HAMADA K.
Regarding claim 22, OKADA H and HAMADA K (citations to OKADA H unless otherwise noted) discloses wherein in a plan view, the electric field relaxation region (12 in HAMADA K) includes a region extended from the drain electrode (D)
10. Claims 8-9 are rejected under 35 U.S.C. 103(a) as being unpatentable over OKADA H and HAMADA K in view of Hirler et al., hereafter “Hirler” (U.S. Publication No. 2010/0264462 A1).
Regarding claim 8, OKADA H and HAMADA K disclose the features of the claimed invention as discussed above including wherein the buffer layer (3) is AlxGa1-xN, but does not disclose wherein the buffer layer having an aluminum (Al) composition X greater than 30%.
Hirler, however, discloses the buffer layer (AlGaN) (17, Fig. 1) has an Aluminum content is low, that is to say less than 10% (para [0050]).
The selection of the claimed device parameters would have been obvious to one having ordinary skill in the art before the effective filing date was made to provide wherein the buffer layer having an aluminum (Al) composition within the claimed range, since it is well settles that when the general conditions of a claim are discloses in the prior art, discovering the optimum or workable ranges involves only routine skill in the art. In re Aller, 105 USPQ 233.
Regarding claim 9, OKADA H, HAMADA K and Hirler (citations to OKADA H unless otherwise noted) discloses the buffer layer (17) has AlN (Fig. 1 and para [0050] in Hirler).
Allowable Subject Matter
11. The following is a statement of reason for the indication of allowable subject matter:
Claims 2-7 and 11-14 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Cited Prior Arts
12. The prior art made of record and not relied upon is considered pertinent to applicant’s disclosure.
DECOUTERE S (EP-3032379-A1) discloses an integrated circuit (1) comprising a first III-N transistor (5) having a source region (8) and a second III-N transistor (6) having a source region (9), both transistors being monolithically integrated on a common silicon substrate (2) of a first doping type and separated from each-other by an isolation region (7),the substrate (2) comprising underneath the first transistor (5) a well (3) of a first doping type electrically connected to the source region (8) of the first transistor (5) and comprising underneath the second transistor (6) a well (4) of a second doping type electrically connected to the source region (9) of the second transistor (6), thereby forming a junction diode (10) in the substrate (2) between the sources (8,9) of the first (5) and the second (6) transistor (Fig. 3 and English Text).
Conclusion
13. Any inquiry concerning this communication or earlier communications from the examiner should be directed to Phuc T. Dang whose telephone number is 571-272-1776. The examiner can normally be reached on 8:00 am-5:00 pm.
If attempts to reach the examiner by telephone are unsuccessful, the examiner's supervisor, Jacob Choi can be reached on 469-295-9060. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/PHUC T DANG/Primary Examiner, Art Unit 2897
Prosecution Insights