DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 6/7/2024 was filed. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Specification
The abstract is consistent with the requirements set forth in the MPEP 608.01(b).
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
The following title is suggested: IMAGE SENSOR COMPRISING TRANSMISSION GATE
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 1-20 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the enablement requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to enable one skilled in the art to which it pertains, or with which it is most nearly connected, to make and/or use the invention. Specifically, claim 1 recites “a third stack, attached to the second stack and comprising a logic transistor configured to provide signals to the pixel gate and to the transmission gate” in lines 18-19; claim 12 recites “a third stack, attached to the second stack, the third stack comprising a logic transistor configured to provide signals to the pixel gate and the transmission gate” in lines 18-19; and claim 18 recites “wherein the third stack includes a logic transistor configured to provide signals to the pixel gate and the transmission gate” in lines 25-26. The specification simply discloses that the logic transistor is configured to provide signals to the transmission gate ([0004]-[0006]) but there is no description or drawings that show how the logic transistor in the third stack is directly or indirectly connected to the transmission gate in the first stack in order for one of ordinary skill in the art would make the connected or configure the logic transistor to provide signals to the transmission gate. The drawings show an electrical connection between the logic transistor and the pixel gate (fig. 4) but fails to show any connection between the logic transistor and the transmission gate in any of the drawings or provide any explanation on how the connection or configuration is done. Claims 2-11, 13-17 and 19-20 are also rejected under 35 U.S.C. 112(a) as failing to comply with the enablement requirement for being dependent on claims 1, 12 and 18.
Allowable Subject Matter
Regarding claim 1, the closest prior art Jang et al. US PGPub. 2023/0081238 teaches an image sensor (100, fig. 2) [0025] comprising: a first stack (SUB1) comprising a first semiconductor substrate (110, fig. 2) [0030] having a first surface (bottom) and a second surface (top) that is opposite to the first surface, a photoelectric conversion region (PD, fig. 2) [0027] in the first semiconductor substrate (110), a floating diffusion region (FD, fig. 2) [0044] arranged in the first semiconductor substrate (110) and configured to store charges transferred from the photoelectric conversion region (PD), a transmission gate (transfer gate TG, fig. 2) [0044] on the first surface (bottom) of the first semiconductor substrate (110),
a second stack (SUB2, fig. 2), attached to the first stack (SUB1), the second stack (SUB2) comprising a second semiconductor substrate (120, fig. 2) [0031] having a first surface (bottom) and a second surface (top) that is opposite to the first surface, a pixel gate (PXT, fig. 2) [0045] arranged on the first surface of the second semiconductor substrate or on the second surface (top) of the second semiconductor substrate (120), the pixel gate (PXT) being electrically connected (fig. 2) with the floating diffusion region (FD), and a gate spacer (176, fig. 2-3) [0045] on a sidewall of the pixel gate (PXT); and a third stack (SUB3), attached to the second stack (SUB2) and comprising a logic transistor (LCT, fig. 2) [0029] (Jang et al., fig. 2). But Jang fails to teach and a first etch stop film arranged on an upper surface and a sidewall of the transmission gate (TG) and on the first surface of the first semiconductor substrate (110); and a third stack (SUB3), attached to the second stack (SUB2) and comprising a logic transistor (LCT) configured to provide signals to the pixel gate (PXT) and to the transmission gate (TG). Claims 1-20 would be allowable if rewritten or amended to overcome the rejection(s) under 35 U.S.C. 112(a), set forth in this Office action.
The following is a statement of reasons for the indication of allowable subject matter: the prior arts of record taken alone or in combination neither anticipates nor renders obvious an image sensor comprising “a first etch stop film arranged on an upper surface and a sidewall of the transmission gate and on the first surface of the first semiconductor substrate” and “a pixel gate arranged on the first surface of the second semiconductor substrate or on the second surface of the second semiconductor substrate, the pixel gate being electrically connected with the floating diffusion region, and a gate spacer on a sidewall of the pixel gate; and a third stack, attached to the second stack and comprising a logic transistor configured to provide signals to the pixel gate” as recited in claim 1; an image sensor comprising “a first etch stop film arranged on an upper surface of a first portion of the transmission gate, on a sidewall of the first portion of the transmission gate, and on the first surface of the first semiconductor substrate” and “a pixel gate arranged on the first surface of the second semiconductor substrate or on the second surface of the second semiconductor substrate, the pixel gate being electrically connected with the floating diffusion region; and a third stack, attached to the second stack, the third stack comprising a logic transistor configured to provide signals to the pixel gate” as recited in claim 12; and an image sensor comprising “a transmission gate arranged on the first surface of the first semiconductor substrate and having a first portion and having a second portion that is arranged in a transmission trench extending to an inside of the first semiconductor substrate, a first etch stop film arranged on an upper surface and a sidewall of the first portion of the transmission gate and on the first surface of the first semiconductor substrate, and a passivation layer arranged between the first etch stop film and each of the upper surface and the sidewall of the first portion of transmission gate and between the first etch stop film and the first surface of the first semiconductor substrate” in combination with the limitation wherein “the pixel gate being electrically connected with the floating diffusion region, a gate spacer on a sidewall of the pixel gate, and a second etch stop film arranged on an upper surface of the pixel gate and on a sidewall of the gate spacer, and wherein the third stack includes a logic transistor configured to provide signals to the pixel gate” as recited in claim 18. Claims 2-11, 13-17 and 19-20 are also allowable for further limiting and depending upon allowable claims 1, 12 and 18.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Jang et al. US PGPub. 2023/0030489 teaches an image sensor comprising three stacks but the logic transistor in the third stack is not connected or configured to provide any signals to the pixel gate or the transmission gate.
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/NDUKA E OJEH/Primary Examiner, Art Unit 2892
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