DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Specification
The specification is objected to as failing to provide proper antecedent basis for the claimed subject matter. See 37 CFR 1.75(d)(1) and MPEP § 608.01(o). Correction of the following is required:
Claim 12 requires the second semiconductor chip to be an RFIC. However, paragraph [0029] of the specification states that the second semiconductor chip “may include one or more of various electronic devices (e.g., a power management integrated circuit (PMIC), a modem, a transceiver, a power amplifier module (PAM), a frequency filter, or a low noise amplifier (LNA)), which may be used to drive the first semiconductor chip 300.”
Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 8 and 15 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 8 requires “a wiring pattern” that is part of the connection member. It is not clear whether this is the same “a wiring pattern” that is also required in parent claim 1. For the purpose of compact prosecution, the examiner will treat these two wiring patterns to be separate entities.
Claim 15 recites the limitation "second semiconductor chip" in the limitation of “a space between the connection substrate and the first and second semiconductor chips.” There is insufficient antecedent basis for this limitation in the claim. For the purpose of compact prosecution, the examiner will disregard the second semiconductor chip.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1-4 and 7-8 are rejected under 35 U.S.C. 103 as being unpatentable over Lee ‘996 (US 2022/0051996 A1) in view of Sato (US 2020/0067170 A1) and Chuang (US 2020/0212537 A1).
Regarding claim 1, Lee ‘996 teaches a semiconductor package, comprising:
a first redistribution substrate (320);
a first semiconductor chip (110) on the first redistribution substrate;
a mold layer (210; ¶ [0045]: 210 made of epoxy molding compound ) on the first redistribution substrate and enclosing the first semiconductor chip;
a second redistribution substrate (410&420) on the mold layer;
a connection member (230) horizontally apart from the first semiconductor chip and connecting the first redistribution substrate to the second redistribution substrate (see ¶ [0042]); and
an antenna substrate (520) attached to the second redistribution substrate,
wherein the antenna substrate comprises
a core portion (510);
an antenna pattern (522) on a top surface (top surface of 510) of the core portion; and
a wiring pattern (524) on a bottom surface (bottom surface of 510) of the core portion.
Lee ‘996 teaches attaching the antenna substrate to the second redistribution layer (¶ [0108]). However, Lee ‘996 does not teach attaching the antenna substrate to the second redistribution substrate by an adhesive layer.
Sato, in the same field of invention, teaches a device wherein the antenna substrate (21) is attached to the redistribution substrate (20) by an adhesive layer (30; Fig. 3).
A person of ordinary skill in the art, prior to the effective date of the claimed invention, will find it obvious to combine the teachings of Sato into the device of Lee ‘996 to attach the antenna substrate to the second redistribution substrate using an adhesive layer. The ordinary artisan would have been motivated to modify Lee ‘996 in the manner set forth above for at least the purpose of using adhesives as one of the various methods of attaching antenna substrates to redistribution substrates ( Sato ¶ [0041] ) and for using the adhesive to improve the mechanical stability of the device.
However, Lee ‘996 in view of Sato does not teach: a second semiconductor chip horizontally apart from the first semiconductor chip, such that the mold layer encloses both the first and second semiconductor chip and the connection member is horizontally apart from the first and second semiconductor chips.
Chuang, in the same field of invention, teaches a device (92; Fig. 22A) comprising
a second semiconductor chip (57) horizontally apart from the first semiconductor chip (56), such that the mold layer (86; ¶ [0034]: 84 may be a molding compound) encloses both the first and second semiconductor chip and a connection member (any 78&34) is horizontally apart from the first and second semiconductor chips.
A person of ordinary skill in the art, prior to the effective date of the claimed invention, will find it obvious to combine the teachings of Chuang into the device of Lee ‘996 in view of Sato to add a second semiconductor chip that is horizontally apart from the first semiconductor chip, such that the mold layer encloses both the first and second semiconductor chips and such that the connection member is horizontally apart from both the first and second semiconductor chips. The ordinary artisan would have been motivated to modify Lee ‘996 in view of Sato in the manner set forth above for at least the purpose of adding various devices such as filters, amplifiers, PMICs, memories, etc. (Chuang ¶ [0046] ), as part of a circuit that is configured to receive and transmit RF signals (¶ [0021] ) in cell phones (¶ [0002] ), that shortens the distance between critical elements of the package for further improving the bandwidth of the device (¶ [0002]).
Regarding claim 2, the semiconductor package of claim 1, wherein the first semiconductor chip includes a radio-frequency integrated circuit (RFIC) (Chuang ¶ [0023]: 56 is an RFIC ), and
the second semiconductor chip includes a power management integrated circuit (PMIC) (¶ [0046]: 57 is a PMIC ).
Regarding claim 3, Lee ‘996 et al. teach the semiconductor package of claim 1, but do not teach: at least one passive device on a top surface of the first redistribution substrate and horizontally apart from the second semiconductor chip.
Chuang teaches the device further comprising: at least one passive device (122; Chuang Fig. 22A) on a top surface (top surface of 77) of the first redistribution substrate (77) and horizontally apart from the second semiconductor chip (57).
A person of ordinary skill in the art, prior to the effective date of the claimed invention, will find it obvious to combine the teachings of Chuang into the device of Lee ‘996 et al. to add one or more passive devices on a top surface of the first redistribution substrate and horizontally apart from the second semiconductor chip. The ordinary artisan would have been motivated to modify Lee ‘996 et al. in the manner set forth above for at least the purpose of improving the signal of transmitted and/or received by the device (Chuang ¶ [0046] ).
Regarding claim 4, the semiconductor package of claim 3, wherein the passive device includes at least one of a capacitor or an inductor (Chuang ¶ [0046]).
Regarding claim 7, the semiconductor package of claim 1, wherein the mold layer (210; Lee ‘996 Fig. 2B) fills a space (space between 320 and 420, see Figs.2E-2G) between the first and second redistribution substrates, and the connection member (230) comprises a metal post (¶ [0047]: copper) vertically penetrating the mold layer and connected to the first and second redistribution substrates (Fig. 2G shows 230 vertically penetrating mold 210 and connected to RDLs 320 and 420; see also ¶ [0042] ).
Regarding claim 8, the semiconductor package of claim 1, further comprising: a connection substrate (220; see Lee ‘996 Figs. 1A and 2A) between the first and second redistribution substrates, the connection substrate defining and being penetrated by an opening (center space in Fig. 2A), wherein the first and second semiconductor chips are in the opening (Fig. 2B shows first semiconductor chip 110 in the opening; in view of Chuang, this opening includes the second semiconductor chip), in the opening, the mold layer (210) fills spaces between the connection substrate and the first semiconductor chip and between the connection substrate and the second semiconductor chip, and the connection member comprises a wiring pattern (230) in the connection substrate (Fig. 1B shows 230 is inside 220).
Claim 5 is rejected under 35 U.S.C. 103 as being unpatentable over Lee ‘996 (US 2022/0051996 A1) in view of Sato (US 2020/0067170 A1) and Chuang (US 2020/0212537 A1) as applied to claim 1 above, and further in view of Wu (CN 112259954 A; see NPL for English translation).
Regarding claim 5, Lee ‘996 et al. teach the semiconductor package of claim 1, but does not teach: a connector on the second redistribution substrate and horizontally apart from the antenna substrate.
Wu, in the same field of invention, teaches a device comprising of a connector (210; Fig. 12) on the second redistribution substrate (203) and horizontally apart from the antenna substrate (204 & 206).
A person of ordinary skill in the art, prior to the effective date of the claimed invention, will find it obvious to combine the teachings of Wu into the device of Lee ‘996 et al. to add a connector on the second redistribution substrate such that the connector is horizontally apart from the antenna substrate. The ordinary artisan would have been motivated to modify Lee ‘996 et al. in the manner set forth above for at least the purpose of improving the connectivity of the device by connecting the second redistribution substrate to an external circuit board (220; see ¶ [0117] of English translation).
Claim 6 is rejected under 35 U.S.C. 103 as being unpatentable over Lee ‘996 (US 2022/0051996 A1) in view of Sato (US 2020/0067170 A1) and Chuang (US 2020/0212537 A1) as applied to claim 1 above, and further in view of Venkatesan (US 2023/0038028 A1).
Regarding claim 6, Lee ‘996 et al. teach the semiconductor package of claim 1, but do not teach: a heat-dissipation pad on a bottom surface of the first redistribution substrate, wherein the heat-dissipation pad and the first semiconductor chip are connected to each other by a heat-dissipation via pattern, the heat-dissipation via pattern vertically penetrating the first redistribution substrate.
Venkatesan, in the same field of invention, teaches a heat-dissipation pad (1328; Fig. 13A) on a bottom surface (bottom of 1320) of the first redistribution substrate (1320),
wherein the heat-dissipation pad and the first semiconductor chip are connected to each other by a heat-dissipation via pattern (1326; see ¶ [0115]: “metal traces 1326 that are used in the interconnect layer 1320, are used to transfer heat from heat generating devices 1360 to the thermally conductive layers 1328” ), the heat-dissipation via pattern vertically penetrating the first redistribution substrate (Fig. 13A shows 1326 vertically connecting the chip 1360 to the heat-dissipation pad 1328).
A person of ordinary skill in the art, prior to the effective date of the claimed invention, will find it obvious to combine the teachings of Venkatesan into the device of Lee ‘996 et al. to add a heat-dissipation pad on a bottom surface of the first redistribution substrate, wherein the heat-dissipation pad has heat-dissipation via pattern that vertically penetrates the first redistribution substrate in order to connect the first semiconductor chip to the heat-dissipation pad. The ordinary artisan would have been motivated to modify Lee ‘996 et al. in the manner set forth above for at least the purpose of improving the heat dissipation of the device (Venkatesan ¶ [0115] ).
Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over Lee ‘996 (US 2022/0051996 A1) in view of Sato (US 2020/0067170 A1) and Chuang (US 2020/0212537 A1) as applied to claim 1 above, and further in view of Lee ‘201 (US 2023/0216201 A1)..
Regarding claim 9, Lee ‘996 et al. teaches the semiconductor package of claim 1, but does not teach: a vertical connection conductor vertically penetrating the mold layer and connecting the first redistribution substrate to the second redistribution substrate, wherein the vertical connection conductor is shaped like a partition wall enclosing the first and second semiconductor chips.
Lee ‘201, in the same field of invention, teaches a device comprising of a vertical connection conductor (553; see Fig. 17) vertically penetrating the mold layer (543) and connecting the first redistribution substrate (520a) to the second redistribution substrate (560), wherein the vertical connection conductor is shaped like a partition wall (Figs. 13 & 14: outline of 543 is a rectangular box) enclosing the first and second semiconductor chips (Figs. 13 &14 show 543 enclosing chip 530; Lee ‘996 in view of Chuang and Lee ‘201, teaches 543 to enclose both first and second semiconductor chips).
A person of ordinary skill in the art, prior to the effective date of the claimed invention, will find it obvious to combine the teachings of Lee ‘201 into the device of Lee ‘996 et al. to add a vertical connection conductor that penetrates the mold layer to connect the first redistribution substrate to the second redistribution substrate, wherein the vertical connection conductor is a partition wall that encloses the first and second semiconductor chips. The ordinary artisan would have been motivated to modify Lee ‘996 et al. in the manner set forth above for at least the purpose of adding an EMI shield ( Lee ‘201 ¶ [0155] ), to filter in/out specific frequency bands (¶ [0156] ), and/or to electrically ground the device (¶ [0157]) for the further purpose of improving the performance of the device (¶ [0202]) .
Claim 10 and 14-15 are rejected under 35 U.S.C. 103 as being unpatentable over Lee ‘996 (US 2022/0051996 A1) in view of Venkatesan (US 2023/0038028 A1).
Regarding claim 10, Lee ‘996 teaches a semiconductor package, comprising:
a first redistribution substrate (320);
a first semiconductor chip (110) on a top surface (top surface of 320) of the first redistribution substrate;
a second redistribution substrate (420) on the first semiconductor chip;
a connection member (230) at a side of the first semiconductor chip and connecting the first redistribution substrate to the second redistribution substrate; and
an antenna substrate (520) on the second redistribution substrate.
However, Lee ‘996 does not teach the device comprising: a heat-dissipation pad on a bottom surface of the first redistribution substrate; and a heat-dissipation via pattern vertically penetrating the first redistribution substrate and connecting the heat-dissipation pad to the first semiconductor chip.
Venkatesan, in the same field of invention, teaches a device comprising:
a heat-dissipation pad (1328; Fig. 13A) on a bottom surface (bottom of 1320) of the first redistribution substrate (1320 is analogous to the first redistribution substrate since a chip 1360 is on it); and a heat-dissipation via pattern (1326) vertically penetrating the first redistribution substrate and connecting the heat-dissipation pad to the first semiconductor chip (see ¶ [0115]: “metal traces 1326 that are used in the interconnect layer 1320, are used to transfer heat from heat generating devices 1360 to the thermally conductive layers 1328”).
A person of ordinary skill in the art, prior to the effective date of the claimed invention, will find it obvious to combine the teachings of Venkatesan into the device of Lee ‘996 to add a heat-dissipation pad on a bottom surface of the first redistribution substrate, wherein the heat-dissipation pad has heat-dissipation via pattern that vertically penetrates the first redistribution substrate in order to connect the first semiconductor chip to the heat-dissipation pad. The ordinary artisan would have been motivated to modify Lee ‘996 et al. in the manner set forth above for at least the purpose of improving the heat dissipation of the device (Venkatesan ¶ [0115] ).
Regarding claim 14, the semiconductor package of claim 10, further comprising:
a mold layer (210; Lee ‘996 ¶ [0045]: 210 made of epoxy molding compound) filling a space (vertical space between 320 and 420 as shown in Fig. 1) between the first and second redistribution substrates,
wherein the connection member comprises a metal post (¶ [0047]: 230 is made of copper) vertically penetrating the mold layer and connecting the first redistribution substrate to the second redistribution substrate (Fig. 2G shows 230 vertically penetrating mold 210 and connected to RDLs 320 and 420; see also ¶ [0042]).
Regarding claim 15, the semiconductor package of claim 10, further comprising:
a connection substrate (220; see Lee ‘996 Fig. 1A and 2A) between the first and second redistribution substrates, the connection substrate defining and being penetrated by an opening (center space in Fig. 2A), the first and second semiconductor chips being in the opening (Fig. 2B shows first semiconductor chip 110 in the opening; also see 112b rejection above); and
in the opening, an insulating layer (210) filling a space between the connection substrate and the first and second semiconductor chips,
wherein the connection member comprises a wiring pattern (pattern of the placements of 230 as shown in Figs. 1A & 1B) in the connection substrate (Fig. 1B shows connection member 230 inside connection substrate 220; see ¶ [0042] ).
Claims 11-12 are rejected under 35 U.S.C. 103 as being unpatentable over Lee ‘996 (US 2022/0051996 A1) in view of Venkatesan (US 2023/0038028 A1), as applied to claim 10 above, and further in view of Chuang (US 2020/0212537 A1).
Regarding claim 11, Lee ‘996 et al. teach the semiconductor package of claim 10, but does not teach the device further comprising: a second semiconductor chip horizontally apart from the first semiconductor chip.
Chuang, in the same field of invention, teaches a device comprising: a second semiconductor chip (57) horizontally apart from the first semiconductor chip (56).
A person of ordinary skill in the art, prior to the effective date of the claimed invention, will find it obvious to combine the teachings of Chuang into the device of Lee ‘996 et al. to add a second semiconductor chip that is horizontally apart from the first semiconductor chip. The ordinary artisan would have been motivated to modify Lee ‘996 et al. in the manner set forth above for at least the purpose of adding various devices such as filters, amplifiers, PMICs, memories, etc. (¶ [0046] ), as part of a circuit that is configured to receive and transmit RF signals (¶ [0021] ) in cell phones (¶ [0002] ), that shortens the distance between critical elements of the package for further improving the bandwidth of the device (¶ [0002]).
Regarding claim 12, the semiconductor package of claim 11, wherein the first semiconductor chip comprises a radio-frequency integrated circuit (RFIC) (Chuang ¶ [0023]: 56 is an RFIC ), and
the second semiconductor chip comprises a radio-frequency integrated circuit (RFIC) (¶ [0046]: 57 can be an RFIC die).
Claim 13 is rejected under 35 U.S.C. 103 as being unpatentable over Lee ‘996 (US 2022/0051996 A1) in view of Venkatesan (US 2023/0038028 A1), as applied to claim 10 above, and further in view of Chuang (US 2020/0212537 A1) and Wu (CN 112259954 A; see NPL for English translation).
Regarding claim 13, Lee ‘996 et al. teach the semiconductor package of claim 10, but do not teach the device further comprising: one or more passive devices on the top surface of the first redistribution substrate and horizontally apart from the first semiconductor chip.
Chuang, in the same field of invention, teaches a device comprising
one or more passive devices (122; Chuang Fig. 22A) on the top surface (top surface of 77) of the first redistribution substrate (77) and horizontally apart from the first semiconductor chip (56).
A person of ordinary skill in the art, prior to the effective date of the claimed invention, will find it obvious to combine the teachings of Chuang into the device of Lee ‘996 et al. to add one or more passive devices, horizontally apart from the first semiconductor chip, and on the top surface of the first redistribution layer. The ordinary artisan would have been motivated to modify Lee ‘996 et al. in the manner set forth above for at least the purpose of improving the signal of transmitted and/or received by the device (Chuang ¶ [0046] ).
However, Chuang et al. does not teach the device further comprising a connector on the second redistribution substrate and horizontally apart from the antenna substrate.
Wu, in the same field of invention, teaches a device comprising a connector (210; Fig. 12) on the second redistribution substrate (203) and horizontally apart from the antenna substrate (204 & 206).
A person of ordinary skill in the art, prior to the effective date of the claimed invention, will find it obvious to combine the teachings of Wu into the device of Lee ‘996 et al. to add a connector on the second redistribution substrate such that the connector is horizontally apart from the antenna substrate. The ordinary artisan would have been motivated to modify Lee ‘996 et al. in the manner set forth above for at least the purpose of connecting the second redistribution substrate to an external circuit board (220; see ¶ [0117] of English translation) to further improve the connectivity of the device.
Claim 16 is rejected under 35 U.S.C. 103 as being unpatentable over Lee ‘996 (US 2022/0051996 A1) in view of Venkatesan (US 2023/0038028 A1), as applied to claim 10 above, and further in view of Sato (US 2020/0067170 A1) and Takano (US 2023/0063204 A1).
Regarding claim 16, Lee ‘996 et al. teach the semiconductor package of claim 10, and further teach attaching the antenna substrate to the second redistribution layer (Lee ‘996 ¶ [0108] ). However, Lee ‘996 et al. do not teach: wherein the antenna substrate is connected to the second redistribution substrate by an adhesive layer, or the antenna substrate is connected to the second redistribution substrate by connection terminals including at least one of solder balls or solder bumps.
Sato, in the same field of invention, teaches a device wherein the antenna substrate (21) is connected to the second redistribution substrate (20) by an adhesive layer (30), or the antenna substrate is connected to the second redistribution substrate by connection terminals including at least one of solder balls or solder bumps.
A person of ordinary skill in the art, prior to the effective date of the claimed invention, will find it obvious to combine the teachings of Sato into the device of Lee ‘996 et al. to connect the antenna substrate to the second redistribution structure using an adhesive. The ordinary artisan would have been motivated to modify Lee ‘996 et al. in the manner set forth above for at least the purpose of using adhesives as one of the various methods of attaching antenna substrates to redistribution substrates ( Sato ¶ [0041] ) for the further purpose using the adhesive to improve the mechanical stability to the device.
However, Lee ‘996 et al. in view of Sato does not teach the adhesive layer to include a die attach film (DAF).
Takano, in the same field of invention, teaches an adhesive layer to include a die attach film (DAF) (¶ [0095] ).
A person of ordinary skill in the art, prior to the effective date of the claimed invention, will find it obvious to combine the teachings of Lee ‘996 et al. in view of Sato into the device of Takano to use a die attach film (DAF) as an adhesive layer. The ordinary artisan would have been motivated to modify Lee ‘996 et al. in view of Sato in the manner set forth above for at least the purpose of substituting the unnamed material of the adhesive in Sato with a die attach film (DAF) as it is known in the art used for the same purpose as attaching elements in semiconductor packages (Takano ¶ [0095] ).
Claims 17 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Lee ‘996 (US 2022/0051996 A1) in view of Chuang (US 2020/0212537 A1), Wu (CN 112259954 A; see NPL for English translation), and Lee ‘201 (US 2023/0216201 A1).
Regarding claim 17, Lee ‘996 teaches a semiconductor package, comprising:
a first redistribution substrate (320);
a first semiconductor chip (110) on a top surface (top surface of 110) of the first redistribution substrate;
a mold layer (210; ¶ [0045]: 210 made of epoxy molding compound ) on the top surface of the first redistribution substrate and enclosing the first semiconductor chip;
a second redistribution substrate (410 & 420) on the mold layer; and
an antenna substrate (520) on the second redistribution substrate.
However, Lee ‘996 does not teach: a second semiconductor chip on the first redistribution substrate and horizontally apart from the first semiconductor chip, such that the mold layer encloses both the first and second semiconductor chips.
Chuang, in the same field of invention, teaches a device (92; Fig. 22A) comprising a second semiconductor chip (57) on the first redistribution substrate (77) and horizontally apart from the first semiconductor chip (56), such that the mold layer (86) encloses both the first and second semiconductor chips.
A person of ordinary skill in the art, prior to the effective date of the claimed invention, will find it obvious to combine the teachings of Lee ‘996 et al. into the device of Lee ‘996 to add a second semiconductor chip on the first redistribution substrate, with the second chip horizontally spaced apart from the first semiconductor chip, such that the mold layer encloses both the first and second semiconductor chips. The ordinary artisan would have been motivated to modify Lee ‘996 in view of Sato in the manner set forth above for at least the purpose of adding various devices such as filters, amplifiers, PMICs, memories, etc. (Chuang ¶ [0046] ), as part of a circuit that is configured to receive and transmit RF signals (¶ [0021] ) in cell phones (¶ [0002] ), that shortens the distance between critical elements of the package for further improving the bandwidth of the device (¶ [0002]).
However, Lee ‘996 et al. does not teach the device further comprising a connector on the second redistribution substrate and horizontally apart from the antenna substrate.
Wu, in the same field of invention, teaches a device comprising of a connector (210; Fig. 12) on the second redistribution substrate (203) and horizontally apart from the antenna substrate (204 & 206).
A person of ordinary skill in the art, prior to the effective date of the claimed invention, will find it obvious to combine the teachings of Wu into the device of Lee ‘996 et al. to add a connector on the second redistribution substrate such that the connector is horizontally apart from the antenna substrate. The ordinary artisan would have been motivated to modify Lee ‘996 et al. in the manner set forth above for at least the purpose of connecting the second redistribution substrate to an external circuit board (220; see ¶ [0117] of English translation) to improve the connectivity of the device.
However, Lee ‘996 et al. do not teach the device further comprising of a vertical connection conductor (230) vertically penetrating the mold layer and connecting the first redistribution substrate to the second redistribution substrate, wherein the vertical connection conductor is shaped like a partition wall enclosing the first and second semiconductor chips.
Lee ‘201, in the same field of invention, teaches a device comprising of a vertical connection conductor (553; see Fig. 17) vertically penetrating the mold layer (543) and connecting the first redistribution substrate (520a) to the second redistribution substrate (560),
wherein the vertical connection conductor is shaped like a partition wall (Figs. 13&14: outline of 543 is a rectangular box) enclosing the first and second semiconductor chips (Figs. 13 &14 show 543 enclosing chip 530; Lee ‘996 in view of Chuang and Lee ‘201, teaches 543 to enclose both first and second semiconductor chips).
A person of ordinary skill in the art, prior to the effective date of the claimed invention, will find it obvious to combine the teachings of Lee ‘201 into the device of Lee ‘996 et al. to add a vertical connection conductor that is shaped like a partition wall that encloses the first and second semiconductor chips, with the said vertical connection conductor connecting the first redistribution substrate to the second redistribution substrate by penetrating the mold layer. The ordinary artisan would have been motivated to modify Lee ‘996 et al. in the manner set forth above for at least the purpose of adding an EMI shield ( Lee ‘201 ¶ [0155] ), to filter in/out specific frequency bands (¶ [0156] ), and/or to electrically ground the device (¶ [0157]) for the further purpose of improving the performance of the device (¶ [0202]).
Regarding claim 20, Lee ‘996 et al. teach the semiconductor package of claim 17, but do not teach: a plurality of passive devices on the top surface of the first redistribution substrate and horizontally apart from the first and second semiconductor chips.
Chuang teaches the device further comprising: a plurality of passive devices (122; see ¶ [0032]) on the top surface (top surface of 77) of the first redistribution substrate (77) and horizontally apart from the first (56) and second semiconductor chips (57).
A person of ordinary skill in the art, prior to the effective date of the claimed invention, will find it obvious to combine the teachings of Chuang into the device of Lee ‘996 et al. to add a plurality of passive devices on a top surface of the first redistribution substrate and horizontally apart from the first and second semiconductor chip. The ordinary artisan would have been motivated to modify Lee ‘996 et al. in the manner set forth above for at least the purpose of improving the signal of transmitted and/or received by the device (Chuang ¶ [0046] ).
Claims 18 is rejected under 35 U.S.C. 103 as being unpatentable over Lee ‘996 (US 2022/0051996 A1) in view of Chuang (US 2020/0212537 A1), Wu (CN 112259954 A; see NPL for English translation), and Lee ‘201 (US 2023/0216201 A1) as applied to claim 17 above, and further in view of Venkatesan (US 2023/0038028 A1).
Regarding claim 18, Lee ‘996 et al. teach the semiconductor package of claim 17, but do not teach the device further comprising a heat-dissipation pad disposed on a bottom surface of the first redistribution substrate,
wherein the heat-dissipation pad and the first semiconductor chip are connected to each other by a heat-dissipation via pattern, the heat-dissipation via pattern vertically penetrating the first redistribution substrate.
Venkatesan, in the same field of invention, teaches a device comprising
a heat-dissipation pad (1328; Fig. 13A) disposed on a bottom surface (bottom of 1320) of the first redistribution substrate (1320),
wherein the heat-dissipation pad and the first semiconductor chip are connected to each other by a heat-dissipation via pattern (1326; see ¶ [0115]: “metal traces 1326 that are used in the interconnect layer 1320, are used to transfer heat from heat generating devices 1360 to the thermally conductive layers 1328” ), the heat-dissipation via pattern vertically penetrating the first redistribution substrate (Fig. 13A shows 1326 vertically connecting the chip 1360 to the heat-dissipation pad 1328).
A person of ordinary skill in the art, prior to the effective date of the claimed invention, will find it obvious to combine the teachings of Venkatesan into the device of Lee ‘996 et al. to add a heat-dissipation pad on a bottom surface of the first redistribution substrate, wherein the heat-dissipation pad has heat-dissipation via pattern that vertically penetrates the first redistribution substrate in order to connect the first semiconductor chip to the heat-dissipation pad. The ordinary artisan would have been motivated to modify Lee ‘996 et al. in the manner set forth above for at least the purpose of improving the heat dissipation of the device (Venkatesan ¶ [0115] ).
Claim 19 is rejected under 35 U.S.C. 103 as being unpatentable over Lee ‘996 (US 2022/0051996 A1) in view of Chuang (US 2020/0212537 A1), Wu (CN 112259954 A; see NPL for English translation), and Lee ‘201 (US 2023/0216201 A1) as applied to claim 17 above, and further in view of Sato (US 2020/0067170 A1) and Takano (US 2023/0063204 A1).
Regarding claim 19, Lee ‘996 et al. teach the semiconductor package of claim 17, and further teach attaching the antenna substrate to the second redistribution layer (Lee ‘996 ¶ [0108] ). However, Lee ‘996 et al. do not teach: wherein the antenna substrate is connected to the second redistribution substrate by an adhesive layer, or the antenna substrate is connected to second redistribution substrate by connection terminals including at least one of solder balls or solder bumps.
Sato, in the same field of invention, teaches a device wherein the antenna substrate (21) is connected to the second redistribution substrate (20) by an adhesive layer (30), or the antenna substrate is connected to the second redistribution substrate by connection terminals including at least one of solder balls or solder bumps.
A person of ordinary skill in the art, prior to the effective date of the claimed invention, will find it obvious to combine the teachings of Sato into the device of Lee ‘996 et al. to connect the antenna substrate to the second redistribution structure using an adhesive. The ordinary artisan would have been motivated to modify Lee ‘996 et al. in the manner set forth above for at least the purpose of using adhesives as one of the various methods of attaching antenna substrates to redistribution substrates ( Sato ¶ [0041] ) for the further purpose of using the said adhesive to improve the mechanical stability of the device.
However, Lee ‘996 et al. in view of Sato does not teach the adhesive layer to include a die attach film (DAF).
Takano, in the same field of invention, teaches an adhesive layer to include a die attach film (DAF) (¶ [0095] ).
A person of ordinary skill in the art, prior to the effective date of the claimed invention, will find it obvious to combine the teachings of Lee ‘996 et al. in view of Sato into the device of Takano to use a die attach film (DAF) as an adhesive layer. The ordinary artisan would have been motivated to modify Lee ‘996 et al. in view of Sato in the manner set forth above for at least the purpose of substituting the unnamed material of the adhesive in Sato with a die attach film (DAF) as it is known in the art used for the same purpose as attaching elements in semiconductor packages (Takano ¶ [0095] ).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DOUGLAS YAP whose telephone number is (703)756-1946. The examiner can normally be reached Monday - Friday 8:00 AM - 5:00 PM ET.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Zandra Smith can be reached at (571) 272-2429. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/DOUGLAS YAP/Assistant Examiner, Art Unit 2899
/JOHN M PARKER/Primary Examiner, Art Unit 2899
Prosecution Insights