The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-8, 11-24 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Chen et al. (U.S. Patent Application Publication 2020/0149155, hereinafter referred to as Chen).
As to claim 1, Chen teaches 1. A method comprising: vaporizing at least a portion of a ruthenium precursor to produce a vaporized ruthenium precursor; contacting a first surface portion and a second surface portion of a substrate with the vaporized ruthenium precursor and at least one reducing gas; and depositing ruthenium on the first surface portion of the substrate with a selectivity of at least 25 Å relative to the second surface portion of the substrate. [[¶0006~0007]
As to claim 2, Chen teaches 2. The method of claim 1, wherein the first surface portion of the substrate comprises at least one of TaN, WCN, WN, TiN, Cu, W, Co, TaN, TiN, Mo, MoN, MoCN, DHF SiGe, SiGe or any combination thereof. [¶0009]
As to claim 3, Chen teaches 3. The method of claim 1, wherein the second surface portion of the substrate comprises at least one of SiO2, SiN, silicon, DHF silicon, native silicon oxide, SiCOH, SiOCNH, low k dielectric, porous low k dielectrics or any combination thereof. [¶0009]
As to claim 4, Chen teaches 4. The method of claim 1, wherein the first surface portion comprises: at least one of TaN, WCN, WN, TiN, or any combination thereof; and wherein the second surface portion comprises: at least one of SiO2, SiN, SiOCNH, or any combination thereof. [[¶0009]
As to claim 5, Chen teaches 5. The method of claim 4, wherein the first surface portion is contacting the gate of a transistor and second surface portion isolates the gate electrically from other parts of the structure. [¶0039~0042]
As to claim 6, Chen teaches 6. The method of claim 4, wherein the first surface portion and the second surface portion are part of a gate-all-around (GAA) transistor. [¶0039~0042]
As to claim 7, Chen teaches 7. The method of claim 1, wherein the first surface portion comprises: at least one of Cu, W, Co, TaN, WCN, TiN, Mo, MoN, MoCN or any combination thereof; and wherein the second surface portion of the via comprises SiN, SiO2, or low K dielectric. [¶0009]
As to claim 8, Chen teaches 8. The method of claim 7, wherein the first surface portion is at a bottom of a via structure and the second surface portion electrically isolates the via from other parts of the structure. [¶0039~0042]
As to claim 11, Chen teaches 11. The method of claim 1, wherein the depositing is performed at a temperature of at least 300 °C and a pressure of at least 0.5 Torr. [¶0035; 0055]
As to claim 12, Chen teaches 12. The method of claim 1, wherein the depositing is performed at a temperature of 300 °C to 450 °C and a pressure of 0.5 Torr to 5 Torr. [¶0035; 0055]
As to claim 13, Chen teaches 13. The method of claim 1, wherein the at least one reducing gas comprises NH3. [¶0036]
As to claim 14, Chen teaches 14. The method of claim 1, wherein the at least one reducing gas comprises H2. [¶0036]
As to claim 15, Chen teaches 15. The method of claim 1, wherein the depositing is performed in a chamber that is substantially free of oxygen. [¶0035; 0055]
As to claim 16, Chen teaches 16. The method of claim 1, wherein the ruthenium is deposited on the first surface portion of the substrate with a selectivity of at least 40 Å relative to the second surface portion of the substrate. [¶0009]
As to claim 17, Chen teaches 17. The method of claim 1, wherein the ruthenium is deposited on the first surface portion of the substrate with a selectivity of 40 Å to 80 Å relative to the second surface portion of the substrate. [¶0009]
As to claim 18, Chen teaches 18. A device comprising: a substrate having a first surface portion and a second surface portion adjacent to the first surface portion; and a ruthenium layer located on the first surface portion of the substrate, wherein the ruthenium layer has a thickness of at least 25 Å on the first surface portion of the substrate; wherein the second surface portion of the substrate does not comprise ruthenium. [[¶0006~0007]
As to claim 19, Chen teaches 19. The device of claim 18, wherein the first surface portion of the substrate comprises at least one of TaN, WCN, WN, TiN, Cu, W, Co, TaN, TiN, Mo, MoN, MoC, MoCN, DHF SiGe, SiGe or any combination thereof. [¶0009]
As to claim 20, Chen teaches 20. The device of claim 18, wherein the second surface portion of the substrate comprises at least one of SiO2, SiN, silicon, DHF silicon, native silicon oxide, SiCOH, SiOCNH, low k dielectric, porous low k dielectrics or any combination thereof. [¶0009]
As to claim 21, Chen teaches 21. The device of claim 18, wherein the first surface portion comprises: at least one of TaN, WCN, WN, MoN, TiN, or any combination thereof; and wherein the second surface portion comprises: at least one of SiO2, SiN, or any combination thereof. [¶0009]
As to claim 22, Chen teaches 22. The device of claim 21, wherein the first surface portion and the second surface portion are part of a gate-all-around (GAA) transistor. [¶0039~0042]
As to claim 23, Chen teaches 23. The device of claim 18, wherein the first surface portion comprises: at least one of Cu, W, Co, TaN, WCN, TiN, Mo, MoN, MoC, MoCN or any combination thereof; wherein the second surface portion comprises SiO2. [¶0009]
As to claim 24, Chen teaches 24. The device of claim 23, wherein the first surface portion is at a bottom of a via structure and the second surface portion electrically isolates the via from other parts of the structure. [¶0039~0042]
Claim Rejections - 35 USC § 103
1. The following is a quotation of 35 U.S.C. 103(a) which forms the basis for all obviousness rejections set forth in this Office action:
(a) A patent may not be obtained though the invention is not identically disclosed or described as set forth in section 102 of this title, if the differences between the subject matter sought to be patented and the prior art are such that the subject matter as a whole would have been obvious at the time the invention was made to a person having ordinary skill in the art to which said subject matter pertains. Patentability shall not be negatived by the manner in which the invention was made.
2. Claim 9-10, 25-26 rejected under 35 U.S.C. 103(a) as being unpatentable over Chen in view of ABELSON et al. (U.S. Patent Application Publication 2016/0148839, hereinafter referred to as ABELSON).
As to claim 9, Chen teaches 9. The method of claim 1, the second surface portion comprises at least one of SiO2, SiN, DHF polysilicon/silicon, silicon, native silicon oxide, SiOCNH or any combination thereof.
Chen may not teach wherein the first surface portion comprises DHF SiGe; or SiGe.
ABELSON teaches this limitation [¶0066 for example]
Therefore, it would have been obvious to one of ordinary skill in the art at the time the invention was made to combine the teachings of Chen and ABELSON to “use the first surface portion that comprises DHF SiGe; or SiGe " in Chen according to ABELSON, for the further advantage of “utilizing known semiconductor materials”. […Specific semiconductor materials useful for some embodiments include, but are not limited to, Si, Ge, Se, diamond, fullerenes, SiC, SiGe, SiO, SiO.sub.2…¶0066]
Generally, differences material properties will not support the patentability of subject matter encompassed by the prior art unless there is evidence indicating such properties are critical. "[W]here the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation." In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955).
As to claim 10, Chen and ABELSON teaches 10. The method of claim 9, wherein the first surface portion and the second surface portion are part of a gate-all-around (GAA) transistor. [Chen ¶0039~0042]
As to claim 25, Chen and ABELSON teaches 25. The device of claim 18, wherein the first surface portion comprises DHF SiGe, SiGe, or any combination thereof; and wherein the second surface portion comprises at least one of SiO2, SiN, DHF polysilicon/silicon, silicon, native silicon oxide, or any combination thereof. [see rejection claim 9 above]
As to claim 26, Chen and ABELSON teaches 26. The device of claim 25, wherein the first surface portion and the second surface portion are part of a gate-all-around (GAA) transistor. [Chen ¶0039~0042]
Conclusion
Claims 1-26 are rejected as explained above.
The prior art made of record in the PTO-892 form and not relied upon is considered pertinent to applicant's disclosure.
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/JAEHWAN OH/
Primary Examiner, Art Unit 2899
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