DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1, 9, and 17 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lee (US Pat Pub 2022/0310163) in view of Huynh et al. (US Pat Pub 2024/0420779).
Regarding claims 1, 9 and 17, Lee discloses a computing system (for example figs. 1 – 16 and all related texts), comprising:
a processing unit (for example 3100 of fig. 16);
a plurality of high bandwidth flash packages (referred to as the plurality of semiconductor memory chips 2100, fig. 16. See also para 0125), each of the high bandwidth flash packages including a memory block (for example memory block BLK 1 – BLKz of memory chip 110, fig. 1 or 2) that includes an array of memory cells that are arranged in a plurality of word lines (for example fig. 3, 4 or 5); and
control circuitry (for example the memory controller 2200, fig. 16) that is configured to program the memory cells of a selected word line in at least one program loop that includes a programming pulse (para 0035 discloses program operation and programming pulse is considered inherent in programming operation) and a verify operation (referred to as program verify operation, para 0029, 0033), during the verify operation, the control circuitry being configured to:
apply a read pass voltage to a plurality of unselected word lines of the plurality of word lines (para 0029, pass voltage Vpass. See also para 0036, 0077 – 0079 and 0089, etc…).
Zhang et al. disclose the system as shown above, except wherein the read pass voltage is negative to make the memory cells of the unselected word lines conductive to holes.
The feature is however taught by Huynh et al. (US Pat Pub 2024/0420779) (see abstract and para 0005, 0013, 0021. Negative voltage is applied to unselected word lines in the memory block to make a plurality of memory cells in the memory block conductive to holes).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the invention, to combine the features taught by the prior arts, so that the memory cells in the memory block are conductive to holes).
Claim(s) 1, 9, and 17 is/are rejected under 35 U.S.C. 103 as being unpatentable over Zhang et al. (US Pat Pub 2024/0112743) in view of Choi et al. (US Pat Pub 2022/0130474).
Regarding claims 1, 9 and 17, Zhang et al. discloses a computing system (for example figs. 1 – 24 and all related texts), comprising:
a processing unit (for example processor 122c of fig. 1);
a plurality of high bandwidth flash packages (referred to as the plurality of non-volatile memory 108, fig. 2), each of the high bandwidth flash packages including a memory block (for example memory block Block 0 – Block M-1, fig. 4A) that includes an array of memory cells that are arranged in a plurality of word lines (for example fig. 4F); and
control circuitry (for example the memory controller 110, fig. 1) that is configured to program the memory cells of a selected word line in at least one program loop that includes a programming pulse and a verify operation (referred to in abstract as programming pulses followed by verification pulses of program verify voltages), during the verify operation (see also para 0008 and 0009), the control circuitry being configured to;
apply a read pass voltage to a plurality of unselected word lines of the plurality of word lines (para 0115, “during read/verify process, unselected memory cells are provided with read pass voltages to their control gates).
Zhang et al. disclose the system as shown above, except wherein the read pass voltage is negative to make the memory cells of the unselected word lines conductive to holes.
The feature is however taught by Choi et al. (see para 0009, 0010, 0109, 0120, “negative voltage applied to unselected word lines as VPPASS”. See also fig. 2, between T5 and T6, VNEG1 is applied to unselected word lines WL_UNS).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the invention, to combine the features taught by the prior arts, so that the memory cells in the memory block are conductive to holes).
Allowable Subject Matter
Claims 2 – 8, 10 – 16 and 18 – 20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
The prior arts of record fail to teach or reasonably suggest the system and method as set forth above, further comprising, in combination, the features and limitations additionally claimed at least in claims 2, 10, and 18.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. See additional cited references for related disclosures to the claimed invention.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to LY D PHAM whose telephone number is (571)272-1793. The examiner can normally be reached M-F: 8am-5pm.
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LY D. PHAM
Examiner
Art Unit 2827
/LY D PHAM/Primary Examiner, Art Unit 2827 November 26, 2025