DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 09/05/2024 is being considered by the examiner.
Claim Objections
Claim 18 is objected to because of the following informality: “transtor” misspelled and should instead read as “transistor”. Appropriate correction is required.
Claims 4 and 15 are objected to because of the following informality: “second layer” should read as “second-layer” for consistency purposes. Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 13 and 14 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 13 recites the limitation "a third node" in line 3. Such limitation is an identical feature to “the third node” as recited already in line 13 of independent claim 10. There is insufficient antecedent basis for this limitation in the claim.
Claim 14 is similarly rejected as being dependent on claim 13.
Allowable Subject Matter
Claim 1 allowed.
The following is a statement of reasons for the indication of allowable subject matter:
Tseng et al. (US 10242622 B2) teaches a display panel (FIG. 9, organic light-emitting display device), comprising a plurality of light-emitting devices ((55), plurality of pixel units, each pixel including a light-emitting device L) arranged in an array ((60)) and a pixel driving circuit (pixel circuit comprising transistors M0-M7 and capacitor Cst) configured to drive the light-emitting devices to emit light ((3)), wherein the pixel driving circuit comprises:
a first initialization transistor (sixth switch transistor M6) configured to input an initialization signal (signal VINIT) to a first node (gate G of drive transistor M0) under control of a first scan signal (second scan signal terminal S2);
a switching transistor (fourth switch transistor M4) configured to input a data signal (signal on the data signal terminal DATA) to a second node (first node N1) under control of a second scan signal (first scan signal terminal S1);
a driving transistor (drive transistor M0) configured to drive the light-emitting devices (light-emitting device L) to emit light ((16)) and the second node (first node N1);
a compensation transistor (fifth switch transistor M5) connected to the driving transistor (drive transistor M0) through the first node (gate G) and a third node (junction connecting M0, M5, and M7), and configured to compensate a threshold voltage (V.sub.th) of the driving transistor under control of a third scan signal (FIG. 2B, signal on reset control signal terminal CS);
a second initialization transistor (eighth switch transistor M8) configured to input the initialization signal (signal on the initialization signal terminal VINIT) to an anode (first terminal of light-emitting device L, connected to source/drain of M7) of the light-emitting devices under control of the third scan signal (FIG. 2B, signal on reset control signal terminal CS);
a first light-emitting control transistor (third switch transistor M3) connected to the driving transistor (drive transistor M0) through the second node (first node N1), and configured to conduct a current ((16)) from a power supply high-potential signal line (first power supply terminal PVDD) to the driving transistor under control of a light-emitting control signal (first light-emitting control signal terminal EM1);
a second light-emitting control transistor (seventh switch transistor M7) connected to the driving transistor (drive transistor M0) through the third node (junction connecting M0, M5, and M7), and configured to conduct a current ((16)) from the driving transistor to the anode (first terminal of light-emitting device L, connected to source/drain of M7) of the light-emitting devices.
However, Tseng et al. does not teach the second light-emitting control transistor under control of the light-emitting control signal.
Kim et al. (CN 108987438 A) is also silent to teaching the second light-emitting control transistor under control of the light-emitting control signal.
Kim et al. does however teach the display panel comprises a substrate (substrate 110), and a first semiconductor layer (polycrystalline semiconductor component 130A), a first metal layer (first grid metal wire (151, 154, 156 and 155a)), a second metal layer (second grid metal lines (172b, 152, 153 and 155)), a second semiconductor layer (oxide semiconductor element 130B), a third metal layer (first data metal line (171, 173, 174, 175, 176, and 178)), a first source-drain layer (driving source/drain electrodes 136a/137a), and a second source-drain layer (compensation source/drain electrodes 136c/137c) stacked on a surface of the substrate (FIG. 4);
the first metal layer (first grid metal wire (151, 154, 156 and 155a)) is patterned ([0075]) to form a plurality of first-layer scan signal lines (first scan lines 151), the second metal layer (second grid metal lines (172b, 152, 153 and 155)) is patterned to form a plurality of second-layer scan signal lines (second scan lines 152) and the third metal layer (first data metal line (171, 173, 174, 175, 176, and 178)) is patterned to form a plurality of third-layer scan signal lines (data line 171);
the first-layer scan signal lines (first scan lines 151) comprise a first scan signal line (first scan lines 151) and a second scan signal line (light emitting control line 154), the first scan signal line having a first portion (switching gate electrode 155b) forming a gate of the switching transistor (switch transistor T2).
However, Kim et al. does not teach the first-layer scan signal lines, the second-layer scan signal lines and the third-layer scan signal lines are extended in a first direction and arranged parallel to each other in a second direction perpendicular to the first direction; the first direction and the second direction are parallel to the surface of the substrate;
Kim et al. is further silent to an additional widened portion protruding away from the second scan signal line in the second direction.
Tseng et al., similarly, is also silent to teach the first-layer scan signal lines, the second-layer scan signal lines and the third-layer scan signal lines are extended in a first direction and arranged parallel to each other in a second direction perpendicular to the first direction; the first direction and the second direction are parallel to the surface of the substrate; and
an additional widened portion protruding away from the second scan signal line in the second direction.
Claims 2-9 allowed.
The following is a statement of reasons for the indication of allowable subject matter:
Claims 2-9 are dependent on claim 1, which is allowed.
Claim 10 allowed.
The following is a statement of reasons for the indication of allowable subject matter:
Tseng et al. (US 10242622 B2) teaches a first initialization transistor (sixth switch transistor M6) configured to input an initialization signal (signal VINIT) to a first node (gate G of drive transistor M0) under control of a first scan signal (second scan signal terminal S2);
a switching transistor (fourth switch transistor M4) configured to input a data signal (signal on the data signal terminal DATA) to a second node (first node N1) under control of a second scan signal (first scan signal terminal S1);
a driving transistor (drive transistor M0) configured to drive the light-emitting devices (light-emitting device L) to emit light ((16)) and the second node (first node N1);
a second initialization transistor (eighth switch transistor M8) configured to input the initialization signal (signal on the initialization signal terminal VINIT) to an anode (first terminal of light-emitting device L, connected to source/drain of M7) of the light-emitting devices under control of the third scan signal (FIG. 2B, signal on reset control signal terminal CS);
a first light-emitting control transistor (third switch transistor M3) connected to the driving transistor (drive transistor M0) through the second node (first node N1), and configured to conduct a current ((16)) from a power supply high-potential signal line (first power supply terminal PVDD) to the driving transistor under control of a light-emitting control signal (first light-emitting control signal terminal EM1);
a second light-emitting control transistor (seventh switch transistor M7) connected to the driving transistor (drive transistor M0) through the third node (junction connecting M0, M5, and M7), and configured to conduct a current ((16)) from the driving transistor to the anode (first terminal of light-emitting device L, connected to source/drain of M7) of the light-emitting devices;
Tseng et al. fails to teach wherein the first initialization transistor and the second initialization transistor are oxide transistors, and the switching transistor and the second initialization transistor are different types of transistors; and
the second light-emitting control transistor under control of the light-emitting control signal.
Kim et al. (CN 108987438 A) is also silent to teach wherein the first initialization transistor and the second initialization transistor are oxide transistors, and the switching transistor and the second initialization transistor are different types of transistors; and
the second light-emitting control transistor under control of the light-emitting control signal.
Kim et al. however does teach the display device comprises a substrate (substrate 110), and a first semiconductor layer (polycrystalline semiconductor component 130A), a first metal layer (first grid metal wire (151, 154, 156 and 155a)), a second metal layer (second grid metal lines (172b, 152, 153 and 155)), a second semiconductor layer (oxide semiconductor element 130B), a third metal layer (first data metal line (171, 173, 174, 175, 176, and 178)), a first source-drain layer (driving source/drain electrodes 136a/137a), and a second source-drain layer (compensation source/drain electrodes 136c/137c) stacked on a surface of the substrate (FIG. 4);
the first metal layer (first grid metal wire (151, 154, 156 and 155a)) is patterned ([0075]) to form a plurality of first-layer scan signal lines (first scan lines 151), the second metal layer (second grid metal lines (172b, 152, 153 and 155)) is patterned to form a plurality of second-layer scan signal lines (second scan lines 152) and the third metal layer (first data metal line (171, 173, 174, 175, 176, and 178)) is patterned to form a plurality of third-layer scan signal lines (data line 171);
the first-layer scan signal lines (first scan lines 151) comprise a first scan signal line (first scan lines 151) and a second scan signal line (light emitting control line 154), the first scan signal line having a portion (switching gate electrode 155b) forming a top gate of the switching transistor (switch transistor T2).
Kim et al. is silent to the first-layer scan signal lines, the second-layer scan signal lines and the third-layer scan signal lines are extended in a first direction and arranged parallel to each other in a second direction perpendicular to the first direction; the first direction and the second direction are parallel to the surface of the substrate; and
an additional widened portion protruding away from the second scan signal line in the second direction.
Tseng et al. is similarly also silent to teach the first-layer scan signal lines, the second-layer scan signal lines and the third-layer scan signal lines are extended in a first direction and arranged parallel to each other in a second direction perpendicular to the first direction; the first direction and the second direction are parallel to the surface of the substrate; and
an additional widened portion protruding away from the second scan signal line in the second direction.
Claims 11, 12, and 15-20 allowed.
The following is a statement of reasons for the indication of allowable subject matter:
Claims 11, 12, and 15-20 are dependent on claim 10, which is allowed.
Claims 13 and 14 would be allowable if rewritten to overcome the rejection(s) under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), 2nd paragraph, set forth in this Office action and to include all of the limitations of the base claim and any intervening claims
References Cited
Tseng et al. (US 10242622 B2)
Kim et al. (CN-108987438-A)
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JEANNE M KIM whose telephone number is (571)272-8768. The examiner can normally be reached Monday-Thursday 8:00-6:00.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Leonard Chang can be reached at (571) 270-3691. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/JEANNE MYON KIM/Examiner, Art Unit 2898
/Leonard Chang/Supervisory Patent Examiner, Art Unit 2898
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