DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant’s arguments with respect to claim(s) 1, 12 and 20 have been considered but are moot because the new ground of rejection does not rely on how any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the “wherein the plurality of first pads are disposed at a position shifted from the plurality of second pads along the second direction” must be shown or the feature(s) canceled from the claim(s). No new matter should be entered.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claim 2 is rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the enablement requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to enable one skilled in the art to which it pertains, or with which it is most nearly connected, to make and/or use the invention.
Claim 2 states “wherein the plurality of first pads are disposed at a position shifted from the plurality of second pads along the second direction”. The Applicant’s Specification and drawings do not suggest shifting the pads relative to one another in the second direction. Note that the Applicant’s Specification references “DR2” as the second direction. The Applicant’s Specification only shows support in the Specification and drawings for shifting the pads relative to one another in the DR1 direction, not with respect to DR2.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1 – 5 and 12 are rejected under 35 U.S.C. 103 as being unpatentable over Bang (US 2010/0062617 A1) in view of Huang (US 2020/0083623 A1).
Regarding Claim 1, Bang (US 2010/0062617 A1) discloses a memory module (Fig 1-3, 9A; [0077]) comprising: a module printed circuit board (110) including a chip region (region or area or portion comprising 111; [0078]) and a pad region (portion or region or area comprising 115); and a plurality of memory chips (111; [0078]) provided on the module printed circuit board (110) in the chip region, wherein the module printed circuit board (110) includes a board ([0078] “circuit board”) including a first surface (surface of 110 with 115 as seen in Fig 3) and a second surface (surface of 110 with 117 as seen in Fig 3; [0053] “back side”) disposed opposite to each other, a plurality of first pads (115; [0053]) provided on the first surface in the pad region and arranged along a first direction (left-right direction in Fig 2-3; note that this is analogous to Applicant’s first-direction DR1 in Applicant’s Specification), and a plurality of second pads (117; [0053]) provided on the second surface ([0053] “back side”) in the pad region and arranged along the first direction (left-right direction in Fig 2-3), wherein a first one of the plurality of memory chips (111) is provided on the first surface (surface with 115 in Fig 9A), wherein lengths (see lengths of 115 Fig 3) of the plurality of first pads (115) in a second direction (up-down direction in Fig 3; note that this is analogous to Applicant’s second-direction DR2 in Applicant’s Specification) intersecting the first direction are the same as lengths of the plurality of second pads (see lengths of 117 Fig 3) in the second direction, and wherein the plurality of first pads (115) are disposed farther from ([0057]; see Fig 3 showing 115 is closer to right-side edge of 110 than 117 and thus further from a region with 111; see Fig 9A showing 111 in the chip region) the chip region (region with 111) than the plurality of second pads (117).
Bang does not disclose a second one of the plurality of memory chips is provided on the second surface.
Huang (US 2020/0083623 A1) teaches of a memory module (Fig 15-18) comprising: a module printed circuit board (310; [0038],0053) including a chip region (region or area or portion with 314) and a pad region (region or area or portion with 316,318); and a plurality of memory chips (314; [0038,0053]) provided on the module printed circuit board in the chip region, wherein the module printed circuit board (310) includes a board (312; [0038,0053]) including a first surface (313) and a second surface (315) disposed opposite to each other, a plurality of first pads (316) provided on the first surface (313) in the pad region and arranged along a first direction (up-down direction in Fig 15; note that this is analogous to Applicant’s first-direction DR1 in Applicant’s Specification), and a plurality of second pads (318) provided on the second surface (315) in the pad region and arranged along the first direction, wherein a first one of the plurality of memory chips (314 on 313) is provided on the first surface (313) and a second one of the plurality of memory chips (314) is provided on the second surface (315), wherein lengths of the plurality of first pads (316) in a second direction (left-right direction in Fig 15; note that this is analogous to Applicant’s first-direction DR2 in Applicant’s Specification) intersecting the first direction are the same (see Fig 15) as lengths of the plurality of second pads (318) in the second direction, and wherein the plurality of first pads (316) are disposed farther (see Fig 18 showing 316 on 313 is farther from 314 than 318 on 315) from the chip region than the plurality of second pads (318).
It would have been obvious to a person having ordinary skill in the art before the effective filling date of the claimed invention to modify the module as disclosed by Bang, wherein a second one of the plurality of memory chips is provided on the second surface as taught by Huang, in order to increase limits of a computer system performance, and take advantage of high performance capabilities (Huang, [0002,0067]) and furthermore increasing memory modules can increase the overall memory capability of a computer system.
Regarding Claim 2, Bang in view of Huang teaches the limitations of the preceding claim.
Bang (in Fig 3) does not explicitly show the memory module of claim 1, wherein the plurality of first pads are disposed at a position shifted from the plurality of second pads along the second direction.
Bang further teaches of a memory module (Fig 4), wherein a plurality of first pads (115) are disposed at a position shifted from a plurality of second pads (117) along the second direction (up-down direction in Fig 4; note that this is analogous to Applicant’s second-direction DR2 in Applicant’s Specification).
It would have been obvious to a person having ordinary skill in the art before the effective filling date of the claimed invention to modify the module as taught by Bang in view of Huang, wherein the plurality of first pads are disposed at a position shifted from the plurality of second pads along the second direction as taught by Bang, as both limitations are presented in the same publication and in order to allow for desired trace patterns on a board surface around unconnected pads.
Regarding Claim 3, Bang further discloses the memory module (Fig 3) of claim 1 wherein a first pad (e.g. 115a) of the plurality of first pads (115) has a pair of first width sides (sides of 115 in Fig 3) extending along the second direction (up-down direction in Fig 3), wherein a second pad (117a) of the plurality of second pads (117) has a pair of second width sides (sides of 117 in Fig 3) extending along the second direction, wherein the board (110) is disposed in the pad region and has a reference side (118) extending along the second direction (118 extends in up-down direction in Fig 3), and wherein a distance (e.g. x) between one of the pair of first width sides adjacent to the reference side (118) and the reference side (118) is smaller than a distance between one of the pair of second width sides adjacent to the reference side (118) and the reference side.
Regarding Claim 4, Bang further discloses the memory module (Fig 3) of claim 3, wherein a first center line (an imaginary line through the centers of 115) extending along the second direction (up-down direction of Fig 3) and passing through the center of the first pad (115) is spaced apart in the first direction (left-right direction) from a second center line (an imaginary line through the centers of 117) extending along the second direction and passing through the center of the second pad (117).
Regarding Claim 5, Bang further discloses the memory module (Fig 3) of claim 3, wherein a distance (distance from 115 to right side edge in Fig 3) between one of the pair of first width sides (sides of 115) disposed farther from the reference side and the reference side is different (structure shown is similar to the Applicant’s shown figures) from the distance between one of the pair of second width sides (sides of 117) adjacent to the reference side and the reference side (118).
Regarding Claim 12, Bang discloses an electronic device assembly (Fig 1-3,9A,20; [0077,0121-0123]) comprising: a main printed circuit board (3008 as seen in Fig 20); a memory module (3010; 210 as seen in Fig 9A); and a connector (130 as seen in Fig 9A) provided between the main printed circuit board (3008) and the memory module (3010; 210), wherein the memory module (210) includes a module printed circuit board (110) including a chip region (region or area or portion comprising 111; [0078]) and a pad region (portion or region or area comprising 115), and a plurality of memory chips (111; [0078]) provided on the module printed circuit board (110) in the chip region, wherein the module printed circuit board includes a first surface (surface of 110 with 115 as seen in Fig 3) provided on one side of the main printed circuit board, a second surface (surface of 110 with 117 as seen in Fig 3; [0053] “back side”) opposite to the first surface and facing the main printed circuit board (see Fig 20 showing both sides of 3010 face 3008), a plurality of first pads (115; [0053]) provided on the first surface in the pad region and arranged along a first direction (left-right direction in Fig 2-3; note that this is analogous to Applicant’s first-direction DR1 in Applicant’s Specification), and a plurality of second pads (117; [0053]) provided on the second surface ([0053] “back side”) in the pad region and arranged along the first direction, wherein a first one of the plurality of memory chips (111) is provided on the first surface, wherein lengths (see lengths of 115 Fig 3) of the plurality of first pads (115) in a second direction (up-down direction in Fig 3; note that this is analogous to Applicant’s second-direction DR2 in Applicant’s Specification) intersecting the first direction are the same as lengths of the plurality of second pads (see lengths of 117 Fig 3) in the second direction, and wherein the plurality of first pads (115) are disposed farther from ([0057]; see Fig 3 showing 115 is closer to right-side edge of 110 than 117 and thus further from a region with 111; see Fig 9A showing 111 in the chip region) the chip region (region with 111) than the plurality of second pads (117).
Bang does not disclose a second one of the plurality of memory chips is provided on the second surface.
Huang teaches of an electronic device assembly (Fig 15-18,29-30) comprising: a main printed circuit board (850); a memory module (810); and a connector (830) provided between the main printed circuit board (850) and the memory module (830), wherein the memory module includes a module printed circuit board (310; [0038],0053) including a chip region (region or area or portion with 314) and a pad region (region or area or portion with 316,318), and a plurality of memory chips (314; [0038,0053]) provided on the module printed circuit board (310) in the chip region, wherein the module printed circuit board includes a first surface (313) provided on one side of the main printed circuit board, a second surface (315) opposite to the first surface and facing the main printed circuit board, a plurality of first pads (316) provided on the first surface in the pad region and arranged along a first direction (up-down direction in Fig 15; note that this is analogous to Applicant’s first-direction DR1 in Applicant’s Specification), and a plurality of second pads (318) provided on the second surface (315) in the pad region and arranged along the first direction, wherein a first one of the plurality of memory chips (314 on 313) is provided on the first surface (313) and a second one of the plurality of memory chips (314) is provided on the second surface (315), wherein lengths of the plurality of first pads (316) in a second direction (left-right direction in Fig 15; note that this is analogous to Applicant’s first-direction DR2 in Applicant’s Specification) intersecting the first direction are the same (see Fig 15) as lengths of the plurality of second pads (318) in the second direction, and wherein the plurality of first pads (316) are disposed farther (see Fig 18 showing 316 on 313 is farther from 314 than 318 on 315) from the chip region than the plurality of second pads (318).
It would have been obvious to a person having ordinary skill in the art before the effective filling date of the claimed invention to modify the assembly as disclosed by Bang, wherein a second one of the plurality of memory chips is provided on the second surface as taught by Huang, in order to increase limits of a computer system performance, and take advantage of high performance capabilities (Huang, [0002,0067]) and furthermore increasing memory modules can increase the overall memory capability of a computer system.
Claim(s) 6 is rejected under 35 U.S.C. 103 as being unpatentable over Bang (US 2010/0062617 A1) in view of Huang (US 2020/0083623 A1) as applied to claim 3 above, and further in view of Chen (US 2023/0009150 A1).
Regarding Claim 6, Bang in view of Huang teaches the limitations of the preceding claim and the structure as taught by Bang in view of Huang would seem substantially similar to the structure as shown by Applicant.
Bang does not disclose the memory module of claim 3, wherein a distance between one of the pair of first width sides disposed farther from the reference side and the reference side is the same as the distance between one of the pair of second width sides adjacent to the reference side and the reference side.
It would have been obvious to a person having ordinary skill in the art before the effective filling date of the claimed invention to modify the module as taught by Bang in view of Huang, wherein a distance between one of the pair of first width sides disposed farther from the reference side and the reference side is the same as the distance between one of the pair of second width sides adjacent to the reference side and the reference side, in order to improve reliability, reduce costs and improve user experience (Chen, [0028,0101-0111]), since it has been held that discovering an optimum value of a result effective variable involves only routine skill in the art. In re Boesch, 617 F.2d 272, 205 USPQ 215 (CCPA 1980). Please note that in the instant application, pages 14-15, [0048-0050], Applicant has not disclosed any criticality for the claimed limitations.
Claim(s) 7 – 11 are rejected under 35 U.S.C. 103 as being unpatentable over Bang (US 2010/0062617 A1) in view of Huang (US 2020/0083623 A1) as applied to claim 1 above, and further in view of Koga (US 2006/0113109 A1).
Regarding Claim 7, Bang in view of Huang teaches the limitations of the preceding claim.
Bang does not disclose the memory module of claim 1, wherein the plurality of first pads include a first power pad, a first ground pad, and a first signal pad, and wherein a width of the first power pad and a width of the first ground pad are greater than a width of the first signal pad.
Koga (US 2006/0113109 A1) teaches of a module (Fig 5), wherein a first pad is a plurality of first pads, wherein the plurality of first pads (141-144) include a first power pad (144; [0038]), a first ground pad (151; [0038]), and a first signal pad (141,142; [0033-0038]), and wherein a width (dimension of 144 in the left-right direction of Fig 5) of the first power pad (144) and a width (dimension of 143 in the left-right direction of Fig 5) of the first ground pad (143) are greater than a width (dimension of 141,142 in the left-right direction of Fig 5) of the first signal pad (141,142).
It would have been obvious to a person having ordinary skill in the art before the effective filling date of the claimed invention to modify the module as taught by Bang in view of Huang, wherein the plurality of first pads include a first power pad, a first ground pad, and a first signal pad, and wherein a width of the first power pad and a width of the first ground pad are greater than a width of the first signal pad as taught by Koga, in order to control impedance, reduce resistance and ensure sufficient power capacity (Koga, [0033-0051]).
Regarding Claim 8, Bang in view of Huang and Koga teaches the limitations of the preceding claim.
Bang does not explicitly disclose wherein the width of the first power pad is different from the width of the first ground pad.
Koga (US 2006/0113109 A1) teaches of a module (Fig 9), wherein a first pad is a plurality of first pads, wherein the plurality of first pads (141-144,151) include a first power pad (144; [0038]), a first ground pad (151; [0038]), and a first signal pad (141,142; [0033-0038]), and wherein a width (dimension of 144 in the left-right direction of Fig 5) of the first power pad (144) and a width (dimension of 151 in the left-right direction of Fig 5) of the first ground pad (151) are greater than a width (dimension of 141,142 in the left-right direction of Fig 5) of the first signal pad (141,142), wherein the width of the first power pad (144) is different from the width of the first ground pad (151).
It would have been obvious to a person having ordinary skill in the art before the effective filling date of the claimed invention to modify the module as taught by Bang in view of Huang and Koga, wherein the width of the first power pad is different from the width of the first ground pad as taught by Koga, as both limitations are presented by the same publication and in order to reduce crosstalk and provide shielding (Koga, [0033-0051]).
Regarding Claim 9, Bang in view of Huang and Koga teaches the limitations of the preceding claim and Koga further teaches the memory module (Fig 5) of claim 7, wherein the width of the first power pad (144) is the same as the width of the first ground pad (143).
Regarding Claim 10, Bang in view of Huang and Koga teaches the limitations of the preceding claim.
Bang does not disclose wherein the plurality of second pads include a second power pad, a second ground pad, and a second signal pad, and wherein a width of the second power pad and a width of the second ground pad are greater than a width of the second signal pad.
However Koga (US 2006/0113109 A1) teaches of a module (Fig 5), wherein a first pad is a plurality of first pads, wherein the plurality of first pads (141-144) include a first power pad (144; [0038]), a first ground pad (151; [0038]), and a first signal pad (141,142; [0033-0038]), and wherein a width (dimension of 144 in the left-right direction of Fig 5) of the first power pad (144) and a width (dimension of 143 in the left-right direction of Fig 5) of the first ground pad (143) are greater than a width (dimension of 141,142 in the left-right direction of Fig 5) of the first signal pad (141,142).
It would have been obvious to a person having ordinary skill in the art before the effective filling date of the claimed invention to modify the module as taught by Bang in view of Huang and Koga, wherein the plurality of second pads include a second power pad, a second ground pad, and a second signal pad, and wherein a width of the second power pad and a width of the second ground pad are greater than a width of the second signal pad as taught by Koga, in order to control impedance, reduce resistance and ensure sufficient power capacity (Koga, [0033-0051]).
Regarding Claim 11, Bang in view of Huang teaches the limitations of the preceding claim.
Bang does not explicitly disclose wherein each of the plurality of first pads has a width smaller than a width of each of the plurality of second pads.
Koga (US 2006/0113109 A1) teaches of a module (Fig 5), wherein a first pad is a plurality of first pads, wherein the plurality of first pads (141-144) include a first power pad (144; [0038]), a first ground pad (151; [0038]), and a first signal pad (141,142; [0033-0038]), and wherein a width (dimension of 144 in the left-right direction of Fig 5) of the first power pad (144) and a width (dimension of 143 in the left-right direction of Fig 5) of the first ground pad (143) are greater than a width (dimension of 141,142 in the left-right direction of Fig 5) of the first signal pad (141,142).
It would have been obvious to a person having ordinary skill in the art before the effective filling date of the claimed invention to modify the module as taught by Bang in view of Huang, wherein each of the plurality of first pads has a width smaller than a width of each of the plurality of second pads as taught by Koga, in order to control impedance, reduce resistance and ensure sufficient power capacity (Koga, [0033-0051]). As some of the plurality of first pads will have differing functions than some of the plurality of second pads, such as grounding or providing power or providing signal, each of the plurality of first pads for signal connection would have a width smaller than a width of each of the plurality of second pads for providing power or ground.
Claim(s) 13 – 15 are rejected under 35 U.S.C. 103 as being unpatentable over Bang (US 2010/0062617 A1) in view of Huang (US 2020/0083623 A1) as applied to claim 12 above, and further in view of Turnbull (US 6,053,757).
Regarding Claim 13, Bang in view of Huang teaches the limitations of the preceding claim.
Bang further discloses the electronic device assembly (Fig 9A) of claim 12, wherein the connector (130) includes a housing (at 130), a plurality of first pins (133) inserted into an upper part of the housing (130).
Huang does not disclose a plurality of second pins inserted into a lower part of the housing, wherein the plurality of first pins protrude from the upper part of the housing and are electrically connected to the plurality of first pads, and wherein the plurality of second pins protrude from the lower part of the housing and are electrically connected to the plurality of second pads.
Turnbull (US 6,053,757) teaches of an electronic device assembly (Fig 1; rotate figure 90º such that 14 is an upper contact and 10 is a lower contact), wherein a connector (2) includes a housing (4), a plurality of first pins (14) inserted into an upper part (right side of Fig 1; note that no datum of reference has been established for establishing “upper”) of the housing, and a plurality of second pins (10) inserted into a lower part (left side of Fig 1; note that no datum of reference has been established for establishing “lower”) of the housing, wherein the plurality of first pins (14) protrude (at 36,36’) from the upper part of the housing and are electrically connected to the plurality of first pads (28), and wherein the plurality of second pins (10) protrude (at 36,36’) from the lower part of the housing and are electrically connected to the plurality of second pads (26).
It would have been obvious to a person having ordinary skill in the art before the effective filling date of the claimed invention to modify the assembly as taught by Bang in view of Huang, wherein the connector includes a housing, a plurality of first pins inserted into an upper part of the housing, and a plurality of second pins inserted into a lower part of the housing, wherein the plurality of first pins protrude from the upper part of the housing and are electrically connected to the plurality of first pads, and wherein the plurality of second pins protrude from the lower part of the housing and are electrically connected to the plurality of second pads as taught by Turnbull, in order to establish a connection, provide a spring contact, provide flexibility, provide resiliency, compensate for warping of the board, and allow for visual inspection (Turnbull, Column 2, lines 9-44, Column 3 lines 14-67, Column 4, lines 15-30).
Regarding Claim 14, Bang in view of Huang and Turnbull teaches the limitations of the preceding claim and Bang further discloses (Fig 3) an arrangement direction (left-right direction in Fig 3) of the chip region and the pad region.
Turnbull further teaches the electronic device assembly (Fig 1) of claim 13, wherein, when viewed along a direction perpendicular (view of Fig 1) to the first surface, the plurality of first pins (14,36’) are positioned shifted from the plurality of second pins (10,36) in a direction parallel to an arrangement direction (up-down direction of Fig 1).
Regarding Claim 15, Bang in view of Huang and Turnbull teaches the limitations of the preceding claim.
Turnbull further teaches the electronic device assembly (Fig 1) of claim 13, wherein, from a perspective (as seen in Fig 1) along a direction perpendicular to the first surface, first contact regions (regions at 14,36’) where the plurality of first pins (14,36’) and the plurality of first pads (28) are in contact are spaced apart (see offset in Fig 1 from 28 and 26) from second contact regions (region at 10,36) where the plurality of second pins (10,36) and the plurality of second pads (26) are in contact in a direction parallel to an arrangement direction (up-down direction in Fig 1 of Turnbull is equivalent to the arrangement direction of Huang) of the chip region and the pad region.
Claim(s) 16 – 19 are rejected under 35 U.S.C. 103 as being unpatentable over Bang (US 2010/0062617 A1) in view of Huang (US 2020/0083623 A1) as applied to claim 12 above, and further in view of Koga (US 2006/0113109 A1).
Regarding Claim 16, Bang in view of Huang teaches the limitations of the preceding claim.
Bang does not disclose the electronic device assembly of claim 12, wherein the plurality of first pads include a first power pad, a first ground pad, and a first signal pad, and wherein a width of the first power pad and a width of the first ground pad are greater than a width of the first signal pad.
Koga (US 2006/0113109 A1) teaches of a module (Fig 5), wherein a first pad is a plurality of first pads, wherein the plurality of first pads (141-144) include a first power pad (144; [0038]), a first ground pad (151; [0038]), and a first signal pad (141,142; [0033-0038]), and wherein a width (dimension of 144 in the left-right direction of Fig 5) of the first power pad (144) and a width (dimension of 143 in the left-right direction of Fig 5) of the first ground pad (143) are greater than a width (dimension of 141,142 in the left-right direction of Fig 5) of the first signal pad (141,142).
It would have been obvious to a person having ordinary skill in the art before the effective filling date of the claimed invention to modify the assembly as taught by Bang in view of Huang, wherein the plurality of first pads include a first power pad, a first ground pad, and a first signal pad, and wherein a width of the first power pad and a width of the first ground pad are greater than a width of the first signal pad as taught by Koga, in order to control impedance, reduce resistance and ensure sufficient power capacity (Koga, [0033-0051]).
Regarding Claim 17, Bang in view of Huang and Koga teaches the limitations of the preceding claim and Bang further discloses the electronic device assembly of claim 16, wherein the second pad (117) is a plurality of second pads (see Fig 3).
Bang does not disclose wherein the plurality of second pads include a second power pad, a second ground pad, and a second signal pad, and wherein a width of the second power pad and a width of the second ground pad are greater than a width of the second signal pad.
However Koga (US 2006/0113109 A1) teaches of a module (Fig 5), wherein a first pad is a plurality of first pads, wherein the plurality of first pads (141-144) include a first power pad (144; [0038]), a first ground pad (151; [0038]), and a first signal pad (141,142; [0033-0038]), and wherein a width (dimension of 144 in the left-right direction of Fig 5) of the first power pad (144) and a width (dimension of 143 in the left-right direction of Fig 5) of the first ground pad (143) are greater than a width (dimension of 141,142 in the left-right direction of Fig 5) of the first signal pad (141,142).
It would have been obvious to a person having ordinary skill in the art before the effective filling date of the claimed invention to modify the assembly as taught by Bang in view of Huang and Koga, wherein the plurality of second pads include a second power pad, a second ground pad, and a second signal pad, and wherein a width of the second power pad and a width of the second ground pad are greater than a width of the second signal pad as taught by Koga, in order to control impedance, reduce resistance and ensure sufficient power capacity (Koga, [0033-0051]).
Regarding Claim 18, Bang in view of Huang teaches the limitations of the preceding claim.
Bang further discloses the electronic device assembly of claim 12, wherein the first pad (115) is a plurality of first pads (see Fig 3), wherein the second pad (117) is a plurality of second pads (see Fig 3).
Bang does not explicitly disclose wherein each of the plurality of first pads has a width smaller than a width of each of the plurality of second pads.
Koga (US 2006/0113109 A1) teaches of a module (Fig 5), wherein a first pad is a plurality of first pads, wherein the plurality of first pads (141-144) include a first power pad (144; [0038]), a first ground pad (151; [0038]), and a first signal pad (141,142; [0033-0038]), and wherein a width (dimension of 144 in the left-right direction of Fig 5) of the first power pad (144) and a width (dimension of 143 in the left-right direction of Fig 5) of the first ground pad (143) are greater than a width (dimension of 141,142 in the left-right direction of Fig 5) of the first signal pad (141,142).
It would have been obvious to a person having ordinary skill in the art before the effective filling date of the claimed invention to modify the assembly as taught by Bang in view of Huang, wherein each of the plurality of first pads has a width smaller than a width of each of the plurality of second pads as taught by Koga, in order to control impedance, reduce resistance and ensure sufficient power capacity (Koga, [0033-0051]). As some of the plurality of first pads will have differing functions than some of the plurality of second pads, such as grounding or providing power or providing signal, each of the plurality of first pads for signal connection would have a width smaller than a width of each of the plurality of second pads for providing power or ground.
Regarding Claim 19, Bang in view of Huang and Koga teaches the limitations of the preceding claim and Bang further teaches the plurality of first pads and plurality of second pads.
Koga further teaches the electronic device assembly (Fig 5) of claim 18, wherein the plurality of first pads are signal pads (141,142 on one side of board), and wherein some of the plurality of second pads are power pads (144 on other side of board), and others of the plurality of second pads are ground pads (143 on the other side of the board).
Claim(s) 20 is rejected under 35 U.S.C. 103 as being unpatentable over Watari (US 2022/03112589) in view of Eguchi (US 2010/0079969 A1).
Regarding Claim 20, Watari (US 2022/03112589) discloses a memory module (Fig 4) comprising: a board (5) having a first surface (upper surface of 5 seen in Fig 3) and a second surface (lower surface of 5 seen in Fig 3) disposed opposite each other; a memory chip (10,20; [0019,0051]) provided on the first surface (upper surface of 5 seen in Fig 3); and a plurality of first pads (51c,52c; [0034]) provided on the second surface and overlapping the memory chip (see Fig 3) along an arrangement direction of the first surface and the second surface, the arrangement direction (up-down direction in Fig 3) being a direction that is perpendicular to the first surface and the second surface.
Watari would seem to show in Fig 4 that the connector (6; [0030]) has pads that are seemingly smaller than the pads 51,52), however Watari does not explicitly disclose wherein some of the plurality of first pads have an area smaller than an area of others of the plurality of first pads. In order to speed prosecution, a secondary reference is provided.
Eguchi (US 2010/0079969 A1) teaches of a memory module (Fig 2-3; [0031]) comprising: a board (11) having a first surface (surface seen in Fig 3) and a second surface (surface seen in Fig 2) disposed opposite each other; a chip (18; [0033]); and a plurality of first pads (15) provided on the second surface, the arrangement direction (left-right direction in Fig 3) being a direction that is perpendicular to the first surface and the second surface, wherein some of the plurality of first pads (15a) have an area ([0033-0035]) smaller than an area of others (15b) of the plurality of first pads.
It would have been obvious to a person having ordinary skill in the art before the effective filling date of the claimed invention to modify the assembly as disclosed by Watari, wherein some of the plurality of first pads have an area smaller than an area of others of the plurality of first pads as taught by Eguchi, in order to establish an electrical connection, reduce insertion force, control redundancy, control functions of pads such as to provide power or grounding (Eguchi, [0003-0011,0032-0036,0084-0090]). Note that larger pad surface areas allow for easier access and therefore easier testing capabilities, whereas smaller surface area pads allow for an increase in the number of pads on the board surface, and thus increase a functionality and a capability of the board. Note also that the Applicant has not structurally detailed the pads nor which pads that may comprise different surface areas.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/ROSHN K VARGHESE/Primary Examiner, Art Unit 2847
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