DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 19 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Lin et al. (US 2023/0009852 A1).
Regarding claim 19, Lin discloses a semiconductor device (Fig 28), comprising: a first source/drain region (234p); a conductive layer (258) over a top surface and upper half of sidewalls of the first source/drain region; and a first contact (260) connecting the first source/drain region to a back end of line (BEOL) through the conductive layer, a via and a metal line.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lin et al. (US 2023/0009852 A1).
Lin discloses a semiconductor device (Fig 28), comprising: a first source/drain region (234p); a conductive layer (258) over a top surface and upper half of sidewalls of the first source/drain region; and a first contact (260) connecting the first source/drain region.
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Lin does not explicitly disclose that the contact connects the first source/drain region to a BEOL through the conductive layer, a via and a metal line. However, such a connection would have been obvious to one of ordinary skill in the art at the time of filing as the connection of source/drain regions to a BEOL through the conductive layer, a via and a metal line is how the source/drain regions of a transistor are wired so that they may be addressed and form a functional device. This means of connecting a source/drain to the metallization layer of an integrated device is a standard practice in the art which is old and well-known.
Claim(s) 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lin as applied to claim 19 above, and further in view of More (US 2022/0051949 A1).
Lin discloses a second source/drain region (234n) but does not disclose that the length of the first source/drain is larger than a length of the second source/drain.
More discloses forming a p-type source/drain (as is the first source/drain of Lin) to have a greater width (i.e. a larger length as the direction which defines length versus width of the source/drains is not claimed) than the n-type source/drain (as is the second source/drain of Lin) in order optimize the contact resistance of the p-type source/drain region for a logic device.
Therefore it would have been obvious to one of ordinary skill in the art at the time of filing to form the source/drain contacts of Lin such that the p-type source/drain has a larger length than the n-type source/drain as suggested by More in order to optimize the contact resistance of the p-type source/drain region when integrated into a logic device.
Allowable Subject Matter
Claims 1-18 are allowed.
The following is an examiner’s statement of reasons for allowance:
Park et al.(US 2025/0351567 A1) discloses a semiconductor device (Fig 3E) similar to that claimed in claim 1 and manufactured by the method of 11, including a top source/drain region (235); and a bottom source/drain region (135), wherein a length of the bottom source/drain region is larger than a length of the top source/drain region.
Park does not disclose a conductive layer over a top surface and upper half of sidewalls of the bottom source/drain region but rather makes contact to the bottom source/drain region through contact structure 118. It would not have been obvious to modify the bottom source/drain region of Park nor that of other prior art to have the conductive layer as claimed due to the increase in process complexity without a benefit recognized in the art. Even if a silicide was formed between source/drain 135 and contact 118, such a silicide would not extend over the top surface and upper half of the sidewalls as claimed.
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Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DANIEL P SHOOK whose telephone number is (571)270-7890. The examiner can normally be reached 9:00 am - 5:00 pm, Mon-Fri.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, WILLIAM KRAIG can be reached at (571)272-8660. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/DANIEL P SHOOK/ Primary Examiner, Art Unit 2896
