DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1, 5-7, and 9-10 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Hieda (US 2004/0079980.)
In regard to claim 1, in fig. 2, Hieda discloses a semiconductor device comprising:
a device layer on a substrate 10 (semiconductor substrates include device layer 11, for example, para [0034]);
an interconnection layer 24 disposed on the device layer, wherein the interconnection layer includes conductive interconnections forming a plurality of layers; and
first and second capacitor structures A and B disposed inside the interconnection layer,
wherein each of the first and second capacitor structures includes:
electrode layers 13/17 spaced apart from each other in a vertical direction and forming three or more layers (para [0035]);
dielectric layers 16 between the electrode layers;
conductive vias 25, for example, respectively connected to one of the electrode layers and extending vertically;
a first connection terminal 26 electrically connected to a lowermost electrode layer; and
a second connection terminal 26 electrically connected to at least one of the electrode layers,
wherein the first capacitor structure and the second capacitor structure include the same number of electrode layers, and wherein a first capacitance of the first capacitor structure is
different from a second capacitance of the second capacitor structure (capacitor A has two dielectric layers formed of different dielectric materials 14 and 16; thus, has a different capacitance, para [0035].)
Regarding claim 5, wherein the dielectric layers comprise silicon nitride (para [0044].)
Regarding claim 6, wherein a second connection terminal included in the first capacitor structure is in contact with a plurality of conductive vias. Fig. 2.
Regarding claim 7, wherein the conductive interconnections comprise lower interconnections 12, wherein the capacitor structures are disposed on upper surfaces of the lower interconnections. Fig. 2.
Regarding claim 9, wherein at least one of electrode layers included in the first capacitor structure is not electrically connected to the first connection terminal and the second connection terminal. Fig. 2.
Regarding claim 10, wherein the number of conductive vias included in the first capacitor structure is different from the number of conductive vias included in the second capacitor structure. Figs/ 1-2.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 2-4, and 8 is/are rejected under 35 U.S.C. 103 as being unpatentable over Hieda as applied to claim 1 above, and further in view of Tsai et al. (US 2024/0313041, hereinafter, Tsai.)
Regarding claim 2, Hieda discloses all of the claimed limitations as mentioned above. Hieda also discloses the electrodes are made of TiN and the conductive interconnection 25 is made of metal, except further mentioning which metal. Tsai, in fig. 1, discloses an analogous semiconductor device 2 including capacitor formed on a device layer of a substrate 10 and capacitors 46A, 46B, and 46C. Tsai further teaches the interconnect made of copper, Cu (para [0020], a common metal that provides better conductivity and availability.
Therefore, it would have been obvious to one of ordinary skill in the art at the time of the application was filed to use the metal as taught in order to take the advantage.
Regarding claim 3, wherein the electrode layers comprise a material different from a material of the conductive interconnections. Layer in via 25 is made of metal and electrodes are made of TiN (see the description in paras [0051] and [0036].)
Regarding claim 4, wherein a specific resistance of the electrode layers is greater than a specific resistance of the conductive interconnections, copper and TiN.
Regarding claim 8, Tsai further discloses wherein the first capacitor structure is located on a different vertical level from the second capacitor structure. Fig. 1.
Allowable Subject Matter
Claims 11-14 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The prior art does not show wherein the semiconductor device further comprises a third capacitor structure,
wherein the number of electrode layers included in the third capacitor structure is different from the number of electrode layers included in the first capacitor structure, and
a third capacitance of the third capacitor structure is different from the first capacitance and the second capacitance.
Claims 15-20 are allowed.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to NATHAN W HA whose telephone number is (571)272-1707. The examiner can normally be reached M-T: 8:00AM-6:00PM.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, WAEL FAHMY can be reached at (571)-272-1705. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/NATHAN W HA/Primary Examiner, Art Unit 2814
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