DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Status of Claims
The status of the claims is as follows: Claims 1-9 are pending. An action on the merits for claims 1-9 follows.
Priority Claim
Acknowledgment is made of applicant’s claim for foreign priority under 35 U.S.C. 119 (a)-(d). However, should applicant desire to obtain the benefit of foreign priority under 35 U.S.C. 119(a)- (d) prior to declaration of an interference, a certified English translation of the foreign application must be submitted in reply to this action. 37 CFR 41.154(b) and 41.202(e). Failure to provide a certified translation may result in no benefit being accorded for the non- English application.
IDS
All references provided in the IDS have been considered.
Claim Objections
Claim 2 is objected to because of the following informalities:
Claims 2 appears to introduce multiple new elements not clearly and distinctly pointed out and should be improved for readability and clarity. The following changes are suggested.
Claim 2 should read: “The semiconductor wafer temperature measurement method according to claim 1, further comprising introducing the impurity into the first surface of the wafer so that a crystal growth speed of the amorphous layer when recrystallizing is a desired speed.” Appropriate correction is required.
Additionally, claim 3 is objected to due to its dependence on claim 2.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-3, 5, 6, and 7 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Yamazawa et al. “A wafer surface temperature measurement method utilizing the reordering phenomena of amorphous silicon,” IEEE, hereinafter Yamazawa.
Regarding Claim 1, Yamazawa teaches a semiconductor wafer temperature measurement method ("novel temperature measurement method, called the REAL method;" pg.3351, sec.1, para. 2) comprising:
introducing an impurity ("ion implantation;" p.3351, sec. 2, para. 3) into a first surface of a wafer ("temperature measurement wafers;" p.3351, sec. 2, para. 3) to form an amorphous layer ("amorphous layer;" p.3352, sec. 2, col. 1, para. 1) on a side of the first surface of the wafer ("temperature measurement wafer");
measuring a first film thickness ("measurements of the difference in the layer thickness;" p.3352, sec. 2, col. 1, para. 1) that is the film thickness of the amorphous layer ("amorphous layer");
thermally treating (with "thermal process;" p.3352, sec. 2, col. 1, para. 1) the wafer ("temperature measurement wafer") to recrystallize part of the amorphous layer ("amorphous layer");
measuring a second film thickness ("measurements of the difference in the layer thicknesses;" p.3352, sec. 2, col. 1, para. 1) that is the film thickness of the amorphous layer ("amorphous layer") after the thermal treatment ("thermal process") ; and
measuring the temperature ("temperature can be derived;" p.3352, sec. 2, col. 1, para. 1) of the wafer ("temperature measurement wafer") at the thermal treatment ("thermal process") based on a film thickness difference ("difference in the amorphous layer thicknesses;" p.3352, sec. 2, col. 1, para. 2) between the first film thickness and the second film thickness. ("measurements of the difference of the layer thickness;" p.3352, sec. 2, col. 1, para. 1 necessarily implies a measurement being taken before and after the thermal treatment process causing the crystal growth.)
Regarding Claim 2, Yamazawa teaches the semiconductor wafer temperature measurement method according to claim 1, further comprising introducing the impurity (by "ion implantation") into the first surface of the wafer ("temperature measurement wafer") so that crystal growth speed of the amorphous layer ("amorphous layer") when recrystallizing is desired speed ("ion implanting at a specific condition (ion species […]), which produces the reordering rate R;" Fig. 1, p.3352, sec.2, col. 1, para. 4: from this paragraph, the growth speed is clearly dependent on the implantation condition and results in a desired crystal growth speed (or reordering rate)).
Regarding Claim 3, Yamazawa teaches the semiconductor wafer temperature measurement method according to claim 2, further comprising introducing the impurity (by "ion implantation") into the first surface of the wafer ("temperature measurement wafer") with an element or concentration of the impurity in accordance with temperature (ion implanting at a specific condition (ion species […]), which produces the reordering rate R to be a function of temperature;" Fig. 1, p.3352, sec.2, col. 1, para. 4: from this paragraph, the growth speed is clearly dependent on the implantation condition and temperature together, resulting in a desired crystal growth speed (or reordering rate)) at the thermal treatment ("thermal process").
Regarding Claim 5, Yamazawa teaches the semiconductor wafer temperature measurement method according to claim 1, further comprising introducing the impurity (by "ion implantation") into the wafer ("temperature measurement wafer") without forming a cover film that covers the first surface. (Fig. 1 clearly shows the impurity implantation process where impurities directly contact the amorphous layer where no cover film or other material is intervening. The implantation is seen to directly contact the wafer.)
Regarding Claim 6, Yamazawa teaches the semiconductor wafer temperature measurement method according to claim 1, further comprising thermally treating (with "thermal process") the wafer ("temperature measurement wafer") for a predetermined time or longer ("altering the process time;" p.3353, sec. 4.1, para. 2: By altering the thermal process time, a predetermined time is set and the process has to take at least some determined amount of time).
Regarding Claim 7, Yamazawa teaches the semiconductor wafer temperature measurement method according to claim 1, wherein the measuring of the temperature of the wafer ("temperature measurement wafer") at the thermal treatment ("thermal process") based on the film thickness difference includes converting the film thickness difference ("difference in the amorphous layer thicknesses") into the temperature of the wafer ("temperature measurement wafer") at the thermal treatment ("thermal process") based on a preset relation between the film thickness difference ("difference in the amorphous layer thicknesses") and the temperature of the wafer ("temperature measurement wafer") at the thermal treatment ("thermal process") ("the difference in the layer thickness among each wafer should be proportional to the difference in their processing time. Thus, under such conditions, the temperature can be derived from the reordering rate calculated from measurements of the difference of the layer thickness among several wafers;" p.3352, sec. 2, col. 1, para. 1).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 4, 8, and 9 are rejected under 35 U.S.C. 103 as being unpatentable over Yamazawa in view of (US 6475815 B1), hereinafter Nambu.
Regarding Claim 4, Yamazawa teaches the semiconductor wafer temperature measurement method according to claim 1.
Yamazawa does not explicitly teach wherein the element of the impurity includes at least one of Si, Ge, P, As, Ar, or Sb.
Nambu teaches at least a temperature measurement method (“method of measuring a temperature;” Col. 2, Lines 53-55) wherein the element of the impurity includes at least one of Si, Ge, P, As, Ar, or Sb ("implanting Ge ions;" Col. 2, Lines 66-67).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the method of Yamazawa with the teachings of Nambu such that the element of the impurity includes at least one of Si, Ge, P, As, Ar, or Sb. The impurity being Ge provides a distinct boundary between the amorphous and non-amorphous region with the added benefit of increasing accuracy and reliability of the temperature measurement (Col. 3, Lines 1-4).
Regarding Claim 8, Yamazawa teaches the semiconductor wafer temperature measurement method according to claim 2.
Yamazawa does not explicitly teach wherein the element of the impurity includes at least one of Si, Ge, P, As, Ar, or Sb.
Nambu teaches at least a temperature measurement method (“method of measuring a temperature;” Col. 2, Lines 53-55) wherein the element of the impurity includes at least one of Si, Ge, P, As, Ar, or Sb ("implanting Ge ions;" Col. 2, Lines 66-67).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the method of Yamazawa with the teachings of Nambu such that the element of the impurity includes at least one of Si, Ge, P, As, Ar, or Sb. The impurity being Ge provides a distinct boundary between the amorphous and non-amorphous region with the added benefit of increasing accuracy and reliability of the temperature measurement (Col. 3, Lines 1-4).
Regarding Claim 9, Yamazawa teaches the semiconductor wafer temperature measurement method according to claim 3.
Yamazawa does not explicitly teach wherein the element of the impurity includes at least one of Si, Ge, P, As, Ar, or Sb.
Nambu teaches at least a temperature measurement method (“method of measuring a temperature;” Col. 2, Lines 53-55) wherein the element of the impurity includes at least one of Si, Ge, P, As, Ar, or Sb ("implanting Ge ions;" Col. 2, Lines 66-67).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the method of Yamazawa with the teachings of Nambu such that the element of the impurity includes at least one of Si, Ge, P, As, Ar, or Sb. The impurity being Ge provides a distinct boundary between the amorphous and non-amorphous region with the added benefit of increasing accuracy and reliability of the temperature measurement (Col. 3, Lines 1-4).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Nolan Stuessy whose telephone number is (571) 645-5843. The examiner can normally be reached on M-F; 9:00-5:00 (EST).
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/NOLAN GABRIEL STUESSY/Examiner, Art Unit 2812
/DAVIENNE N MONBLEAU/Supervisory Patent Examiner, Art Unit 2812
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