DETAILED ACTION
Notice of Pre-AIA or AIA Status
1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
2. This office action is in response to the Amendment filed on July 20, 2026.
Claims 1, 5, 7, 9, 13, 15, 18, and 22 are amended. Claims 3, 11, and 20 are canceled. No claims are added.
Response to Arguments
3. Applicant’s arguments, see page 11, filed July 20, 2026, with respect to the rejection of claim 1 under 35 USC § 103 have been fully considered and are persuasive. Therefore, the rejection has been withdrawn.
Applicant asserts Claim 1 recites that the voltage of the claimed sense node is pre-charged to a high value and allowed to drop to a lower voltage that corresponds to either a one or a zero and by contrast, Joshi discloses that during READ-0 the sense node is at VDD, and during READ-1 the voltage at the sense node drops. However, for Joshi to read on claim 1, Joshi must disclose that the sense node also drops during READ-0. Joshi contains no such disclosure. For this reason, Applicant believes that Joshi cannot be properly used to teach the limitation of "a pre-charge circuit that is configured to pre-charge the sense node to a predetermined value that is selected to be sufficiently high, such that, after the sense node is pre-charged, a voltage at the sense node falls to a value corresponding to the amplified data signal, the voltage at the sense node falling to the value corresponding to the amplified data signal irrespective of whether the amplified data signal is logic-high or logic-low," as recited by amended claim 1. Examiner agrees and, therefore, the rejections of claims 1, 9, and 15 and their respective dependent claims set forth in the previous office action are withdrawn in light of the amendments.
4. Applicant's arguments filed July 20, 2026 have been fully considered but they are not persuasive.
Applicant submits that because Joshi (US 20230005521 A1) teaches using feedback from bit-line RBL to control the voltage at the sense node and the feedback relies on the sense-current draw of the memory that is being read, then if the address transition is used to control the voltage at the sense node, this will change the principle of operation of Joshi from using "memory sense- current draw" to using "an extra signal (or address-transition signal)," which is not permissible under the rules. (See MPEP § 2143.01(VI).)
However, the modification of Joshi based on the characterization circuit of Pascucci (US 5886945 A) FIG. 2 merely deals with the pre-charge timing (Pascucci FIG. 3) and in no way changes the configuration nor operation of Joshi’s sense amplifier. Pascucci’s modification merely changes the timing at which VDD is passed to Joshi’s sense node SENSE_N (Joshi FIGS. 3-4, ¶[0029]), which in turn pre-charges Joshi’s node RBL to VDD/2 (Joshi ¶[0037-0038]). No change is made to the schematic or operation of Joshi’s sense amplifier. Pascucci further provides motivation for such timing in Col. 2, ll. 12-16, which is sufficient for modifying Joshi (MPEP § 2145(X)(C)).
Applicant further asserts Joshi discloses that the sense node is maintained near VDD during both idle phases and READ-0 operations. However, Joshi as modified by Pascucci would not maintain VDD during the idle phase (Pascucci FIGS. 2-3; PCn may control the timing of the application of Joshi FIG. 1 VB_P and limit the pre-charge timing to when an address transition is detected).
Applicant further asserts the Office Action alleges that the maintenance of the sense node at VDD during READ-0 is analogous to the claimed pre-charging, and the maintenance of the sense node at VDD is data-dependent (i.e., it occurs only when a zero is read). However, Joshi ¶[0029] was cited in the previous office action only to provide the magnitude of the voltage at SENSE_N during pre-charge, which may not be the same as during sensing. ¶[0029] teaches when transitioning from pre-charge to a READ-0, “the transistor will stay in triode mode, SENSE_N (node 18) will be close to VDD.” That is, during READ-0, SENSE_N will remain the same as during pre-charge, which will be “close to VDD.” This makes sense as ¶[0037] discusses pre-charging RBL to VDD/2, which indicates SENSE_N will be something higher than VDD/2 while MP3 is in triode mode and functioning as a pull-up. Therefore, the pre-charge voltage at SENSE_N is not data-dependent because the input data is not evaluated until after pre-charge. What is data-dependent is the operating mode of MP3. During READ-1 (after pre-charge), MP3 changes to saturation mode and the responsibility for maintaining RBL at VDD/2 after pre-charge (during sensing) shifts to MP4.
Specification
4. The disclosure is objected to because of the following informalities.
Regarding ¶[0019], some reference symbols do not match FIG. 1B in the drawings. To correct, Examiner suggests the following.
[0019] The conditioning circuit 120 may include NMOS transistors [[112]] 122 and 124. The drain of transistor 122 may be coupled to the drain of a CMOS transistor [[166]] 163, the source of transistor 122 may be coupled to node [[CH]] C0, and the gate of transistor 122 may be coupled to node FB. The source of transistor 124 may be coupled to node SM, and the gate of transistor 124 may be coupled to the output of inverter 161. The conditioning circuit 120 may be configured to reduce the capacitance on node SN to speed up both the pre-charge and sensing phases. The pre-charge and sensing phases correspond to periods p2 and p3 in FIGS. 2-3.
Appropriate correction is required.
Claim Rejections - 35 USC § 112
5. The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
6. Claims 7 and 15 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claims 7 and 15 recite, “a conditioning circuit that includes a second transistor having…a respective gate, wherein…the respective gate of the second transistor is arranged to receive the feedback signal.” Referencing FIG. 1B, conditioning circuit 120 includes transistors 122 and 124. Of the transistors, only transistor 122 has a gate “arranged to receive the feedback signal.” Therefore, the “second transistor” in the claims must be transistor 122.
Claims 7 and 15 further recite, “a second transistor having a respective first terminal, a respective second terminal, and a respective gate, wherein the respective first terminal of the second transistor is coupled to the respective first terminal of the first transistor and arranged to receive the data signal, the respective second terminal of the second transistor is coupled to a power source.”
The “second terminal” is best understood as the source of transistor 122. The “second terminal” is not physically “coupled to a power source,” as recited in the claims, but may be electrically coupled to VDD under certain operating conditions (i.e., depending upon the state of PRE_EN).
The “first terminal” is best understood as the drain of transistor 122 as it is “arranged to receive the data signal,” under certain operation conditions (i.e., depending on the state of PRE_EN in FIG. 1B). The “first terminal of the second transistor” is not physically “coupled to the respective first terminal of the first transistor” (i.e., the source of transistor 132) as recited in the claims, but may be electrically connected to the respective first terminal of the first transistor under certain operation conditions (i.e., depending on the state of PRE_EN in FIG. 1B).
Because claims 7 and 15 do not accurately describe the physical connections or arrangement of conditioning circuit components in the circuit of FIG. 1B, the meaning of the claims is indefinite.
For the purpose of this action, the limitation, “the respective second terminal of the second transistor is coupled to a power source” shall be interpreted as “the respective second terminal of the second transistor is electrically coupled to a power source.”
Claim Rejections - 35 USC § 102
7. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
8. Claims 7 and 15 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Ogawa, et al (EP 0903752 B1), hereinafter Ogawa.
Regarding independent claim 7, Ogawa teaches in FIG. 11 a read amplifier (353), comprising:
a first transistor (312) having a respective first terminal (coupled to node 320) and a respective second terminal (coupled to node 322), the respective second terminal of the first transistor being coupled to a sense node (node 322), the first transistor being arranged to: (i) receive, on the respective first terminal of the first transistor, a data signal (the present application teaches in ¶[0025] “the term ‘data signal’ may refer to any signal that is generated, at least in part, based on the raw output of the flash array,” and so Ogawa’s “data signal” could refer to node 320 or bit line 303) that is generated at least in part by a memory matrix (301; Abstract teaches “a matrix of nonvolatile memory cells (301)”), and (ii) output, on the sense node, an amplified data signal (¶[0087] teaches “a sense amplifier comprising an MOS transistor 352 connected at the drain thereof to the power line 306, at the source thereof to the node 322 and supplied at the gate thereof with an ATD signal); and
a feedback circuit (315) arranged to generate, based at least in part on the data signal (input node 320 is coupled to the input node of the feedback circuit (gate of 310)), a feedback signal (node 321) that is applied at a respective gate of the first transistor (gate of 312);
a pre-charge circuit (352; ¶[0088] teaches “nodes 320 and 322 are precharged based on the ATD signal”) that is configured to pre-charge the sense node to a predetermined value (FIG. 12A, dashed line during ATD SIGNAL high time)), such that, after the sense node is pre-charged, a voltage at the sense node settles at a value corresponding to the amplified data signal (FIG. 12A, dashed line after ATD SIGNAL high time; ¶[0090] teaches “the time required for the node 322 to take the L level can be shortened…”); and
a conditioning circuit (311, 314) that includes a second transistor (311) having a respective first terminal (coupled to 314), a respective second terminal (coupled to V.sub.cc), and a respective gate (coupled to node 321), wherein the respective first terminal of the second transistor is coupled to the respective first terminal of the first transistor (311 shown coupled to transistor 314) and arranged to receive the data signal (311 coupled to input node 320), the respective second terminal of the second transistor is coupled to a power source (311 shown coupled to V.sub.cc), and the respective gate of the second transistor is arranged to receive the feedback signal (311 gate shown coupled to feedback node 321).
Regarding independent claim 15, Ogawa teaches in FIG. 11 a read amplifier (353), comprising:
a first transistor (312) having a respective first terminal (coupled to node 320) and a respective second terminal (coupled to node 322), the respective second terminal of the first transistor being coupled to a sense node (node 322), the first transistor being arranged to: (i) receive, on the respective first terminal of the first transistor, a data signal (the present application teaches in ¶[0025] “the term ‘data signal’ may refer to any signal that is generated, at least in part, based on the raw output of the flash array,” and so Ogawa’s “data signal” could refer to node 320 or bit line 303) that is generated at least in part by a memory matrix (301; Abstract teaches “a matrix of nonvolatile memory cells (301)”), and (ii) output, on the sense node, an amplified data signal (¶[0087] teaches “a sense amplifier comprising an MOS transistor 352 connected at the drain thereof to the power line 306, at the source thereof to the node 322 and supplied at the gate thereof with an ATD signal); and
a pre-charge circuit (352; ¶[0088] teaches “nodes 320 and 322 are precharged based on the ATD signal”) that is configured to pre-charge the sense node to a predetermined value (FIG. 12A, dashed line during ATD SIGNAL high time)), such that, after the sense node is pre-charged, a voltage at the sense node settles at a value corresponding to the amplified data signal (FIG. 12A, dashed line after ATD SIGNAL high time; ¶[0090] teaches “the time required for the node 322 to take the L level can be shortened…”),
a conditioning circuit (311, 314) that includes a second transistor (311) having a respective first terminal (coupled to 314), a respective second terminal (coupled to V.sub.cc), and a respective gate (coupled to node 321), wherein the respective first terminal of the second transistor is coupled to the respective first terminal of the first transistor (311 shown coupled to transistor 314) and arranged to receive the data signal (311 coupled to input node 320), the respective second terminal of the second transistor is coupled to a power source (311 shown coupled to V.sub.cc), and the respective gate of the second transistor is arranged to receive a feedback signal (311 gate shown coupled to feedback node 321) that is also applied at a gate of the first transistor (312 gate shown coupled to feedback node 321), the feedback signal being generated by a feedback circuit based, at least in part, on the data signal (signal at feedback node 321 generated by feedback circuit 315 based on signal at input node 320).
Allowable Subject Matter
9. Claims 1-2, 4-6, 8-10, 12-14, 16-19, and 21-24 are allowed.
10. The following is a statement of reasons for the indication of allowable subject matter.
Regarding claim 1, the prior art made of record and considered pertinent to the applicant’s disclosure does not teach or suggest the claimed limitation of a pre-charge circuit that is configured to pre-charge the sense node to a predetermined value that is selected to be sufficiently high, such that, after the sense node is pre-charged, a voltage at the sense node falls to a value corresponding to the amplified data signal, the voltage at the sense node falling to the value corresponding to the amplified data signal irrespective of whether the amplified data signal is logic-high or logic-low. Claims 2, 4-6, and 8 depend on claim 1.
Regarding claim 9, the prior art made of record and considered pertinent to the applicant’s disclosure does not teach or suggest the claimed limitation of a pre-charge circuit that is configured to pre-charge the sense node to a predetermined value that is selected to be sufficiently high, such that, after the sense node is pre-charged, a voltage at the sense node falls to a value corresponding to the amplified data signal, the voltage at the sense node falling to the value corresponding to the amplified data signal irrespective of whether the amplified data signal is logic-high or logic-low. Claims 10, 12-14, and 16-17 depend on claim 9.
Regarding claim 18, the prior art made of record and considered pertinent to the applicant’s disclosure does not teach or suggest the claimed limitation of a pre-charge circuit that is configured to pre-charge the sense node to a predetermined value that is selected to be sufficiently high, such that, after the sense node is pre-charged, a voltage at the sense node falls to a value corresponding to the amplified data signal, the voltage at the sense node falling to the value corresponding to the amplified data signal irrespective of whether the amplified data signal is logic-high or logic-low. Claims 19 and 21-24 depend on claim 18.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to BRADLEY COON whose telephone number is (571)270-0740. The examiner can normally be reached M-F 8am-5pm (Eastern).
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/B.S.C./Examiner, Art Unit 2827
/AMIR ZARABIAN/Supervisory Patent Examiner, Art Unit 2827
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