DETAILED ACTION
Notice of Pre-AIA or AIA Status
1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
2. This office action is in response to the Amendment filed on March 16, 2026.
Claims 1-2, 7-10, and 15-18 are amended. Claims 3, 11, and 20 are canceled. No claims are added.
Applicant’s amendments to the specification submitted on March 16, 2026 are acknowledged and objections to the specification are withdrawn.
Applicant’s amendments to claims 7 and 15 overcome the 112(b) rejection set forth in the previous office action and therefore the 112(b) rejections of claims 7 and 15 are withdrawn.
Response to Arguments
3. Applicant’s arguments, see pages 8-9, filed March 16, 2026, with respect to the rejections of independent claims 1, 9, and 18 under 35 USC § 102 and 35 USC § 103 have been fully considered and are persuasive. Therefore, the rejection has been withdrawn.
Applicant asserts that by amending the limitations of claim 3, which have been amended to overcome the 112(b) rejections set forth in the previous Office Action, into the independent claims, the independent claims overcome their respective rejections under 35 USC § 102 and 35 USC § 103. Examiner notes the prior art cited in the previous Office Action does not teach all of the limitations of the amended independent claims. However, upon further consideration, a new ground(s) of rejection is made in view of Pascucci (US 5886945 A).
Specification
4. The disclosure is objected to because of the following informalities.
Regarding ¶[0019], some reference symbols do not match FIG. 1B in the drawings. To correct, Examiners suggests the following.
[0019] The conditioning circuit 120 may include NMOS transistors [[112]] 122 and 124. The drain of transistor 122 may be coupled to the drain of a CMOS transistor [[166]] 163, the source of transistor 122 may be coupled to node [[CH]] C0, and the gate of transistor 122 may be coupled to node FB. The source of transistor 124 may be coupled to node SM, and the gate of transistor 124 may be coupled to the output of inverter 161. The conditioning circuit 120 may be configured to reduce the capacitance on node SN to speed up both the pre-charge and sensing phases. The pre-charge and sensing phases correspond to periods p2 and p3 in FIGS. 2-3.
Appropriate correction is required.
Claim Rejections - 35 USC § 112
5. The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
6. Claims 7 and 15 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claims 7 and 15 recite, “a conditioning circuit that includes a second transistor having…a respective gate, wherein…the respective gate of the second transistor is arranged to receive the feedback signal.” Referencing FIG. 1B, conditioning circuit 120 includes transistors 122 and 124. Of the transistors, only transistor 122 has a gate “arranged to receive the feedback signal.” Therefore, the “second transistor” in the claims must be transistor 122.
Claims 7 and 15 further recite, “a second transistor having a respective first terminal, a respective second terminal, and a respective gate, wherein the respective first terminal of the second transistor is coupled to the respective first terminal of the first transistor and arranged to receive the data signal, the respective second terminal of the second transistor is coupled to a power source.”
The “second terminal” is best understood as the source of transistor 122. The “second terminal” is not physically “coupled to a power source,” as recited in the claims, but may be electrically coupled to VDD under certain operating conditions (i.e., depending upon the state of PRE_EN).
The “first terminal” is best understood as the drain of transistor 122 as it is “arranged to receive the data signal,” but only under certain operation conditions (i.e., depending on the state of PRE_EN in FIG. 1B). The “first terminal of the second transistor” is not physically “coupled to the respective first terminal of the first transistor” (i.e., the source of transistor 132) as recited in the claims, but may be electrically connected to the respective first terminal of the first transistor under certain operation conditions (i.e., depending on the state of PRE_EN in FIG. 1B).
Because claims 7 and 15 do not accurately describe the physical connections or arrangement of components in the circuit of FIG. 1B, the meaning of the claims is indefinite. For the purpose of this action, they shall be interpreted as electrical connections under certain operating conditions as follows.
“…a conditioning circuit that includes a second transistor having a respective first terminal, a respective second terminal, and a respective gate, wherein the respective gate of the second transistor is arranged to receive the feedback signal, and, in response to the pulse in the signal that is generated by the address transition decoder, the respective first terminal of the second transistor is electrically coupled to the respective first terminal of the first transistor and arranged to receive the data signal, and the respective second terminal of the second transistor is electrically coupled to a power source
Claim Rejections - 35 USC § 103
7. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
8. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
9. The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
10. Claims 1-2, 4, 6, 9-10, 12, 14, and 17 are rejected under 35 U.S.C. 103 as being unpatentable over Joshi, et al (US 20230005521 A1), hereinafter Joshi, in view of Pascucci (US 5886945 A).
Regarding independent claim 1, Joshi teaches in FIG. 1 a read amplifier (10), comprising:
a first transistor (MN3) having a respective first terminal (source coupled to node 16), and a respective second terminal (drain coupled to node 18; ¶[0004]), the respective second terminal of the first transistor being coupled to a sense node (18, SENSE_N), the first transistor being arranged to: (i) receive, on the respective first terminal of the first transistor, a data signal that is generated at least in part by a memory matrix (18; the present application teaches in ¶[0025] “the term ‘data signal’ may refer to any signal that is generated, at least in part, based on the raw output of the flash array,” and so Joshi’s “data signal” could refer to node 16, 18, VOUT, etc.), and (ii) output, on the sense node, an amplified data signal (signal at 18, SENSE_N); and
a feedback circuit (MP1, MP2, MN1, MN2, MN3) arranged to generate, based at least in part on the data signal (input node 16 is coupled to the input node of the feedback circuit (gates of MP2 and MN1)), a feedback signal (coupled to node FB) that is applied at a gate of the first transistor (gate of MN3); and
a pre-charge circuit (MP3) that is configured to pre-charge the sense node to a predetermined value (¶[0029], “close to VDD”), such that, after the sense node is pre-charged, a voltage at the sense node settles at a value corresponding to the amplified data signal (¶[0004], [0029]).
Joshi does not teach the pre-charge circuit is configured to pre-charge the sense node in response to a pulse in a signal that is generated by an address transition decoder, the pulse signals a transition in the address signal, the address signal identifies a cell in the memory matrix whose value is desired to be read, and the data signal indicates the value of the identified cell.
Pascucci teaches a pre-charge signal (FIGS. 1-3, PCn; Col. 2, ll. 14-16) in response to a pulse in a signal (FIG. 3, ATD; FIG. 2 shows pre-charge signal PCn is in response to ATD; Col. 3, ll. 29-31) that is generated by an address transition decoder (FIG. 2, Logic Stage 5), the pulse signals a transition in the address signal (Col. 2, ll. 12-13 teach signal ATD indicates an address transition at the start of a read step), the address signal identifies a cell in the memory matrix (FIG. 1, cell 4 in Memory Array 3) whose value is desired to be read (Col. 2, ll. 12-13 teach signal ATD indicates an address transition at the start of a read step), and the data signal indicates the value of the identified cell (Col. 2, ll. 30-33 teach “an output connected to pad 10, so as to receive the data read by memory array 3 and supply it externally of device 1 to pad 10”; see also Col. 1, ll. 14-15 (“the data item in a given location is evaluated”) and Claim 7).
Therefore, Joshi as modified by Pascucci teaches the pre-charge circuit is configured to pre-charge the sense node (Joshi) in response to a pulse in a signal that is generated by an address transition decoder, the pulse signals a transition in the address signal, the address signal identifies a cell in the memory matrix whose value is desired to be read, and the data signal indicates the value of the identified cell (Pascucci).
Regarding independent claim 9, Joshi teaches in FIG. 1 a read amplifier (10), comprising:
a transistor (MN3) having a first terminal (source coupled to node 16) and a second terminal (drain coupled to node 18; ¶[0004]), the second terminal being coupled to a sense node (18, SENSE_N), the transistor being arranged to: (i) receive, on the second terminal, a data signal that is generated at least in part by a memory matrix (18; the present application teaches in ¶[0025] “the term ‘data signal’ may refer to any signal that is generated, at least in part, based on the raw output of the flash array,” and so Joshi’s “data signal” could refer to node 16, 18, VOUT, etc.), and (ii) output, on the sense node, an amplified data signal (signal at 18, SENSE_N); and
a pre-charge circuit (MP3) that is configured to pre-charge the sense node to a predetermined value (¶[0029], “close to VDD”), such that, after the sense node is pre-charged, a voltage at the sense node settles at a value corresponding to the amplified data signal (¶[0004], [0029]).
Joshi does not teach the pre-charge circuit is configured to pre-charge the sense node in response to a pulse in a signal that is generated by an address transition decoder, the pulse signals a transition in the address signal, the address signal identifies a cell in the memory matrix whose value is desired to be read, and the data signal indicates the value of the identified cell.
Pascucci teaches a pre-charge signal (FIGS. 1-3, PCn; Col. 2, ll. 14-16) in response to a pulse in a signal (FIG. 3, ATD; FIG. 2 shows pre-charge signal PCn is in response to ATD; Col. 3, ll. 29-31) that is generated by an address transition decoder (FIG. 2, Logic Stage 5), the pulse signals a transition in the address signal (Col. 2, ll. 12-13 teach signal ATD indicates an address transition at the start of a read step), the address signal identifies a cell in the memory matrix (FIG. 1, cell 4 in Memory Array 3) whose value is desired to be read (Col. 2, ll. 12-13 teach signal ATD indicates an address transition at the start of a read step), and the data signal indicates the value of the identified cell (Col. 2, ll. 30-33 teach “an output connected to pad 10, so as to receive the data read by memory array 3 and supply it externally of device 1 to pad 10”; see also Col. 1, ll. 14-15 (“the data item in a given location is evaluated”) and Claim 7).
Therefore, Joshi as modified by Pascucci teaches the pre-charge circuit is configured to pre-charge the sense node (Joshi) in response to a pulse in a signal that is generated by an address transition decoder, the pulse signals a transition in the address signal, the address signal identifies a cell in the memory matrix whose value is desired to be read, and the data signal indicates the value of the identified cell (Pascucci).
Regarding claims 1 and 9, it would have been obvious to one of ordinary skill of the art before the time of the effective filing date of the invention to incorporate the teachings of Pascucci into the method of Joshi to include an address transition decoder (Joshi FIG. 1, Logic Stage 5 generating address transition detect signal ATD). The ordinary artisan would have been motivated to modify Joshi in the above manner for the purpose of indicating an address transition at the start of a read step and generating a pre-charge signal (Pascucci, Col. 2, ll. 12-16).
Regarding claim 2, Joshi as modified by Pascucci teaches the limitations of claim 1.
Joshi further teaches the predetermined value includes a logic-high value (¶[0029], “close to VDD”), the respective first terminal of the first transistor includes a source of the first transistor, and the respective second terminal of the first transistor includes a drain of the first transistor (FIG. 1, MN3 is the “third NMOS transistor” of ¶[0004], where pinning is identified).
Regarding claim 4, Joshi as modified by Pascucci teaches the limitations of claim 1.
Joshi further teaches pre-charging the sense node increases, on at least some occasions, a speed at which the voltage at the sense node settles at the value corresponding to the amplified data signal (¶[0029], because the sense node is “close to VDD” both before sensing and in READ-0 operations, “settling” will be faster in the READ-0 “occasions” because no voltage transition is necessary).
Regarding claim 6, Joshi as modified by Pascucci teaches the limitations of claim 1.
Joshi further teaches the pre-charge circuit is configured to pre-charge the sense node during a period in which the data signal is rising to a limit voltage (FIG. 1, when VB_P enables pre-charge transistor MP3, the sense node rises to “close to VDD” (¶[0029]) as limited by the supply voltage VDD on the drain of MP3).
Regarding claim 10, Joshi as modified by Pascucci teaches the limitations of claim 9.
Joshi further teaches the predetermined value includes a logic-high value (¶[0029], “close to VDD”), the first terminal includes a source of the transistor, and the second terminal includes a drain of the first transistor (FIG. 1, MN3 is the “third NMOS transistor” of ¶[0004], where pinning is identified).
Regarding claim 12, Joshi as modified by Pascucci teaches the limitations of claim 9.
Joshi further teaches pre-charging the sense node increases, on at least some occasions, a speed at which the voltage at the sense node settles at the value corresponding to the amplified data signal (¶[0029], because the sense node is “close to VDD” both before sensing and in READ-0 operations, “settling” will be faster in the READ-0 “occasions” because no voltage transition is necessary).
Regarding claim 14, Joshi as modified by Pascucci teaches the limitations of claim 9.
Joshi further teaches the pre-charge circuit is configured to pre-charge the sense node during a period in which the data signal is rising to a limit voltage (FIG. 1, when VB_P enables pre-charge transistor MP3, the sense node rises to “close to VDD” (¶[0029]) as limited by the supply voltage VDD on the drain of MP3).
Regarding claim 17, Joshi as modified by Pascucci teaches the limitations of claim 9.
Joshi further teaches in FIG. 1 a feedback circuit (MP1, MP2, MN1, MN2, MN3) arranged to generate, based at least in part on the data signal (input node 16 is coupled to the input node of the feedback circuit (gates of MP2 and MN1)), a feedback signal (coupled to node FB) that is applied at a respective gate of the first transistor (gate of MN3).
11. Claims 5, 8, 13, and 16 are rejected under 35 U.S.C. 103 as being unpatentable over Joshi, et al (US 20230005521 A1), hereinafter Joshi, in view of Pascucci (US 5886945 A), and further in view of Vimercati, et al (US 20050030809 A1), hereinafter Vimercati.
Regarding claim 5, Joshi as modified by Pascucci teaches the limitations of claim 1.
Joshi does not teach the output node is coupled to a latch, and pre-charging the sense node increases, on at least some occasions, a speed at which the value corresponding to the amplified data signal is stored in the latch.
Vimercati teaches the output node is coupled to a latch (FIG. 1, SEN is coupled to the input of Latch 123).
Joshi as modified by Pascucci and Vimercati further teaches pre-charging the sense node increases, on at least some occasions, a speed at which the value corresponding to the amplified data signal is stored in the latch (¶[0029], because the sense node is “close to VDD” both before sensing and in READ-0 operations, “settling” will be faster in the READ-0 “occasions” because no voltage transition is necessary and the data is ready to be stored faster than in READ-1 “occasions”).
Regarding claim 13, Joshi as modified by Pascucci teaches the limitations of claim 9.
Joshi does not teach the output node is coupled to a latch, and pre-charging the sense node increases, on at least some occasions, a speed at which the value corresponding to the amplified data signal is stored in the latch.
Vimercati teaches the output node is coupled to a latch (FIG. 1, SEN is coupled to the input of Latch 123).
Joshi as modified by Pascucci and Vimercati further teaches pre-charging the sense node increases, on at least some occasions, a speed at which the value corresponding to the amplified data signal is stored in the latch (¶[0029], because the sense node is “close to VDD” both before sensing and in READ-0 operations, “settling” will be faster in the READ-0 “occasions” because no voltage transition is necessary and the data is ready to be stored faster than in READ-1 “occasions”).
Regarding claims 5 and 13, it would have been obvious to one of ordinary skill of the art before the time of the effective filing date of the invention to incorporate the teachings of Vimercati into the method of Joshi to include a buffer memory (latch) at the output of the sense amplifier. The ordinary artisan would have been motivated to modify Joshi in the above manner for the purpose of provides a digital signal whose logic state is indicative of the datum stored in the memory cell selected for reading (Vimercati, ¶[0053]).
Regarding claim 8, Joshi as modified by Pascucci teaches the limitations of claim 1.
Joshi further teaches the first transistor is part of an amplification circuit (referencing FIG. 1, ¶[0028] teaches “transistors MN1, MN2, MN3, MP1, MP2 and MP4 comprise a feedback amplifier circuit which operates as a current-voltage controlled negative feedback system,” in which MN3 is “the transistor” of the claim).
Pascucci further teaches the memory matrix includes a memory array (FIG. 1, 3; Col. 2, ll. 2-3).
Joshi does not teach the memory matrix includes a flash array.
Vimercati teaches the memory matrix includes a flash array (¶[0036]).
Regarding claim 16, Joshi as modified by Pascucci teaches the limitations of claim 9.
Joshi further teaches the first transistor is part of an amplification circuit (referencing FIG. 1, ¶[0028] teaches “transistors MN1, MN2, MN3, MP1, MP2 and MP4 comprise a feedback amplifier circuit which operates as a current-voltage controlled negative feedback system,” in which MN3 is “the transistor” of the claim).
Pascucci further teaches the memory matrix includes a memory array (FIG. 1, 3; Col. 2, ll. 2-3).
Joshi does not teach the memory matrix includes a flash array.
Vimercati teaches the memory matrix includes a flash array (¶[0036]).
Regarding claims 8 and 16, because both Joshi and Vimercati teach single-ended sense amplifiers (Joshi, FIG. 1, input node 16 and Abstract; Vimercati, FIG. 1, 111) with inverting buffer output stages (Joshi, FIG. 1, MP9/MN10, ¶[0029]; Vimercati, FIG. 1, P5/N2, ¶[0051]) in memory cell reading applications (Joshi, ¶[0004]; Vimercati, ¶[0053]), it would have been obvious to one of ordinary skill in the art at the time of the invention to substitute the sense amplifier of Joshi with the sense amplifier of Vimercati to yield predictable results with a flash array. See MPEP § 2143(I)(B).
12. Claims 18-19 and 21-24 are rejected under 35 U.S.C. 103 as being unpatentable over Joshi, et al (US 20230005521 A1), hereinafter Joshi, in view of Vimercati, et al (US 20050030809 A1), hereinafter Vimercati, and further in view of Pascucci (US 5886945 A).
Regarding independent claim 18, Joshi teaches a system (FIG. 7), comprising:
a flash memory (¶[0068]);
a transistor (FIG. 1, 10) having a first terminal (source coupled to node 16) and a second terminal (drain coupled to node 18; ¶[0004]), the second terminal being coupled to a sense node (FIG. 1, 18, SENSE_N), the transistor being arranged to: (i) receive, on the second terminal, a data signal that is generated at least in part by the flash memory (FIG. 1, 18; the present application teaches in ¶[0025] “the term ‘data signal’ may refer to any signal that is generated, at least in part, based on the raw output of the flash array,” and so Joshi’s “data signal” could refer to node 16, 18, VOUT, etc.), and (ii) output, on the sense node, an amplified data signal (FIG. 1, signal at 18, SENSE_N);
a pre-charge circuit (FIG. 1, MP3) that is configured to pre-charge the sense node to a predetermined value (¶[0029], “close to VDD”), such that, after the sense node is pre-charged, a voltage at the sense node settles at a value corresponding to the amplified data signal (¶[0004], [0029]).
Joshi does not teach a buffer memory having a data input terminal that is coupled to the sense node, the buffer memory being configured to buffer the amplified data signal.
Vimercati teaches a buffer memory (FIG. 1, Latch 123) having a data input terminal (FIG. 1, input signal to left side of latch symbol 123) that is coupled to the sense node (FIG. 1, SEN), the buffer memory being configured to buffer the amplified data signal (¶[0053]; see also FIG. 2A and ¶ [0064-0065]).
Joshi does not teach the sense amplifier of Joshi, FIG. 1, is used to sense data from the flash memory of the system of Joshi, FIG. 7. Vimercati teaches a system containing flash memories utilizing the sensing circuit of Vimercati FIG. 1 (¶[0114]). Therefore, Joshi as modified by Vimercati teaches a system containing flash memories utilizing the sensing circuit of Joshi as modified by Vimercati.
Joshi does not teach the pre-charge circuit is configured to pre-charge the sense node in response to a pulse in a signal that is generated by an address transition decoder, the pulse signals a transition in the address signal, the address signal identifies a cell in the memory matrix whose value is desired to be read, and the data signal indicates the value of the identified cell.
Pascucci teaches a pre-charge signal (FIGS. 1-3, PCn; Col. 2, ll. 14-16) in response to a pulse in a signal (FIG. 3, ATD; FIG. 2 shows pre-charge signal PCn is in response to ATD; Col. 3, ll. 29-31) that is generated by an address transition decoder (FIG. 2, Logic Stage 5), the pulse signals a transition in the address signal (Col. 2, ll. 12-13 teach signal ATD indicates an address transition at the start of a read step), the address signal identifies a cell in the memory matrix (FIG. 1, cell 4 in Memory Array 3) whose value is desired to be read (Col. 2, ll. 12-13 teach signal ATD indicates an address transition at the start of a read step), and the data signal indicates the value of the identified cell (Col. 2, ll. 30-33 teach “an output connected to pad 10, so as to receive the data read by memory array 3 and supply it externally of device 1 to pad 10”; see also Col. 1, ll. 14-15 (“the data item in a given location is evaluated”) and Claim 7).
Therefore, Joshi as modified by Vimercati and Pascucci teaches the pre-charge circuit is configured to pre-charge the sense node (Joshi) in response to a pulse in a signal that is generated by an address transition decoder, the pulse signals a transition in the address signal, the address signal identifies a cell in the memory matrix whose value is desired to be read, and the data signal indicates the value of the identified cell (Pascucci).
It would have been obvious to one of ordinary skill of the art before the time of the effective filing date of the invention to incorporate the teachings of Vimercati into the method of Joshi to include a buffer memory (latch) at the output of the sense amplifier. The ordinary artisan would have been motivated to modify Joshi in the above manner for the purpose of provides a digital signal whose logic state is indicative of the datum stored in the memory cell selected for reading (Vimercati, ¶[0053]).
It would have been obvious to one of ordinary skill of the art before the time of the effective filing date of the invention to incorporate the teachings of Pascucci into the method of Joshi to include an address transition decoder (Joshi FIG. 1, Logic Stage 5 generating address transition detect signal ATD). The ordinary artisan would have been motivated to modify Joshi in the above manner for the purpose of indicating an address transition at the start of a read step and generating a pre-charge signal (Pascucci, Col. 2, ll. 12-16).
Regarding claim 19, Joshi as modified by Vimercati and Pascucci teaches the limitations of claim 18.
Joshi further teaches the predetermined value includes a logic-high value (¶[0029], “close to VDD”), the first terminal includes a source of the transistor, and the second terminal includes a drain of the transistor (FIG. 1, MN3 is the “third NMOS transistor” of ¶[0004], where pinning is identified).
Regarding claim 21, Joshi as modified by Vimercati and Pascucci teaches the limitations of claim 18.
Joshi further teaches pre-charging the sense node increases, on at least some occasions, a speed at which the voltage at the sense node settles at the value corresponding to the amplified data signal (¶[0029], because the sense node is “close to VDD” both before sensing and in READ-0 operations, “settling” will be faster in the READ-0 “occasions” because no voltage transition is necessary).
Regarding claim 22, Joshi as modified by Vimercati and Pascucci teaches the limitations of claim 18.
Vimercati further teaches the output node is coupled to a latch (FIG. 1, SEN is coupled to the input of Latch 123).
Joshi as modified by Vimercati further teaches pre-charging the sense node increases, on at least some occasions, a speed at which the value corresponding to the amplified data signal is stored in the latch (¶[0029], because the sense node is “close to VDD” both before sensing and in READ-0 operations, “settling” will be faster in the READ-0 “occasions” because no voltage transition is necessary and the data is ready to be stored faster than in READ-1 “occasions”).
Regarding claim 23, Joshi as modified by Vimercati and Pascucci teaches the limitations of claim 18.
Vimercati further teaches the buffer memory includes a latch (FIG. 1, Latch 123).
Regarding claim 24, Joshi as modified by Vimercati and Pascucci teaches the limitations of claim 18.
Joshi further teaches in FIG. 1 a feedback circuit (MP1, MP2, MN1, MN2, MN3) arranged to generate, based at least in part on the data signal (input node 16 is coupled to the input node of the feedback circuit (gates of MP2 and MN1)), a feedback signal (coupled to note FB) that is applied at a gate of the transistor (gate of MN3).
Allowable Subject Matter
13. Claims 7 and 15 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims, and if rewritten to overcome the rejection(s) under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), 2nd paragraph, set forth in this Office action.
14. The following is a statement of reasons for the indication of allowable subject matter.
Regarding claims 7 and 15, the prior art made of record and considered pertinent to the applicant’s disclosure does not teach the claimed limitation of a conditioning circuit that includes a second transistor having a respective first terminal, a respective second terminal, and a respective gate, wherein the respective first terminal of the second transistor is coupled to the respective first terminal of the first transistor and arranged to receive the data signal, the respective second terminal of the second transistor is coupled to a power source, and the respective gate of the second transistor is arranged to receive the feedback signal.
Citation of Relevant Art
15. The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Chang, et al (US 6255900 B1) teaches an Address Transition Detection Circuit (FIG. 2, 200) generating an address transition pulse (FIG. 2, ATD1ST) and pre-charge circuits (FIG. 2, 215, 216) responsive to the address transition pulse.
Brigati (US 6104644 A) teaches pre-charging begins when an address transition detector detects an address transition to address the word line to be selected.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/B.S.C./Examiner, Art Unit 2827
/AMIR ZARABIAN/Supervisory Patent Examiner, Art Unit 2827
Prosecution Insights