Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1, 3-5, and 8-15 are rejected under 35 U.S.C. 103 as being unpatentable over Ryu et al. (US 20200168550 A1) in view of Kim et al. (US 20240347434 A1).
Regarding claim 1, FIG. 2A and FIG. 2B of Ryu et al. teach a semiconductor package (20; FIG. 2A; FIG. 2B; paragraph 0054) comprising:
a package substrate (paragraph 0020) having a first region (AR1; FIG. 2B; paragraph 0060) and a second region (AR2; FIG. 2B; paragraph 0061) that is adjacent to the first region;
first connection pads (241; FIG. 2B; paragraph 0060) disposed on the first region of the package substrate, wherein each of the first connection pads has a first height;
second connection pads (250; FIG. 2A; paragraph 0104) disposed on the second region of the package substrate, wherein each of the second connection pads has a second height that is lower than the first height;
a semiconductor chip (310; FIG. 1; paragraph 0056) including first chip pads (313; FIG. 2A; paragraph 0035), second chip pads (313; FIG. 2A; paragraph 0035), and a, wherein the first chip pads are disposed in the first region, wherein the second chip pads are disposed in the second region.
first bump structures (315; FIG. 2A; paragraph 0040) wherein the first bump structures are respectively connected to the first connection pads; and
second bump structures (260; FIG. 2A; paragraph 0104) wherein the second bump structures are respectively connected to the second connection pads.
Ryu et al. does not teach a protective insulating layer, the protective insulating layer being disposed on the second chip pads, the first bump structures being disposed on the first chip pads, and the second bump structures being disposed on the protective insulating layer.
FIG. 1 of Kim et al. teaches a first insulating layer (132; FIG. 21; paragraph 0048) on a FIRST chip pad (102; FIG. 1; paragraph 0048) with a first conductive bump (120; FIG. 1; paragraph 0048) on the chip pad and a second conductive bump (150; FIG. 1; paragraph 0048) on the insulating layer.
Ryu et al. and Kim et al. are both analogous to the claimed invention in that they involve semiconductor devices with chip pads and bumps. Therefore, it would have been obvious for a person with ordinary skill in the art before the effective filing date of the claimed invention to have modified Ryu et al. to have a protective insulating layer, the protective insulating layer being disposed on the second chip pads, the first bump structures being disposed on the first chip pads, and the second bump structures being disposed on the protective insulating layer. These are known aspects of the structure (paragraph 0048).
Regarding claim 3, the combination of Ryu et al. in view of Kim et al. teach the semiconductor package of claim 1. FIG. 2B of Ryu et al. further teaches the package wherein
the first region (AR1; FIG. 2B; paragraph 0060) includes a central portion of the package substrate, and
the second region (AR2; FIG. 2B; paragraph 0061) includes an external surface of the package substrate, and surrounds the first region.
Regarding claim 4, the combination of Ryu et al. in view of Kim et al. teach the semiconductor package of claim 1. FIG. 2A of Ryu et al. further teaches the package wherein the first bump structures (315; FIG. 2A; paragraph 0040) have a height that is greater than a height of the second bump structures (260; FIG. 2A; paragraph 0104) (in this case, height meaning on a higher elevation).
Regarding claim 5, the combination of Ryu et al. in view of Kim et al. teach the semiconductor package of claim 1. FIG. 2A of Ryu et al. further teaches the package wherein the first bump structures (315; FIG. 2A; paragraph 0036) electrically connect the semiconductor chip (310; FIG. 2A; paragraph 0056) and the package substrate (paragraph 0020) to each other.
Regarding claim 8, the combination of Ryu et al. in view of Kim et al. teach the semiconductor package of claim 1. FIG. 2A of Ryu et al. further teaches the package further comprising: external connection conductors (260; FIG. 2A; paragraph 0051) disposed on a lower surface of the package substrate (paragraph 0020).
Regarding claim 9, the combination of Ryu et al. in view of Kim et al. teach the semiconductor package of claim 1. Ryu et al. does not teach the package wherein the first height is about twice the second height. However, the ordinary artisan would have recognized the heights to be a result effective variable affecting the placement and usage of the connecting pads (paragraph 0104). Thus, it would have been obvious to set the silicone oil composition within the claimed range, since optimum or workable ranges of such variables are discoverable through routine experimentation. see MPEP 2144.05 II.B.
Regarding claim 10, the combination of Ryu et al. in view of Kim et al. teach the semiconductor package of claim 9. Ryu et al. does not teach the package wherein
the first height is about 14 µm, and
the second height is about 7 µm.
However, the ordinary artisan would have recognized the heights to be a result effective variable affecting the placement and usage of the connecting pads (paragraph 0104). Thus, it would have been obvious to set the silicone oil composition within the claimed range, since optimum or workable ranges of such variables are discoverable through routine experimentation. see MPEP 2144.05 II.B.
Regarding claim 11, the combination of Ryu et al. in view of Kim et al. teach the semiconductor package of claim 1. FIG. 2A of Ryu et al. further teaches the package wherein each of the first (241; FIG. 2A; paragraph 0059) and second connection pads (250; FIG. 2A; paragraph 0104) include copper (Cu) (paragraph 0059).
Regarding claim 12, the combination of Ryu et al. in view of Kim et al. teach the semiconductor package of claim 1. FIG. 2A of Ryu et al. further teaches the package wherein the first (241; FIG. 2A; paragraph 0060) and second connection pads (250; FIG. 2A; paragraph 0104) have a tapered shape.
Regarding claim 13, FIG. 2A and FIG. 2B of Ryu et al. teaches a semiconductor package comprising:
a package substrate (paragraph 0020);
first (241; FIG. 2B; paragraph 0060) and second connection pads (250; FIG. 2A; paragraph 0104) disposed on the package substrate and spaced apart from each other;
bump structures (315; FIG. 2A; paragraph 0040) in contact with at least one of the first or second connection pads;
and a semiconductor chip (310; FIG. 2A; paragraph 0056) disposed on the bump structures, the, which overlap the second connection pads.
wherein upper surfaces of the first connection pads are positioned on a level higher than that of upper surfaces of the second connection pads (FIG. 2A).
Ryu et al. does not teach the package wherein the semiconductor chip includes a protective insulating layer disposed on bump structures.
FIG. 1 of Kim et al. teaches a second insulating layer (134; FIG 1; paragraph 0048) over a first conductive bump (120; FIG. 1; paragraph 0048).
Ryu et al. and Kim et al. are both analogous to the claimed invention in that they involve semiconductor devices with chip pads and bumps. Therefore, it would have been obvious for a person with ordinary skill in the art before the effective filing date of the claimed invention to have modified Ryu et al. to have a protective insulating layer disposed on bump structures. These are known aspects of the structure (paragraph 0048).
Regarding claim 14, the combination of Ryu et al. in view of Kim et al. teach the semiconductor package of claim 13. FIG. 2A of Ryu et al. further teaches the package wherein upper surfaces of the bump structures (315; FIG. 2A; paragraph 0040), which contact the first connection pads (241; FIG. 2B; paragraph 0060), are positioned on a level higher than that of upper surfaces of the bump structures (260; FIG. 2A; paragraph 000104, which contact the second connection pads (250; FIG. 2A; paragraph 0104).
Regarding claim 15, the combination of Ryu et al. in view of Kim et al. teach the semiconductor package of claim 13. FIG. 2A of Ryu et al. further teaches the package wherein the bump structures (315; FIG. 2A; paragraph 0040) contact the first connection pads (241; FIG. 2B; paragraph 0060). Ryu et al. does not teach the package wherein upper surfaces of the bump structures are positioned on a level the same as that of an upper surface of the protective insulating layer.
FIG. 1 of Kim et al. teaches the upper surface of a first conductive bump (120; FIG. 1; paragraph 0048) is the same level as the upper surface of a first insulating layer (132; FIG. 1; paragraph 0048).
It would have been obvious for a person with ordinary skill in the art before the effective filing date of the claimed invention to have modified Ryu et al. to have upper surfaces of the bump structures are positioned on a level the same as that of an upper surface of the protective insulating layer. These is a known way that these devices are constructed (paragraph 0048).
Claim 6 is rejected under 35 U.S.C. 103 as being unpatentable over Ryu et al. in view of Kim et al. and further in view of Kim (US 20190181067 A1).
Regarding claim 6, the combination of Ryu et al. in view of Kim et al. teach the semiconductor package of claim 1. Neither Ryu et al. nor Kim et al. teach the package wherein
each of the first and second bump structures has a solder portion and a pillar portion, wherein the solder portion is in contact with at least one of the first or second connection pads, and
wherein the pillar portion is disposed on the solder portion, and the pillar portions of the first and second bump structures have the same height as each other.
FIG. 1 and FIG. 9 of Kim teaches chip bump structures (200; FIG. 1; paragraph 0021) including a first conductive pattern (210; FIG. 1; paragraph 0021), a second conductive pattern (220; FIG. 1; paragraph 0021) and a first solder ball (230; FIG. 1; paragraph 0021), with the patterns on top of the solders if rotated in the final structure (FIG. 9) and the solders connected to second connection pads (332; FIG. 9; paragraph 0063) and the heights of the first and second conductive patterns being the same throughout.
Ryu et al., Kim et al., and Kim are all analogous to the claimed invention in that they involve semiconductor devices with chip pads and bumps. Therefore, it would have been obvious for a person with ordinary skill in the art before the effective filing date of the claimed invention to have modified Ryu et al. to have the semiconductor bumps with the aforementioned shape. This shape allows for the bump to be attached to a connection pad (paragraph 0070).
Allowable Subject Matter
Claims 2, 7, 16, and 17 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Regarding claim 2, the combination of Ryu et al. in view of Kim et al. teach the semiconductor package of claim 1. Neither Ryu et al. nor Kim et al. teach the package wherein upper surfaces of the second connection pads have a concave shape protruding toward the package substrate. None of the located prior art teaches this limitation. Therefore, it would be improper in hindsight to modify Ryu et al. so upper surfaces of the second connection pads have a concave shape protruding toward the package substrate.
Regarding claim 7, the combination of Ryu et al. in view of Kim et al. teach the semiconductor package of claim 1. Neither Ryu et al. nor Kim et al. teach the package wherein
the protective insulating layer has a third height, and
the second height is substantially equal to a difference between the first height and the third height.
None of the located prior art teaches this limitation. Therefore, it would be improper in hindsight to modify Ryu et al. so the protective insulating layer has a third height, and the second height is substantially equal to a difference between the first height and the third height.
Regarding claim 16, the combination of Ryu et al. in view of Kim et al. teach the semiconductor package of claim 13. Neither Ryu et al. nor Kim et al. teach the package wherein the upper surfaces of the second connection pads have a central portion and a peripheral portion, wherein the central portion is positioned on a level lower than a level of the peripheral portion. None of the located prior art teaches this limitation. Therefore, it would be improper in hindsight to modify Ryu et al. to have the upper surfaces of the second connection pads have a central portion and a peripheral portion, wherein the central portion is positioned on a level lower than a level of the peripheral portion.
Regarding claim 17, the combination of Ryu et al. in view of Kim et al. teach the semiconductor package of claim 13. Neither Ryu et al nor Kim et al. teach the package wherein
outermost first connection pads of the first connection pads are more adjacent to side surfaces of the package substrate than the second connection pads, on the package substrate.
None of the located prior art teaches this limitation. Therefore, it would be improper in hindsight to modify Ryu et al. to have Therefore, it would be improper in hindsight to modify Ryu et al. to have outermost first connection pads of the first connection pads be more adjacent to side surfaces of the package substrate than the second connection pads, on the package substrate.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Park et al. (US 20170011976 A1) concerns a semiconductor chip with a chip pad and a redistribution wiring connection pad. Choi et al. (US 20220037261 A1) concerns a semiconductor package with a pad portion and an insulating layer.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JACOB A VLCEK whose telephone number is (571)272-9665. The examiner can normally be reached Mon-Fri, 9:00 AM -5:00 PM.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Eliseo Ramos-Feliciano can be reached at (571) 272-7925. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/J.A.V./ Examiner, Art Unit 2817
/ELISEO RAMOS FELICIANO/Supervisory Patent Examiner, Art Unit 2817
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