DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 1-20 rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-20 of U.S. Patent No. 11558040 and unpatentable over claims 1-20 of U.S. Patent No. 12040800. Although the claims at issue are not identical, they are not patentably distinct from each other because the patents’ claims and application’s claims recite similar limitations.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1, 3, 5-8, 10, 12-14, 17, 18 and 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kao et al. (US 20170141766) in view of Lin et al. (US 20180224505).
As to claim 1, Kao et al.’s figure 5A shows a flip-flop comprising: a not shown circuit that provides scan input signal SI. The figure fails to show that the not shown circuit is a delay circuit. However, Lin et al.’s figures 2A, 4 and 5 show a similar circuit that its scan input signal S20 is generated by a delay circuit 20A in order to fix hold-time violation. Thus, the modified Kao et al.’s figure 5A shows first circuitry (the added delay circuit) configured to generate a delayed scan input signal (SI); a latch (500) configured to output (at Q) a data signal (D) or the delayed scan input signal (SI) based on a scan enable signal (SEN); and second circuitry (550) configured to provide a clock signal to the latch and to receive an inverted version of the scan enable signal (SEN is an inverted version of SE).
As to claim 3, Lin et al.’s figures 2B and 4 in the modified Kao et al.’s figure shows that the first circuitry further comprises a first buffer (leftmost 20) having a first inverter and a second inverter (see Lin’s figure 4) coupled in series to a second buffer (that coupled to the output of the leftmost buffer 20) having a third inverter and a fourth inverter (see figure 4); and the delayed scan input signal is output from an output of the fourth inverter.
As to claim 5, the modified Kao et al.’s figure shows that the latch is further configured to receive the inverted version of the scan enable signal (SEN).
As to claim 6, the modified Kao et al.’s figure shows that the latch is further configured to receive an inverted version of the clock signal (clkb, clkbb, clk_m or clkbb_m).
As to claim 7, the modified Kao et al.’s figure shows that the first circuitry receives the scan enable signal (Lin’s STE or STEB) such that the scan enable signal bypasses the latch.
Claims 8, 10, 12-14, 17, 18 and 20 recite similar limitations in claims above. Therefore, they are rejected for the same reasons.
Claim(s) 2, 4, 9, 11, 15, 16 and 19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kao et al. (US 20170141766) in view of Lin et al. (US 20180224505) and Penzes et al. (US 20140266365).
As to claim 2, the modified Kao et al.’s figure fails to show that the added delay circuit (Lin’s 20) comprises a NOR gate. However, Lin et al.’s figures 4 and 5A shows that circuit 20 functions as a logic OR gate. Penzes et al.’s figure 1A shows a logic OR gate 150. It would have been obvious to one having ordinary skill in the art to use Penzes et al.’s logic OR gate for Lin et al.’s circuit 20 in the modified Kao et al.’s circuit due to the doctrine of equivalent function, MPEP 2144.06) and reducing noise. Therefore, circuit 20 in the modified Kao et al.’s figure includes the first circuitry comprises an inverter (Penzes et al.’s 154) coupled to a NOR gate (Penzes et al.’s 152), wherein the NOR gate is configured to receive a scan input signal (Lin’s TI) and the scan enable signal (Lin’s STEB/STE); an output of the NOR gate is coupled to an input of the inverter; and the delayed scan input signal is output from an output of the inverter.
As to claim 4, the modified Kao et al.’s figure shows further shows that a NOR gate (the leftmost 20 is also a NOR gate), the first buffer (that coupled to the leftmost buffer), and the second buffer (that coupled to the first buffer) are coupled together in series; and the delayed scan input signal is output from an output of the fifth inverter (Lin’s figure 4 shows that the each buffer comprises first and second inverters).
Claims 9, 11, 15, 16 and 19 recite similar limitations in claims above. Therefore, they are rejected for the same reasons.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ANH-QUAN TRA whose telephone number is (571)272-1755. The examiner can normally be reached Mon-Fri from 8:00 A.M.-5:00 P.M.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Lincoln Donovan can be reached at 571-272-1988. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/QUAN TRA/
Primary Examiner
Art Unit 2842