DETAILED ACTION
This Office action is in response to the election submitted on 07 July 2026. Claims 1-20 are pending in the application.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of the invention of Group I, on which claims 1-10 are readable, in the reply filed on 07 July 2026 is acknowledged.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-5 and 10 are rejected under 35 U.S.C. 102(a)(1) as being clearly anticipated by Endo et al., US 2009/0090920, cited by applicant on the Information Disclosure Statement (IDS) submitted on 21 April 2026.
With respect to claim 1, Endo et al. disclose a transistor, shown in Fig. 8 comprising:
a drain layer 13;
a drift layer 2 over the drain layer 13, see paragraph [0037];
a channel layer 3 over the drift layer 2;
a first source layer 6 over the channel layer 3;
a trench formed through the first source layer 6, through the channel layer 3 and at least partially into the drift layer 2; and a gate 9 formed within the trench, see Fig 8. .
With respect to claim 2, in the transistor of Endo et al., the drain layer 13 comprises a first concentration of a first type dopant n++, as shown in Fig. 8.
With respect to claim 3, in the transistor of Endo et al., the drift layer 2 comprises a second concentration of the first type dopant n, as shown in Fig. 8, the second concentration different from the first concentration, see paragraph [0037]. The drift layer has a lower concentration of the first type dopant (n) than the drain layer 13 (n++).
With respect to claim 4, in the transistor of Endo et al., the channel layer 3 comprises a third concentration of a second type dopant p, as shown in Fig. 8.
With respect to claim 5, in the transistor of Endo et al., the first source layer 6 comprises a fourth concentration of the first type dopant n+.
With respect to claim 10, the transistor of Endo et al. further comprises an insulating layer 10 over the gate 9within the trench, see paragraph [0044]..
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 6-9 are rejected under 35 U.S.C. 103 as being unpatentable over Endo et al., US 2009/0090920, as applied to claim 5 above, in view of Nakamura et al., US 9,041,006, cited by applicant on the Information Disclosure Statement (IDS) submitted on 21 April 2026.
Endo et al. is applied as above. Although Endo et al. disclose a SiC transistor having a gate 9 formed in a trench, as shown in Fig. 8 of Endo et al., Endo et al. lack anticipation of a second source layer between the first source layer and the channel layer, wherein the second source layer comprises a fifth concentration of the first type dopant, the fifth concentration different from the fourth concentration, and the trench is formed through the second source layer. However, in the same field of endeavor, Nakamura et al. disclose a SiC transistor having a gate formed in a trench and having a drift region, as shown in Fig. 1, wherein the source layer comprises a first source layer 6-1 of a high impurity concentration n-type and a second source layer 6-2 of a higher impurity concentration n-type, as shown in Fig. 1, thereby preventing the generation of leak defects, see column 12, lines 15-26. Therefore, in order to prevent leakage defects in the known transistor of Endo et al., it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include a second source layer 6-1 between the first source layer 6 and the channel layer 3, wherein the second source layer 6-1 comprises a fifth concentration of the first type dopant n, the fifth concentration different from the fourth concentration n+, and the trench is formed through the second source layer, as shown in Fig. 1 of Nakamura et al.. Nakamura et al. disclose that the first source layer 6-1 has a lower n-type doping concentration than the second source layer 6-2, see column 9, lines 20-43.
With respect to claim 7, the transistor of Endo et al. further comprises a shield layer 21 within the drift layer 2 and adjacent to the gate 9, wherein the shield layer comprises a sixth concentration of the second type dopant p, as shown in Fig. 8.
With respect to claim 8, the transistor of Endo et al. further comprises a drift implant layer 2a formed within the drift layer 2 and adjacent to the shield layer 21, wherein the drift implant layer 2a comprises a seventh concentration of the first type dopant n+, the seventh concentration n+ different from the second concentration n, as shown in Fig. 8. The seventh concentration of the drift implant region 2a (n+) is greater than the second concentration of the drift region (n), as shown in Fig. 8.
With respect to claim 9, the transistor of Endo et al. further comprises a body 5 having an eighth concentration of the second type dopant p+, as shown in Fig. 8.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. The additionally cited reference discloses a transistor having a gate formed in a trench and a drift region.
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MARY A. WILCZEWSKI
Primary Examiner
Art Unit 2898
/MARY A WILCZEWSKI/Primary Examiner, Art Unit 2898
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