DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
This office acknowledges receipt of the following items from the applicant: Information Disclosure Statement (IDS) filed on 10 June 2024. The references cited on the PTOL 1449 form have been considered.
Specification
The disclosure is objected to because of the following informalities:
Paragraphs 155 and 156 recite multiple instances of the reference character “174d” and each should instead read -- 173d -- to be consistent with Fig. 10.
Appropriate correction is required.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1, 2, 5, 6, 10, 11, 14-18 and 20 are rejected under 35 U.S.C. 102(a)(1) and 102(a)(2) as being anticipated by Lee (U.S. Patent Application Publication 2022/0139920)
Referring to Claim 1, Lee (‘920) teaches in Fig. 4A-4C for example, a semiconductor memory device comprising: a first bit line (215 of 215A) extending in a first direction (along A-A’; cross-section shown in Fig. 4B) on a substrate (201); a word line (212 of 216A) on the first bit line (215), and extending in a second direction (along B-B’; cross-section shown in Fig. 4C) intersecting the first direction (along A-A’); a first channel pattern (204) between the first bit line (215) and the word line (212), and extending along a first side wall of the word line (212); and a first contact pattern (432) on the first channel pattern (204), wherein in a cross-sectional view (Fig. 4C) taken along the first channel pattern (204) in the second direction (along B-B’), the first contact pattern (432) includes: a connecting part (horizontal portion) on the first channel pattern (204), and a protruding part (vertical portions), which is connected to the connecting part (horizontal portion), and extends along a side wall of the first channel pattern (204).
Referring to Claim 2, Lee (‘920) further teaches wherein a width of an upper surface of the first contact pattern (432) in the second direction (along B-B’; Fig. 4C) is greater than a width of an upper surface of the first channel pattern (204) in the second direction (along B-B’; Fig. 4C).
Referring to Claim 5, Lee (‘920) further teaches a second bit line (215) spaced apart from the first bit line (215) in the second direction (along B-B’; Fig. 4C); a second channel pattern (204), which is between the second bit line (215) and the word line (212), spaced apart from the first channel pattern (204) in the second direction (along B-B’; Fig. 4C), and extends along the first side wall of the word line (212); a second contact pattern (432), which is on the second channel pattern (204), and is on a part of a side wall of the second channel pattern (204); and an insulating pattern (331) disposed between the first contact pattern (432) and the second contact pattern (432).
Referring to Claim 6, Lee (‘920) further teaches wherein the insulating pattern includes: a first portion (upper portion) which is between the first contact pattern (432) and the second contact pattern (432), and a second portion (lower portion) which is disposed below the first portion (upper portion) relative to the substrate (201) providing a base reference plane and disposed between the first channel pattern (204) and the second channel pattern (204), and a width of the first portion (upper portion) in the second direction (along B-B’; Fig. 4C) is less than a width of the second portion (lower portion) in the second direction (along B-B’; Fig. 4C).
Referring to Claim 10, Lee (‘920) further teaches wherein a lower surface of the protruding part (vertical portions) of the first contact pattern (432) is above a lower surface of the first channel pattern (204), relative to an upper surface of the first bit line (215) providing a base reference plane.
Referring to Claim 11, Lee (‘920) further teaches wherein a lower surface of the connecting part (horizontal portion) of the first contact pattern (432) is above an upper surface of the word line (212), relative to an upper surface of the first bit line (215) providing a base reference plane.
Referring to Claim 14, Lee (‘920) further teaches a capacitor (435/237/240), which is on the first contact pattern (432), connected to the first channel pattern (204) (par. 66-68).
Referring to Claim 15, Lee (‘920) teaches in Fig. 4A-4C for example, a semiconductor memory device comprising: a first bit line extending in a first direction on a substrate; a word line on the first bit line, and extending in a second direction intersecting the first direction; a first channel pattern (204) between the first bit line (215) and the word line (212), and extending in a third direction (vertical) intersecting the first direction (along A-A’) and the second direction (along B-B’) along a first side wall of the word line (212); a first contact pattern (432) on the first channel pattern (204); a second bit line (215), which is spaced apart from the first bit line (215) in the second direction (along B-B’) and extends in the first direction (along A-A’); a second channel pattern (204) between the second bit line (215) and the word line (212), spaced apart from the first channel pattern (204) in the second direction (along B-B’), and extending in the third direction (vertical) along the first side wall of the word line (212); a second contact pattern (432) on the second channel pattern (204); and an insulating pattern (331) between the first channel pattern (204) and the second channel pattern (204), wherein the insulating pattern (331) includes: a first portion (upper portion) between the first contact pattern (432) and the second contact pattern (432), and a second portion (lower portion) below the first portion (upper portion) relative to the substrate (201) providing a base reference plane, and between the first channel pattern (204) and the second channel pattern (204), and wherein a width of the first portion (upper portion) is less than a width of the second portion (lower portion).
Referring to Claim 16, Lee (‘920) further teaches wherein a side face of the first contact pattern (432) overlaps a side face of the first channel pattern (204) in the second direction (along B-B’).
Referring to Claim 17, Lee (‘920) further teaches wherein a lower surface of the first contact pattern (432) is between a lower surface of the first channel pattern (204) and an upper surface of the first channel pattern (204).
Referring to Claim 18, Lee (‘920) further teaches wherein the first contact pattern (432) includes: a connecting part (horizontal portion) on an upper surface of the first channel pattern (204), and a protruding part (vertical portions), which is on a lower surface of the connecting part (horizontal portion) and extends along a side wall of the first channel pattern (204).
Referring to Claim 20, Lee (‘920) teaches in Fig. 4A-4C for example a semiconductor memory device comprising: a first bit line (215) extending in a first direction (along A-A’) on a substrate (201); a word line (212) on the first bit line (215), and extending in a second direction (along B-B’) intersecting the first direction (along A-A’); a first channel pattern (204) between the first bit line (215) and the word line (212), and extending along a first side wall of the word line (212) in a third direction (vertical) intersecting the first direction (along A-A’) and the second direction (along B-B’); a gate insulating film (120) between the first channel pattern (204) and the word line (212), and extending in the third direction (vertical) along a side wall of the first channel pattern (204) and the first side wall of the word line (212); a first contact pattern (lower portion of 432) on the first channel pattern (204); an insulating pattern (331) extending along a side face of the first contact pattern (lower portion of 432) and a side face of the first channel pattern (204); a landing pad (upper portion of 432) on the first contact pattern (lower portion of 432); and a capacitor (435/237/240; par. 66-68) on the landing pad (upper portion of 432) and connected to the first channel pattern (204), wherein in a cross-sectional view (Fig. 4C) taken along the first channel pattern (204) in the second direction (along B-B’), the first contact pattern (432) includes: a connecting part (horizontal portion) on the first channel pattern (204), and a protruding part (vertical portions) connected to the connecting part (horizontal portion) and extending along the side wall of the first channel pattern (204), and wherein a lower surface of the protruding part (vertical portions) is located above a lower surface of the first channel pattern (204) relative to the substrate (201) providing a base reference plane.
Claims 1, 2, 4-11 and 13-20 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Lee et al. (U.S. Patent Application Publication 2024/0381623).
The applied reference has a common assignee with the instant application. Based upon the earlier effectively filed date of the reference, it constitutes prior art under 35 U.S.C. 102(a)(2). This rejection under 35 U.S.C. 102(a)(2) might be overcome by: (1) a showing under 37 CFR 1.130(a) that the subject matter disclosed in the reference was obtained directly or indirectly from the inventor or a joint inventor of this application and is thus not prior art in accordance with 35 U.S.C. 102(b)(2)(A); (2) a showing under 37 CFR 1.130(b) of a prior public disclosure under 35 U.S.C. 102(b)(2)(B) if the same invention is not being claimed; or (3) a statement pursuant to 35 U.S.C. 102(b)(2)(C) establishing that, not later than the effective filing date of the claimed invention, the subject matter disclosed in the reference and the claimed invention were either owned by the same person or subject to an obligation of assignment to the same person or subject to a joint research agreement.
Referring to Claim 1, Lee (‘623) teaches Fig. 1-6 for example, a semiconductor memory device comprising: a first bit line (BL) extending in a first direction (Y) on a substrate (100); a word line (WL) on the first bit line (BL), and extending in a second direction (X) intersecting the first direction (Y); a first channel pattern (CP) between the first bit line (BL) and the word line (WL), and extending along a first side wall of the word line (WL); and a first contact pattern (LP) on the first channel pattern (CP), wherein in a cross-sectional view (C-C’: Fig. 3) taken along the first channel pattern (CP) in the second direction (X), the first contact pattern (LP) includes: a connecting part on (along the top of CP_S1 and CP_S2) the first channel pattern (CP), and a protruding part (LP2), which is connected to the connecting part, and extends along a side wall (one of CP_S3 or CP_S4) of the first channel pattern (CP).
Referring to Claim 2, Lee (‘623) further teaches in Fig. 3, wherein a width of an upper surface of the first contact pattern (LP) in the second direction (X) is greater than a width of an upper surface of the first channel pattern (CP) in the second direction (X).
Referring to Claim 4, Lee (‘623) further teaches in Fig. 4 for example, a gate insulating film (120) between the first side wall of the word line (WL) and the first channel pattern (CP), wherein the gate insulating film (120) extends along side walls of the first contact pattern (lower portion of LP). It is noted that the recitation of “extends along side walls” does not required direct physical contact between respective elements.
Referring to Claim 5, Lee (‘623) further teaches a second bit line (BL) spaced apart from the first bit line (BL) in the second direction (X); a second channel pattern (CP), which is between the second bit line (BL) and the word line (WL), spaced apart from the first channel pattern (CP) in the second direction (X), and extends along the first side wall of the word line (WL); a second contact pattern (LP), which is on the second channel pattern (CP), and is on a part of a side wall of the second channel pattern (CP); and an insulating pattern (120/130/160/150) disposed between the first contact pattern (LP) and the second contact pattern (LP).
Regarding Claim 6, Lee (‘623) further teaches in Fig. 3 the insulating pattern (120/130/160/150) includes: a first portion (130/160/150) which is between the first contact pattern (lower portion of LP) and the second contact pattern (lower portion of LP), and a second portion (120) which is disposed below the first portion (130/160/150) relative to the substrate (100) providing a base reference plane, and disposed between the first channel pattern (CP) and the second channel pattern (CP), and a width (at the bottom) of the first portion (130/160/150) is less than a width (at the bottom) of the second portion (120) in the second direction (X).
Referring to Claim 7, Lee (‘623) further teaches wherein the insulating pattern (120/130/160/150) includes: a liner film (120) below the first contact pattern (LP) and the second contact pattern (LP) relative to the substrate (100) providing a base reference plane, and extending along side walls (CP_S3 and CP_S4) of the first channel pattern (CP) and the second channel pattern (CP), and a filling film (130) on the liner film (120), and does not overlap the first contact pattern (LP) and the second contact pattern (LP) in a third direction (Z) perpendicular to the first direction (Y) and the second direction (X).
Referring to Claim 8, Lee (‘623) further teaches wherein the liner film (120) includes silicon nitride (par. 72), and wherein the filling film (130) includes silicon oxide (par. 78).
Referring to Claim 9, Lee (‘623) further teaches wherein a lower surface (LP_E1) of the protruding part (LP2) of the first contact pattern (LP) is below an upper surface of the word line (WL), relative to an upper surface of the first bit line (BL) providing a base reference plane.
Referring to Claim 10, Lee (‘623) further teaches in Fig. 3 wherein a lower surface (LP_E1 or LP_E2) of the protruding part (LP2) of the first contact pattern (LP) is above a lower surface of the first channel pattern (CP), relative to an upper surface of the first bit line (BL) providing a base reference plane.
Referring to Claim 11, Lee (‘623) further teaches in Fig. 3 wherein a lower surface (along the top of CP_S1 and CP_S2) of the connecting part of the first contact pattern (LP) is above an upper surface of the word line (WL), relative to an upper surface of the first bit line (BL) providing a base reference plane.
Referring to Claim 13. Lee (‘623) further teaches in Fig. 1-3 wherein a lower surface of the word line (WL) completely overlaps the first channel pattern (CP) in a third direction (Z) intersecting the first direction (Y) and the second direction (X).
Referring to Claim 14, Lee (‘623) further teaches in Fig. 2, a capacitor (DSP; par. 113), which is on the first contact pattern (LP), connected to the first channel pattern (CP).
Referring to Claim 15, Lee (‘623) teaches in Fig. 1-6 for example, a semiconductor memory device comprising: a first bit line (BL) extending in a first direction (Y) on a substrate (100); a word line on the first bit line (BL), and extending in a second direction (X) intersecting the first direction (Y); a first channel pattern (CP) between the first bit line (BL) and the word line (WL), and extending in a third direction (Z) intersecting the first direction (Y) and the second direction (X) along a first side wall of the word line (WL); a first contact pattern (lower portion of LP) on the first channel pattern (CP); a second bit line (BL), which is spaced apart from the first bit line (BL) in the second direction (X) and extends in the first direction (Y); a second channel pattern (CP) between the second bit line (BL) and the word line (WL), spaced apart from the first channel pattern (CP) in the second direction (X), and extending in the third direction (Z) along the first side wall of the word line (WL); a second contact pattern (lower portion of LP) on the second channel pattern (CP); and an insulating pattern (120/130/160/150) between the first channel pattern (CP) and the second channel pattern (CP), wherein the insulating pattern (120/130/160/150) includes: a first portion (130/160/150) between the first contact pattern (lower portion of LP) and the second contact pattern (lower portion of LP), and a second portion (120) below the first portion (130/160/150) relative to the substrate (100) providing a base reference plane, and between the first channel pattern (CP) and the second channel pattern (CP), and wherein a width (at the bottom) of the first portion (130/160/150) is less than a width (at the bottom) of the second portion (120).
Referring to Claim 16, Lee (‘623) further teaches in Fig. 3 wherein a side face of the first contact pattern (lower portion of LP) overlaps a side face of the first channel pattern (CP) in the second direction (X).
Referring to Claim 17, Lee (‘623) further teaches wherein a lower surface of the first contact pattern (lower portion of LP) is between a lower surface of the first channel pattern (CP) and an upper surface of the first channel pattern (CP).
Referring to Claim 18, Lee (‘623) further teaches wherein the first contact pattern (lower portion of LP) includes: a connecting part on (along the top of CP_S1 and CP_S2) an upper surface of the first channel pattern (CP), and a protruding part (LP2), which is on a lower surface of the connecting part and extends along a side wall of the first channel pattern (CP).
Referring to Claim 19, Lee (‘623) further teaches in Fig. 1-3 wherein an entire lower surface of the word line (WL) extending in the second direction (X) overlaps the first channel pattern (CP) in the third direction (Z).
Referring to Claim 20, Lee (‘623) teaches in Fig. 1-6 for example, a semiconductor memory device comprising: a first bit line (BL) extending in a first direction (Y) on a substrate (100); a word line (WL) on the first bit line (BL), and extending in a second direction (X) intersecting the first direction (Y); a first channel pattern (CP) between the first bit line (BL) and the word line (WL), and extending along a first side wall of the word line (WL) in a third direction (Z) intersecting the first direction (Y) and the second direction (X); a gate insulating film (120) between the first channel pattern (CP) and the word line (WL), and extending in the third direction (Z) along a side wall of the first channel pattern (CP) and the first side wall of the word line (WL); a first contact pattern (lower portion of LP) on the first channel pattern (CP); an insulating pattern (210/220) extending along a side face of the first contact pattern (lower portion of LP) and a side face of the first channel pattern (CP); a landing pad (top portion of LP) on the first contact pattern (lower portion of LP); and a capacitor (DSP; par. 113) on the landing pad (top portion of LP) and connected to the first channel pattern (CP), wherein in a cross-sectional view (C-C’: Fig. 3) taken along the first channel pattern (CP) in the second direction (X), the first contact pattern (lower portion of LP) includes: a connecting part on (along the top of CP_S1 and CP_S2) the first channel pattern (CP), and a protruding part (LP2) connected to the connecting part and extending along the side wall of the first channel pattern (CP), and wherein a lower surface of the protruding part (LP2) is located above a lower surface of the first channel pattern (CP) relative to the substrate (100) providing a base reference plane.
Allowable Subject Matter
Claims 3 and 12 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding Claim 3, the prior art of record alone or in combination neither teaches nor makes obvious the invention of the semiconductor memory device wherein a width of the upper surface of the first contact pattern in the first direction is the same as a width of the upper surface of the first channel pattern in the first direction in combination with all of the limitations of Claim 1 and 3.
Regarding Claim 12, the prior art of record alone or in combination neither teaches nor makes obvious the invention of the semiconductor memory device wherein a lower surface of the connecting part of the first contact pattern is below an upper surface of the word line, relative to an upper surface of the first bit line providing a base reference plane in combination with all of the limitations of Claim 1 and 12.
Contact Information
Any inquiry concerning this communication or earlier communications from the examiner should be directed to EARL N TAYLOR whose telephone number is (571)272-8894. The examiner can normally be reached M-F, 9:00am-5:00pm.
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/EARL N TAYLOR/Primary Examiner, Art Unit 2896
EARL N. TAYLOR
Primary Examiner
Art Unit 2896
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