DETAILED ACTION
This correspondence is in response to the communications received 06/10/2024. Claims 1-20 are pending.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 06/10/2024 has been considered by the examiner and made of record in the application file.
Specification
The lengthy specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant’s cooperation is requested in correcting any errors of which applicant may become aware in the specification.
Claim Objections
Claim 1 recites “wherein the memory stack includes a plurality of memory dies,
wherein the memory stack includes a first memory die…”, however based on the similar structure of claim 15, the above limitation of claim 1 may be clearer if written as “wherein the memory stack includes a plurality of memory dies,
wherein the plurality of memory dies includes a first memory die…”
Applicant’s Claim to Figure Comparison
It is noted that this comparison is merely for the benefit of reviewers of this office action during prosecution, to allow for an understanding of the examiner’s interpretation of the Applicant’s independent claims as compared to disclosed embodiments in Applicant’s Figures. No response or comments are necessary from Applicant.
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Regarding claim 1, a high bandwidth memory, comprising:
a base die ("buffer die 110"); and
a memory stack ("16H-memory stack 410") on the base die (see Fig. 7),
wherein the memory stack includes a plurality of memory dies ("1H-memory die 111 to the 16H-memory die 126"),
wherein the memory stack includes
a first memory die (111) closest to the base die among the plurality of memory dies (see Fig. 7), the first memory die having a first width in a horizontal direction (see Fig. 7), the horizontal direction extending parallel to an in-plane direction of the base die, and
a second memory die on the first memory die (112), the second memory die having a second width in the horizontal direction (see Fig. 7), wherein the first width is smaller than the second width (see Fig. 7).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1 and 2 are rejected under 35 U.S.C. 103 as being unpatentable over Bang et al. (US 20240213219 A1, filed 05/19/2023) in view of Uzoh et al. (US 9,583,456 B2, published 02/28/2017).
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Regarding claim 1, Figs. 1-6 and 9 of Bang disclose a high bandwidth memory (see title), comprising:
a base die (“base die 10”, [0021]); and
a memory stack (“memory stack 20”, [0021]) on the base die (as seen in Fig. 1, 20 is on 10), wherein the memory stack includes a plurality of memory dies (“The memory stack 20 may include a plurality of stacked memory dies 20B, 20M and 20T. The plurality of memory dies 20B, 20M and 20T may include a bottom memory die 20B, a plurality of intermediate memory dies 20M, and a top memory die 20T”, [0023]),
wherein the memory stack includes
a first memory die (20B) closest to the base die among the plurality of memory dies (as seen in Fig. 1, 20B is closest to 10 among 20B, 20M, and 20T), the first memory die having a first width in a horizontal direction (as seen in Fig. 1, 20B has a first width in a horizontal direction), the horizontal direction extending parallel to an in-plane direction of the base die (the horizontal direction of Fig. 1 extends parallel to an in-plane direction of 10), and
a second memory die (the bottommost instance of 20M is a second memory die) on the first memory die (as seen in Fig. 1, the bottommost instance of 20M is on 20B), the second memory die having a second width in the horizontal direction (as seen in Fig. 1, the bottommost instance of 20M has a second width in the horizontal direction).
Bang fails to disclose “wherein the first width is smaller than the second width”.
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However, in a similar field of endeavor, Fig. 6B of Uzoh teaches wherein the first width is smaller than the second width (as seen in Fig. 6B, the horizontal width of “die 626”, col. 13, line 59, is smaller than the horizontal width of “die 627”, col. 13, line 60, where 626 and 627 of Uzoh are equivalent to 20B and the bottommost instance of 20M of Bang, respectively).
Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to implement “wherein the first width is smaller than the second width” as taught by Uzoh in the system of Bang for the purpose of further increasing die connectivity by adding external connectivity to the bottom surfaces of stacked dies.
Regarding claim 2, Figs. 1-6 and 9 of Bang in combination with Fig. 6B of Uzoh disclose the high bandwidth memory of claim 1, Fig. 6B of Uzoh further discloses wherein:
the memory stack further comprises a third memory die (“die 629”, col. 13, line 66) on the second memory die (as seen in Fig. 6B, 629 is on 627), the third memory die having a third width in the horizontal direction (as seen in Fig. 6B, 629 has a third width in the horizontal direction), and
the second width is smaller than the third width (as seen in Fig. 6B, the second width of 627 is smaller than the third width of 629).
Claims 3-5 and 9 are rejected under 35 U.S.C. 103 as being unpatentable over Bang et al. (US 20240213219 A1, filed 05/19/2023) in view of Uzoh et al. (US 9,583,456 B2, published 02/28/2017) in view of Keeth et al. (US 11,386,004 B2, published 07/12/2022).
Regarding claim 3, Figs. 1-6 and 9 of Bang in combination with Fig. 6B of Uzoh disclose the high bandwidth memory of claim 2.
Bang in combination with Uzoh fail to specify “wherein:
the memory stack further comprises fourth to eighth memory dies that are sequentially stacked”.
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However, in a similar field of endeavor, Fig. 8B of Keeth teach wherein:
the memory stack further comprises fourth to eighth memory dies that are sequentially stacked (“The stack of DRAM dies 830 in FIG. 8B includes 16 DRAM dies”, col. 11, lines 46-47, where as seen in Fig. 8B, 830 includes fourth through eighth dies that are sequentially stacked).
Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to implement “wherein:
the memory stack further comprises fourth to eighth memory dies that are sequentially stacked” as taught by Keeth in the system of Bang in combination with Uzoh for the purpose of increasing die density.
Regarding claim 4, Figs. 1-6 and 9 of Bang in combination with Fig. 6B of Uzoh and Fig. 8B of Keeth disclose the high bandwidth memory of claim 3, Fig. 8B of Keeth further discloses wherein:
the memory stack further comprises ninth to twelfth memory dies that are sequentially stacked (as seen in Fig. 8B, 830 includes ninth through twelfth dies that are sequentially stacked).
Regarding claim 5, Figs. 1-6 and 9 of Bang in combination with Fig. 6B of Uzoh and Fig. 8B of Keeth disclose the high bandwidth memory of claim 4, Fig. 8B of Keeth further discloses wherein:
the fourth to twelfth memory dies each have a fourth width in the horizontal direction (as seen in Fig. 8B, the fourth through twelfth dies each have a fourth width in the horizontal direction).
Regarding claim 9, Figs. 1-6 and 9 of Bang in combination with Fig. 6B of Uzoh and Fig. 8B of Keeth disclose the high bandwidth memory of claim 4, Fig. 8B of Keeth further discloses wherein:
the memory stack further includes thirteenth to sixteenth memory dies that are sequentially stacked (as seen in Fig. 8B, 830 includes thirteenth through sixteenth dies that are sequentially stacked).
Claims 15-19 are rejected under 35 U.S.C. 103 as being unpatentable over Bang et al. (US 20240213219 A1, filed 05/19/2023) in view of Sohn et al. (US 11,232,029 B2, published 07/12/2022) in view of Uzoh et al. (US 9,583,456 B2, published 02/28/2017).
Regarding claim 15, Figs. 1-6 and 9 of Bang disclose a high bandwidth memory (see title), comprising:
a base die (“base die 10”, [0021]); and
a memory stack (“memory stack 20”, [0021]) on the base die (as seen in Fig. 1, 20 is on 10), the memory stack including
a plurality of memory dies (“The memory stack 20 may include a plurality of stacked memory dies 20B, 20M and 20T. The plurality of memory dies 20B, 20M and 20T may include a bottom memory die 20B, a plurality of intermediate memory dies 20M, and a top memory die 20T”, [0023]), and
a plurality of interconnection structures (“signal transmission structures 30, and power distribution structures 40, 50, and 60”, [0021, as seen in Fig. 1, 30, 40, 50, and 60 interconnect 20B, 20M, and 20T); and
wherein the plurality of memory dies includes
a first memory die (20B) closest to the base die among the plurality of memory dies (as seen in Fig. 1, 20B is closest to 10 among 20B, 20M, and 20T), the first memory die having a first width in a horizontal direction (as seen in Fig. 1, 20B has a first width in a horizontal direction), the horizontal direction extending parallel to an in-plane direction of the base die (the horizontal direction of Fig. 1 extends parallel to an in-plane direction of 10), and
a second memory die (the bottommost instance of 20M is a second memory die) on the first memory die (as seen in Fig. 1, the bottommost instance of 20M is on 20B), the second memory die having a second width in the horizontal direction (as seen in Fig. 1, the bottommost instance of 20M has a second width in the horizontal direction),
the plurality of interconnection structures includes
a first interconnection structure connecting the base die and the first memory die (as seen in Fig. 1, a portion of 30, 40, and 60 connect 10 and 20B), and
a second interconnection structure connecting the first memory die and the second memory die (as seen in Fig. 1, a portion of 30, 50, and 60 connect 20B and the bottommost instance of 20M).
Bang fails to disclose “a molding material molding the memory stack on the base die,
the second width greater than the first width”.
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However, in a similar field of endeavor, Figs. 3A and 3B of Sohn teach a molding material (“side mold member 340”) molding the memory stack on the base die (as seen in Fig. 3A, 340 molds “plurality of core dies MD1 to MD8”, col. 6, lines 42-43, on “buffer die 310”, col. 6, line 42).
Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to implement “a molding material molding the memory stack on the base die” as taught by Sohn in the system of Bang for the purpose of protecting and supporting the die stack.
Bang in combination with Sohn fails to disclose “the second width greater than the first width”.
However, in a similar field of endeavor, Fig. 6B of Uzoh teaches the second width greater than the first width (as seen in Fig. 6B, the horizontal width of “die 627”, col. 13, line 60, is greater than the horizontal width of “die 626”, col. 13, line 59, where 626 and 627 of Uzoh are equivalent to 20B and the bottommost instance of 20M of Bang, respectively).
Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to implement “the second width greater than the first width” as taught by Uzoh in the system of Bang in combination with Sohn for the purpose of further increasing die connectivity by adding external connectivity to the bottom surfaces of stacked dies.
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Regarding claim 16, Figs. 1-6 and 9 of Bang in combination with Figs. 3A and 3B of Sohn and Fig. 6B of Uzoh disclose the high bandwidth memory of claim 15, Figs. 1-6 and 9 of Bang further disclose wherein:
the first memory die and the second memory die each include a plurality of through silicon vias (“The inventive concepts of a via structure 22 according to an embodiment of the disclosure may be selectively or wholly applied to the via structures 232B, 232M, 232T, 242B, 242M, 242T, 252B, 252M, 252T, 262B, 262M, and 262T of FIGS. 2 to 8. Referring to FIG. 9, the via structure 22 according to an embodiment of the present disclosure may include a metal via 22a, a via pad 22b, and a TSV (through-silicon via) 22c”, [0066]).
Regarding claim 17, Figs. 1-6 and 9 of Bang in combination with Figs. 3A and 3B of Sohn and Fig. 6B of Uzoh disclose the high bandwidth memory of claim 15, Figs. 3A and 3B of Sohn further disclose wherein:
the base die is a buffer die (as discussed previously 310 of Sohn is a buffer die, which is equivalent to 10 of Bang as a base for MD1 through MD8).
Regarding claim 18, Figs. 1-6 and 9 of Bang in combination with Figs. 3A and 3B of Sohn and Fig. 6B of Uzoh disclose the high bandwidth memory of claim 15, Figs. 1-6 and 9 of Bang further disclose wherein:
the plurality of memory dies are DRAM (“For example, each of the bottom memory die 20B, the intermediate memory dies 20M, and the top memory die 20T may include a dynamic random access memory (DRAM)”, [0023]).
Regarding claim 19, Figs. 1-6 and 9 of Bang in combination with Figs. 3A and 3B of Sohn and Fig. 6B of Uzoh disclose the high bandwidth memory of claim 15, Figs. 1-6 and 9 of Bang further disclose wherein:
each of the plurality of interconnection structures comprises:
a plurality of micro bumps (“The metal via 22a may extend vertically and partially through the lower area LA of the memory dies 20B, 20M, and 20T to electrically connect a lower bump 21 to the via pad 22b … The TSV 22c may extend to vertically and partially pass through the upper area UA of the memory dies 20B, 20M, and 20T to electrically connect the via pad 22b to an upper bump 23”, [0066]);
Figs. 3A and 3B of Sohn further disclose non-conductive film (NCF) insulating the plurality of micro bumps (“the underfill layer 320 may be arranged through … a thermal compression-non conductive film (TC-NCF) process”, col. 7, lines 29-34, as seen in Fig. 3A, 320 insulates “Solder bumps SB”, col. 7, line 24, which are equivalent to 21 and 23 of Bang).
Claim 20 is rejected under 35 U.S.C. 103 as being unpatentable over Bang et al. (US 20240213219 A1, filed 05/19/2023) in view of Sohn et al. (US 11,232,029 B2, published 07/12/2022) in view of Uzoh et al. (US 9,583,456 B2, published 02/28/2017) in view of Molnar et al. (US 20230187407 A1, published 06/15/2023).
Regarding claim 19, Figs. 1-6 and 9 of Bang in combination with Figs. 3A and 3B of Sohn and Fig. 6B of Uzoh disclose the high bandwidth memory of claim 15.
Bang in combination with Sohn and Uzoh fail to disclose “wherein:
each of the plurality of interconnection structures comprises
a plurality of first bonding pads;
a first silicon insulating layer insulating the plurality of first bonding pads;
a plurality of second bonding pads located on the plurality of first bonding pads, the plurality of second bonding pads directly bonded to the plurality of first bonding pads; and
a second silicon insulating layer located on the first silicon insulating layer and directly bonded to the first silicon insulating layer.
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However, in a device that is reasonably pertinent to the particular problem with which the inventor was concerned, Figs. 2B and 2C of Molnar teach wherein:
each of the plurality of interconnection structures comprises
a plurality of first bonding pads (“conductive contact 254”, [0129]);
a first silicon insulating layer (“dielectric 258 (e.g., silicon oxide, silicon nitride, silicon oxynitride, etc.)”, [0129]) insulating the plurality of first bonding pads (as seen in Fig. 2C, 258 insulates 254);
a plurality of second bonding pads (“conductive contact 252”, [0129]) located on the plurality of first bonding pads (as seen in Fig. 2C, 252 is located on 254), the plurality of second bonding pads directly bonded to the plurality of first bonding pads (“conductive contact 252 … may bond with conductive contact 254”, [0129]); and
a second silicon insulating layer (“dielectric 256 (e.g., silicon oxide, silicon nitride, silicon oxynitride, etc.)”, [0129]) located on the first silicon insulating layer (as seen in Fig. 2C, 256 is located on 258) and directly bonded to the first silicon insulating layer (“dielectric 256 … may bond with dielectric 258”, [0129]).
Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to implement “wherein:
each of the plurality of interconnection structures comprises
a plurality of first bonding pads;
a first silicon insulating layer insulating the plurality of first bonding pads;
a plurality of second bonding pads located on the plurality of first bonding pads, the plurality of second bonding pads directly bonded to the plurality of first bonding pads; and
a second silicon insulating layer located on the first silicon insulating layer and directly bonded to the first silicon insulating layer” as taught by Molnar in the
system of Bang in combination with Sohn and Uzoh for the purpose of increasing connection density (“DTD interconnects 218 comprise hybrid bonds comprised of metal-to-metal and oxide-to-oxide (e.g., silicon oxide-to-silicon oxide) bonds, permitting silicon-level interconnect density and low pitch interconnection”, Molnar, [0115]).
Allowable Subject Matter
Claims 6-8 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. The following is a statement of reasons for the indication of allowable subject matter: The prior art of record does not teach or fairly suggest the high bandwidth memory as recited in the claims of the instant application.
Regarding claim 6, the prior art of Bang et al. (US 20240213219 A1) in combination with Uzoh et al. (US 9,583,456 B2) in combination with Keeth et al. (US 11,386,004 B2) discloses a similar high bandwidth memory but fails to disclose the specific claims of the instant application regarding the exact relationship of the widths of the first and fourth dies e.g. “wherein: the first width is 1.2% smaller than the fourth width.”
Regarding claim 7, the prior art of Bang et al. (US 20240213219 A1) in combination with Uzoh et al. (US 9,583,456 B2) in combination with Keeth et al. (US 11,386,004 B2) discloses a similar high bandwidth memory but fails to disclose the specific claims of the instant application regarding the exact relationship of the widths of the second and fourth dies e.g. “the second width is 0.8% smaller than the fourth width.”
Regarding claim 8, the prior art of Bang et al. (US 20240213219 A1) in combination with Uzoh et al. (US 9,583,456 B2) in combination with Keeth et al. (US 11,386,004 B2) discloses a similar high bandwidth memory but fails to disclose the specific claims of the instant application regarding the exact relationship of the widths of the third and fourth dies e.g. “the third width is 0.4% smaller than the fourth width.”
Claims 10-14 are allowed. The following is an examiner’s statement of reasons for allowance: The prior art of record does not teach or fairly suggest the high bandwidth memory as recited in the claims of the instant application.
Regarding claim 10, the prior art of the prior art of Bang et al. (US 20240213219 A1) in combination with Uzoh et al. (US 9,583,456 B2) discloses a similar high bandwidth memory but fails to disclose the specific claims of the instant application regarding the relationship of the widths of the dies of the second sub-memory stack e.g. “wherein the second sub-memory stack has a profile in which a horizontal width of each memory die of the plurality of second memory dies decreases from a lower second memory die of the plurality of second memory dies to an upper second memory die of the plurality of second memory dies, the lower second memory die closest to the base die among the plurality of second memory dies.”
Claims 11-14 are allowable by virtue of their dependence on claim 10.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to BENJAMIN M KUPP whose telephone number is (571)272-5608. The examiner can normally be reached Monday - Friday, 7:00 am - 4:00 pm PT.
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/BENJAMIN MICHAEL KUPP/Examiner, Art Unit 2893
/YARA B GREEN/Supervisor Patent Examiner, Art Unit 2893
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