DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Status of Claims
Applicant’s election of the invention of species V, drawn to Figure 12 and claims 1-3, 6-14, 16-8, and 27 is acknowledged. Claims 4-5, 15, and 19, drawn to a nonelected species are thus withdrawn from further examination. Claims 20-26 have been cancelled. Claims 1-3, 6-14, 16-18, and 27 are examined herein.
Election/Restrictions
Claims 4-5, 15, and 19 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected species, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 07/16/2026.
Applicant’s election without traverse of species V, drawn to Figure 12 and claims 1-3, 6-14, 16-18, and 27, in the reply filed on 07/16/2026 is acknowledged.
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 06/10/2024 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-3, 6-10, and 27 is/are rejected under 35 U.S.C. 103 as being unpatentable over Choi (US Patent Application Publication 2017/0047363A1) in view of Choi (US Patent Application Publication 2022/0344393A1).
Regarding claim 1, Choi (US Patent Application Publication 2017/0047363A1) teaches an image sensor (auto-focus image sensor, Figures 2-5, Abstract), comprising: a substrate (substrate 20, Figure 5, paragraphs 0093-0095) that comprises a plurality of pixels (unit pixel UP, Figures 2-5, paragraph 0093), each of which comprises a left sub-pixel and a right sub-pixel (sub-pixels Px, Figures 4-5, paragraph 0095); a well region (first impurity region 32, Figure 5, paragraph 0095) in the substrate on each of the plurality of pixels, the well region connecting the left sub-pixel and the right sub-pixel to each other; a pixel separation part (pixel separation part 70 + sub-pixel separation part 80, Figures 4-5, paragraphs 0094 + 0096) that separates the plurality of pixels from each other and extends in the substrate between the left sub-pixel and the right sub-pixel; a left transfer transistor (transfer transistor TX, paragraph 0086) and a first logic transistor on the left sub-pixel (reset transistor RX or drive transistor / source follower transistor DX or selection transistor SX, paragraph 0086); a right transfer transistor (transfer transistor TX, paragraph 0086) and a second logic transistor (reset transistor RX or drive transistor / source follower transistor DX or selection transistor SX, paragraph 0086) on the right sub-pixel, as claimed
Choi (US Patent Application Publication 2017/0047363A1) is silent to teach a ground region in the substrate on one of the left sub-pixel and the right sub-pixel, and in contact with the well region, wherein the ground region is adjacent to a corner of each of the plurality of pixels.
In an analogous art, Choi (US Patent Application Publication 2022/0344393A1) teaches a ground region (ground region GR, Figure 1A-1B + 2A, paragraph 0040) in the substrate on one of the left sub-pixel and the right sub-pixel, and in contact with the well region, wherein the ground region is adjacent to a corner of each of the plurality of pixels (Figure 1A).
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Therefore, it would have been obvious for some one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the teachings of Choi (US Patent Application Publication 2017/0047363A1) by incorporating a ground region in contact with the well region and at the corner of each pixel as taught by Choi (US Patent Application Publication 2022/0344393A1) thereby providing a ground voltage to a transfer transistor preventing a short circuit issue from occurring therebetween.
Regarding claim 2, Choi (US Patent Application Publication 2017/0047363A1) and Choi (US Patent Application Publication 2022/0344393A1) teach the image sensor of claim 1, as claimed. Choi (US Patent Application Publication 2017/0047363A1) further teaches further comprising a microlens (micro lens ML, Figure 4-5, paragraphs 0103-0104) on the left sub-pixel and the right sub-pixel on each of the plurality of pixels.
Regarding claim 3, Choi (US Patent Application Publication 2017/0047363A1) and Choi (US Patent Application Publication 2022/0344393A1) teach the image sensor of claim 1, as claimed.
Choi (US Patent Application Publication 2017/0047363A1) is silent to teach further comprising a device isolation part in the substrate on a center of each of the plurality of pixels. However, Choi (US Patent Application Publication 2022/0344393A1) teaches further comprising a device isolation part in the substrate on a center of each of the plurality of pixels (shallow trench isolation layer STI, Figure 1A, paragraph 0035).
Therefore, it would have been obvious for some one of ordinary skill in the art before the effective filing date of the claimed invention to have further modified the teachings of Choi (US Patent Application Publication 2017/0047363A1) by isolating the ground region from the transfer transistor with the shallow device isolation layer as taught by Choi (US Patent Application Publication 2022/0344393A1) thereby preventing a short circuit issue from occurring therebetween.
Regarding claim 6, Choi (US Patent Application Publication 2017/0047363A1) and Choi (US Patent Application Publication 2022/0344393A1) teach the image sensor of claim 1, as claimed.
Choi (US Patent Application Publication 2017/0047363A1) is silent to teach wherein each of gate electrodes of the left transfer transistor and the right transfer transistor comprises at least one protruding part that extends into the substrate. However, Choi (US Patent Application Publication 2022/0344393A1) teaches a transfer gate contact (transfer gate contact CT_TG, Figures 1A-1B, paragraph 0046) that extends into the substrate to connect the transistor transfer gate (transfer gate TG, Figures 1A-1B) to the device wiring.
Therefore, it would have been obvious for some one of ordinary skill in the art before the effective filing date of the claimed invention to have further modified the sub-pixels of Choi (US Patent Application Publication 2017/0047363A1) to include the transfer gate contact in the transfer gates such that the contact extends into the substrate, thereby providing an electrical connection between the transfer transistors for each sub-pixel and the device wiring.
Regarding claim 7, Choi (US Patent Application Publication 2017/0047363A1) teaches an image sensor, comprising: a substrate (substrate 20, Figure 5, paragraphs 0093-0095) comprising a plurality of pixel groups (Figure 4), each of which comprises a plurality of pixels (unit pixels UP, Figure 4-5, paragraph 0093) in a 2×2 arrangement, each of the plurality of pixels comprising a left sub-pixel and a right sub-pixel (sub-pixels Px, Figure 4-5, paragraphs 0095); a well region (first impurity region 32, Figure 5, paragraph 0095) in the substrate on each of the plurality of pixels, the well region connecting the left sub-pixel and the right sub-pixel to each other; a pixel separation part (pixel separation part 70 + sub-pixel separation part 80, Figures 4-5, paragraphs 0094 + 0096) that separates the plurality of pixels from each other and extends in the substrate between the left sub-pixel and the right sub-pixel; a left transfer transistor (transfer transistor TX, paragraph 0086) and a left active region (paragraph 0066) on the left sub-pixel; a right transfer transistor (transfer transistor TX, paragraph 0086) and a right active region (paragraph 0066) on the right sub-pixel, as claimed.
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Choi (US Patent Application Publication 2017/0047363A1) is silent to teach a ground region in the substrate on one of the left sub-pixel and the right sub-pixel, and in contact with the well region; and a ground line that extends over the substrate between the plurality of pixel groups, wherein, on each of the plurality of pixels, the ground region is adjacent to the ground line.
In an analogous art, Choi (US Patent Application Publication 2022/0344393A1) teaches a ground region (ground region GR, Figure 1A-1B + 2A, paragraphs 0040) in the substrate on one of the left sub-pixel and the right sub-pixel, and in contact with the well region; and a ground line (First interconnection lines M1 + FD connection line FDC, Figure 2A + 6A, paragraph 0043) that extends over the substrate between the plurality of pixel groups, wherein, on each of the plurality of pixels, the ground region is adjacent to the ground line.
Therefore, it would have been obvious for some one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the teachings of Choi (US Patent Application Publication 2017/0047363A1) by incorporating a ground region in contact with the well region of the pixels and a ground line adjacent to the ground region as taught by Choi (US Patent Application Publication 2022/0344393A1) thereby providing a ground voltage to a transfer transistor preventing a short circuit issue from occurring therebetween.
Regarding claim 8, Choi (US Patent Application Publication 2017/0047363A1) and Choi (US Patent Application Publication 2022/0344393A1) teach the image sensor of claim 7, as claimed. Choi (US Patent Application Publication 2017/0047363A1) further teaches further comprising: a microlens (micro lens ML, Figure 4-5, paragraphs 0103-0104) on the left sub-pixel and the right sub-pixel of each of the plurality of pixels.
Choi (US Patent Application Publication 2017/0047363A1) is silent to teach a first color filter on one of the plurality of pixel groups; a second color filter on another of the plurality of pixel groups; and a third color filter on still another of the plurality of pixel groups. However, Choi (US Patent Application Publication 2022/0344393A1) teaches a first color filter (first color filter, Figure 3, paragraph 0053) on one of the plurality of pixel groups; a second color filter (second color filter, Figure 3, paragraph 0053) on another of the plurality of pixel groups; and a third color filter (third color filter, Figure 3, paragraph 0053) on still another of the plurality of pixel groups
Therefore, it would have been obvious for some one of ordinary skill in the art before the effective filing date of the claimed invention to have further modified the teachings of Choi (US Patent Application Publication 2017/0047363A1) by incorporating different color filters on different pixel groups as taught by Choi (US Patent Application Publication 2022/0344393A1) thereby having pixel groups of the sensor configured for specific wavelengths of light.
Regarding claim 9, Choi (US Patent Application Publication 2017/0047363A1) and Choi (US Patent Application Publication 2022/0344393A1) teach the image sensor of claim 7, as claimed. Choi (US Patent Application Publication 2022/0344393A1) further teaches wherein the ground line extends in the first direction (Figure 5, paragraph 0061).
Choi (US Patent Application Publication 2017/0047363A1) is silent to explicitly teach wherein the left transfer transistor is spaced apart in a first direction from the left active region, wherein the right transfer transistor is spaced apart in the first direction from the right active region. However, Choi (US Patent Application Publication 2017/0047363A1) does suggest the image sensor having multiple active regions and transistor structures (paragraph 0066) for the purpose of providing power to the transistor structures for device operation. Further, Choi (US Patent Application Publication 2022/0344393A1) teaches a transfer transistor on a first active region spaced apart from a second active region (Figure 1A-1B, paragraphs 0036 + 0041) for the purpose of powering different transistor structures.
Therefore, it would have been obvious for some one of ordinary skill in the art before the effective filing date of the claimed invention to have further modified the teachings of Choi (US Patent Application Publication 2017/0047363A1) and Choi (US Patent Application Publication 2022/0344393A1) by spacing the transfer transistors, which are already on active regions, from secondary active regions thereby spacing active regions with different transistor structures apart from each other, per design requirements.
Regarding claim 10, Choi (US Patent Application Publication 2017/0047363A1) and Choi (US Patent Application Publication 2022/0344393A1) teach the image sensor of claim 7, as claimed. Choi (US Patent Application Publication 2017/0047363A1) further teaches wherein each of the plurality of pixel groups comprises a first pixel (Figure 4), a second pixel (Figure 4), a third pixel (Figure 4), and a fourth pixel (Figure 4), wherein the first pixel and the second pixel are side by side in a first direction to constitute a first row (Figure 4), wherein the third pixel and the fourth pixel are side by side in the first direction to constitute a second row (Figure 4).
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Choi (US Patent Application Publication 2017/0047363A1) is silent to teach wherein the left transfer transistor and the right transfer transistor on the first pixel and the second pixel, are adjacent to the left transfer transistor and the right transfer transistor on the third pixel and the fourth pixel. However, Choi (US Patent Application Publication 2017/0047363A1) does teach each sub-pixel having a transfer transistor (paragraph 0086), such that where the general conditions of a claim are disclosed in the prior art, the particular placement of the transfer transistors of each pixel being adjacent to each other is a matter of design choice (MPEP 2144.04(VI)(C)).
Therefore, it would have been obvious for some one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the teachings of Choi (US Patent Application Publication 2017/0047363A1) and Choi (US Patent Application Publication 2022/0344393A1) by arranging the transfer transistors of each pixel adjacent to each other thereby having an image sensor per design requirements.
Regarding claim 27, Choi (US Patent Application Publication 2017/0047363A1) teaches an image sensor (auto-focus image sensor, Figures 2-5, Abstract), comprising: a substrate (substrate 20, Figures 4-5, paragraph 0093) having a first surface (first surface 20a, Figures 4-5, paragraph 0093) and a second surface (second surface 20b, Figure 5, paragraph 0093) that are opposite to each other, each of which comprises a plurality of pixels (unit pixels UP, Figures 4-5, paragraph 0093) arranged in a 2×2 matrix, and each of the plurality of pixels comprising a left sub-pixel and a right sub-pixel (sub-pixels Px, Figures 4-5, paragraphs 0095); a well region (first impurity region 32, Figure 5, paragraph 0095) in the substrate on each of the plurality of pixels, the well region connecting the left sub-pixel and the right sub-pixel to each other; a pixel separation part (pixel separation part 70 + sub-pixel separation part 80, Figures 4-5, paragraphs 0094 + 0096) that separates the plurality of pixels from each other and extends between the left sub-pixel and the right sub-pixel; a left photoelectric conversion region (second impurity region 34, Figure 5, paragraphs 0095) in the substrate on the left sub-pixel of each of the plurality of pixels; a right photoelectric conversion region (second impurity region 34, Figure 5, paragraphs 0095) in the substrate on the right sub-pixel of each of the plurality of pixels; a left transfer transistor on the second surface on each of the plurality of pixels (paragraph 0100); a right transfer transistor on the second surface on each of the plurality of pixels (paragraph 0100), as claimed.
Choi (US Patent Application Publication 2017/0047363A1) is silent to teach the substrate comprising a plurality of pixel groups; a first color filter on the first surface covering one of the plurality of pixel groups; a second color filter on the first surface covering another of the plurality of pixel groups; a third color filter on the first surface covering still another of the plurality of pixel groups; a plurality of microlenses respectively provided on the first color filter, the second color filter, and the third color filter and covering each of the plurality of pixels; a device isolation part adjacent to the second surface in the substrate, the device isolation part separating a left active region on the left sub-pixel from a right active region on the right sub-pixel; and a ground region in the substrate on one of the left sub-pixel and the right sub-pixel and in contact with the well region, wherein the ground region is provided in plural, and wherein the plurality of ground regions are adjacent to a corner of each of the plurality of pixel groups.
In an analogous art, Choi (US Patent Application Publication 2022/0344393A1) teaches the substrate comprising a plurality of pixel groups (pixel groups GPR1 - GPR3, Figure 3, paragraph 0053); a first color filter (first color filter, Figure 3, paragraph 0053) on the first surface covering one of the plurality of pixel groups; a second color filter (second color filter, Figure 3, paragraph 0053) on the first surface covering another of the plurality of pixel groups; a third color filter (third color filter, Figure 3, paragraph 0053) on the first surface covering still another of the plurality of pixel groups; a plurality of microlenses (micro lenses ML, Figure 3, paragraph 0049 + 0055) respectively provided on the first color filter, the second color filter, and the third color filter and covering each of the plurality of pixels; a device isolation part (shallow trench isolation layer STI, Figure 1A, paragraph 0035) adjacent to the second surface in the substrate, the device isolation part separating a left active region on the left sub-pixel from a right active region on the right sub-pixel (paragraph 0035); and a ground region (ground region GR, Figure 1A-1B + 2A, paragraphs 0040) in the substrate on one of the left sub-pixel and the right sub-pixel and in contact with the well region, wherein the ground region is provided in plural (Figure 12), and wherein the plurality of ground regions are adjacent to a corner of each of the plurality of pixel groups (Figure 12).
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Therefore, it would have been obvious for some one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the teachings of Choi (US Patent Application Publication 2017/0047363A1) with the teachings of Choi (US Patent Application Publication 2022/0344393A1) by having the pixels arranged in pixel groups with varying color filters and ground regions at the corners of the sub-pixels, thereby having an image sensor per design requirements.
Claim(s) 13-14 and 16-18 are rejected under 35 U.S.C. 103 as being unpatentable over Choi (US Patent Application Publication 2017/0047363A1) in view of Choi (US Patent Application Publication 2022/0344393A1) and Nakagawa (US Patent Application Publication 2024/0388817A1).
Regarding claim 13, Choi (US Patent Application Publication 2017/0047363A1) and Choi (US Patent Application Publication 2022/0344393A1) teach the image sensor of claim 10, as claimed.
Choi (US Patent Application Publication 2017/0047363A1) is silent to teach wherein the plurality of pixel groups comprise a first pixel group, a second pixel group, a third pixel group, and a fourth pixel group in a 2×2 arrangement. However, Choi (US Patent Application Publication 2022/0344393A1) shows an image sensor with pixel groups arranged in a 2×2 array (Figure 3).
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Therefore, it would have been obvious for some one of ordinary skill in the art before the effective filing date of the claimed invention to have further modified the teachings of Choi (US Patent Application Publication 2017/0047363A1) by grouping the plurality pixels into groups which are similarly arranged in a 2×2 array as taught by Choi (US Patent Application Publication 2022/0344393A1) thereby having an image sensor per design requirements.
Choi (US Patent Application Publication 2017/0047363A1) and Choi (US Patent Application Publication 2022/0344393A1) are silent to teach wherein the ground line is between the first pixel group and the second pixel group, and between the third pixel group and the fourth pixel group, wherein the ground region comprises a plurality of first ground regions on the fourth pixel of the first pixel group, the third pixel of the second pixel group, the second pixel of the third pixel group, and the first pixel of the fourth pixel group, and wherein the plurality of first ground regions are adjacent to the ground line.
In another analogous art, Nakagawa (US Patent Application Publication 2024/0388817A1) teaches wherein the ground line (ground level wiring 44-2) is between (Figure 6, paragraph 0053) the first pixel group (shared pixel unit 13c) and the second pixel group (shared pixel unit 13d), and between (Figure 6, paragraph 0053) the third pixel group (shared pixel unit 13a) and the fourth pixel group (shared pixel unit 13b), wherein the ground region comprises a plurality of first ground regions (P+ type region 28c-4, Figure 6, paragraph 0053) on the fourth pixel of the first pixel group, the third pixel of the second pixel group (P+ type region 28d-3, Figure 6, paragraph 0053), the second pixel of the third pixel group (P+ type region 28a-2, Figure 6, paragraph 0053), and the first pixel of the fourth pixel group (P+ type region 28b-1, Figure 6, paragraph 0053), and wherein the plurality of first ground regions are adjacent to the ground line (Figure 6, paragraph 0053), as claimed.
Therefore it would have been obvious for some one of ordinary skill in the art before the effective filing date of the claimed invention to have further modified the teachings of Choi (US Patent Application Publication 2017/0047363A1) and Choi (US Patent Application Publication 2022/0344393A1) by having the ground line placed between the first and second pixel groups and between the third and fourth pixel groups and the ground regions configured as taught by Nakagawa (US Patent Application Publication 2024/0388817A1) thereby providing a ground
Regarding claim 14, Choi (US Patent Application Publication 2017/0047363A1), Choi (US Patent Application Publication 2022/0344393A1), and Nakagawa (US Patent Application Publication 2024/0388817A1) teach the image sensor of claim 13, as claimed. Nakagawa (US Patent Application Publication 2024/0388817A1) further teaches wherein the plurality of first ground regions are spaced apart at a common distance from the ground line (Figure 6).
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Regarding claim 16, Choi (US Patent Application Publication 2017/0047363A1), Choi (US Patent Application Publication 2022/0344393A1), and Nakagawa (US Patent Application Publication 2024/0388817A1) teach the image sensor of claim 13, as claimed.
Choi (US Patent Application Publication 2017/0047363A1) is silent to teach further comprising a ground pattern on the substrate and in contact with the plurality of first ground regions, wherein the ground line extends over the ground pattern. However, Nakagawa (US Patent Application Publication 2024/0388817A1) further teaches a ground pattern on the substrate and in contact with the plurality of first ground regions (Figure 6), wherein the ground line extends over the ground pattern (Figure 6).
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Regarding claim 17, Choi (US Patent Application Publication 2017/0047363A1), Choi (US Patent Application Publication 2022/0344393A1), and Nakagawa (US Patent Application Publication 2024/0388817A1) teach the image sensor of claim 16, as claimed.
Nakagawa (US Patent Application Publication 2024/0388817A1) is silent to teach wherein the ground pattern has an octagonal shape or a cross shape when viewed in plan. However, no persuasive evidence of the significance of the shape of the ground pattern is found, such that having a ground pattern in an octagonal or cross shape is a matter of choice (MPEP 2144.04(IV)(B)).
Therefore, it would have been obvious for some one of ordinary skill in the art before the effective filing date of the claimed invention to have further modified the teachings of Choi (US Patent Application Publication 2017/0047363A1), Choi (US Patent Application Publication 2022/0344393A1), and Nakagawa (US Patent Application Publication 2024/0388817A1) by having a ground pattern in an octagonal or cross shape thereby connecting the plurality of ground regions to the ground line.
Allowable Subject Matter
Claims 11-12 and 18 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is an examiner’s statement of reasons for allowance: the prior art of record does not teach or suggest the combination of a first reset gate electrode that extends over the left active region of the first pixel; a second reset gate electrode that extends over the right active region of the first pixel; a third reset gate electrode that extends over the left active region of the second pixel; a first dummy gate electrode that extends over the right active region of the second pixel; a selection gate electrode that extends over the left active region of the third pixel; a source follower gate electrode that extends over the right active region of the third pixel and the left active region of the fourth pixel; and a second dummy gate that extends over the right active region of the fourth pixel, as claimed in claim 11.
The reset gate electrodes having a width smaller than the width of the source follower gate electrode, as claimed in claim 12.
The ground pattern and the first reset gate electrode having a common thickness, as claimed in claim 18.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to KAREEM M MOHAMED-ALY whose telephone number is (571)270-0312. The examiner can normally be reached 8am-5pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Leonard Chang can be reached at (571) 270-3691. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/KAREEM M MOHAMED-ALY/Examiner, Art Unit 2898
/Leonard Chang/Supervisory Patent Examiner, Art Unit 2898
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