DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Interpretation
The following is a quotation of 35 U.S.C. 112(f):
(f) Element in Claim for a Combination. – An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The claims in this application are given their broadest reasonable interpretation using the plain meaning of the claim language in light of the specification as it would be understood by one of ordinary skill in the art. The broadest reasonable interpretation of a claim element (also commonly referred to as a claim limitation) is limited by the description in the specification when 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is invoked.
As explained in MPEP § 2181, subsection I, claim limitations that meet the following three-prong test will be interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph:
(A) the claim limitation uses the term “means” or “step” or a term used as a substitute for “means” that is a generic placeholder (also called a nonce term or a non-structural term having no specific structural meaning) for performing the claimed function;
(B) the term “means” or “step” or the generic placeholder is modified by functional language, typically, but not always linked by the transition word “for” (e.g., “means for”) or another linking word or phrase, such as “configured to” or “so that”; and
(C) the term “means” or “step” or the generic placeholder is not modified by sufficient structure, material, or acts for performing the claimed function.
Use of the word “means” (or “step”) in a claim with functional language creates a rebuttable presumption that the claim limitation is to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites sufficient structure, material, or acts to entirely perform the recited function.
Absence of the word “means” (or “step”) in a claim creates a rebuttable presumption that the claim limitation is not to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is not interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites function without reciting sufficient structure, material or acts to entirely perform the recited function.
Claim limitations in this application that use the word “means” (or “step”) are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action. Conversely, claim limitations in this application that do not use the word “means” (or “step”) are not being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action.
Regarding claim 20, the limitation “means, applied to the substrate, for embedding the stack of one or more semiconductor dies and the first set of bond wires” is interpreted under 112(f) due to the use of the term “means”, the functional language “applied to the substrate, for embedding…”, and the lack of sufficient structure or material for performing the function. In light of the specification at [0037], the corresponding structure is interpreted as requiring a film layer.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-3, 6-7, 10, and 20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Lee (U.S. PGPub 2006/0220257).
Regarding claim 1, Lee teaches a semiconductor device (Fig. 2), comprising:
a substrate and a stack of one or more memory dies surface mounted to the substrate (10, 120, 130, [0008], [0054])
bond wires electrically coupling the stack of one or more memory dies to each other and the substrate (152/154, [0051]),
a film layer having a first surface positioned against the substrate, and a second surface opposite the first surface, the stack of one or more semiconductor dies and the bond wires being embedded within the film layer (161, [0046]), and
a component mounted to the second surface of the film layer (140, [0046]).
Regarding claim 2, Lee teaches wherein the component is a controller die ([0054], [0061]).
Regarding claim 3, Lee teaches wherein the bond wires comprise a first set of bond wires, the semiconductor device further comprising a second set of bond wires electrically coupling the controller die to the substrate (156, [0056]).
Regarding claim 6, Lee teaches an encapsulant for encapsulating the film layer and component (163, [0046]).
Regarding claim 7, Lee teaches wherein the film layer is a curable epoxy ([0053]).
Regarding claim 10, Lee teaches wherein the film layer is formed on the substrate in a shape and position at least as large as the component (Fig. 2).
Regarding claim 20, Lee teaches a semiconductor device (Fig. 2), comprising:
a substrate and a stack of one or more memory dies surface mounted to the substrate (10, 120, 130, [0008], [0054])
a first set of bond wires electrically coupling the stack of one or more memory dies to each other and the substrate (152/154, [0051]),
a film layer, the stack of one or more semiconductor dies and the bond wires being embedded within the film layer (161, [0046]), and
a controller die mounted to the second surface of the film layer (140, [0046], [0054], [0061]), and
a second set of bond wires electrically coupling the controller die to the substrate (156, [0056]).
Claims 12-19 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Ye (U.S. PGPub 2015/0221624).
Regarding claim 12, Ye teaches a semiconductor device (Fig. 10), comprising:
a substrate and a controller die directly mounted to the substrate (Fig. 4, 102, 114, [0030]),
a film layer having a first surface positioned against the substrate, and a second surface opposite the first surface, the controller die being embedded within the film layer (120, [0032]),
a stack of one or more memory dies mounted to the second surface of the film layer (130, [0039]) and
bond wires electrically coupling the stack of one or more memory dies to each other and the substrate (134, [0047]).
Regarding claim 13, Ye teaches wherein the bond wires comprise a first set of bond wires, the semiconductor device further comprising a second set of bond wires electrically coupling the controller die to the substrate (116, [0030]).
Regarding claim 14, Ye teaches wherein the controller die is flip-chip mounted to the substrate ([0030]).
Regarding claim 15, Ye teaches an encapsulant for encapsulating the film layer and stack of one or more memory dies (140, [0049]).
Regarding claim 16, Ye teaches wherein the film layer is a curable epoxy ([0042]-[0046]).
Regarding claim 17, Ye teaches wherein the film layer on the substrate is cured from an A-stage to a C-stage ([0042]-[0046]).
Regarding claim 18, Ye teaches wherein the film layer on the substrate is cured from an B-stage to a C-stage ([0042]-[0046]).
Regarding claim 19, Ye teaches a die attach film attaching a bottommost memory die of the stack of one or more memory dies to the second surface of the film layer ([0040]).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1 and 5 are rejected under 35 U.S.C. 103 as being unpatentable over Li (U.S. PGPub 2024/0304509) in view of Tomonaga (U.S. PGPub 2014/0159215).
Regarding claims 1 and 5, Li teaches a semiconductor device (Fig. 7B) comprising:
a substrate and a stack of one or more memory dies surface mounted to the substrate (19, 121, [0047], [0026], Claim 20),
bond wires electrically coupling the stack of one or more memory dies to each other and the substrate (14, [0050]),
a film layer having a first surface positioned against the substrate, and a second surface opposite the first surface, the stack of one or more semiconductor dies and the bond wires being embedded within the film layer (131, [0083]).
Li does not explicitly teach a component mounted to the second surface of the film layer, wherein the component is a spacer layer.
Tomonaga teaches a semiconductor package (Fig. 1) comprising a substrate and semiconductor die mounted to the substrate (13, [0027]) coupled to the substrate with bond wires (20, [0028]), a film layer having a first surface positioned against the substrate and a second surface opposite the first surface, the semiconductor dies and the bond wires being embedded within the film layer (191, [0030]), and a component mounted to the second surface, wherein the component is a spacer layer (18, [0027], [0031]).
Therefore it would have been obvious to a person having ordinary skill in the art before the time of the effective filing date to combine the teachings of Tomonaga with Li such that the device comprises a component mounted to the second surface of the film layer, wherein the component is a spacer layer for the purpose of providing a heat sink (Tomonaga, [0031]).
Claims 4 and 11 are rejected under 35 U.S.C. 103 as being unpatentable over Lee (U.S. PGPub 2006/0220257) in view of Kouchi (U.S. PGPub 2016/0351502).
Regarding claim 4, Lee does not explicitly teach wherein the component is a multiplexer.
Kouchi teaches a package comprising memory dies and a logic die ([0057]), wherein the logic die is a multiplexer ([0020], Fig. 1).
Therefore it would have been obvious to a person having ordinary skill in the art before the time of the effective filing date to combine the teachings of Kouchi with Lee such that the component is a multiplexer for the purpose of incorporating a multiplexer without increasing surface area (Kouchi, [0066]-[0067]).
Regarding claim 11, Lee does not explicitly teach wherein the semiconductor device is a flash memory package.
Kouchi teaches a package comprising memory dies and a logic die ([0057]), wherein the memory dies are flash memory ([0019], [0057], [0071]).
Therefore it would have been obvious to a person having ordinary skill in the art before the time of the effective filing date to combine the teachings of Kouchi with Lee such that the semiconductor device is a flash memory package for the purpose of providing the reduced cost of Lee for a flash memory package (Lee, [0055]).
Claims 8-9 are rejected under 35 U.S.C. 103 as being unpatentable over Lee (U.S. PGPub 2006/0220257) in view of Ye (U.S. PGPub 2015/0221624).
Regarding claim 8, Lee does not explicitly teach wherein the film layer on the substrate is cured from an A-stage to a C-stage.
Ye teaches one or more dies embedded in a film layer on a substrate and a component mounted to the top surface of the film layer (Figs. 4-6, 114, 120, 130, [0055]), wherein the film layer on the substrate is cured from an A-stage to a C-stage ([0034]-[0037], [0042], [0046]).
Therefore it would have been obvious to a person having ordinary skill in the art before the time of the effective filing date to combine the teachings of Ye with Lee such that the film layer on the substrate is cured from an A-stage to a C-stage for the purpose of forming the film layer of Lee (Ye, [0046]; Lee, [0053]).
Regarding claim 9, Lee does not explicitly teach wherein the film layer on the substrate is cured from a B-stage to a C-stage.
Ye teaches one or more dies embedded in a film layer on a substrate and a component mounted to the top surface of the film layer (Figs. 4-6, 114, 120, 130, [0055]), wherein the film layer on the substrate is cured from a B-stage to a C-stage ([0040]-[0046]]).
Therefore it would have been obvious to a person having ordinary skill in the art before the time of the effective filing date to combine the teachings of Ye with Lee such that the film layer on the substrate is cured from a B-stage to a C-stage for the purpose of forming the film layer of Lee (Ye, [0046]; Lee, [0053]).
Conclusion
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/ALIA SABUR/Primary Examiner, Art Unit 2812
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