DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
As per MPEP 2111 and 2111.01, the claims are given their broadest reasonable interpretation and the words of the claims are given their plain meaning consistent with the specification without importing claim limitations from the specification.
In responding to this Office action, the applicant is requested to include specific references (figures, paragraphs, lines, etc.) to the drawings/specification of the present application and/or the cited prior arts that clearly support any amendments/arguments presented in the response, to facilitate consideration of the amendments/arguments.
Priority
The present application, 18/738644, is a continuation of Application 18/061005, filed on December 2, 2022, which is a continuation of application 16/909632, filed on June 23, 2020. The claim for priority through this chain is acknowledged as properly supported under 35 U.S.C. § 120.
Information Disclosure Statement
The Information Disclosure Statements (IDS) submitted on June 10, 2024; July 3, 2024; August 21, 2024; January 9, 2025; and February 11, 2025 have been considered by the examiner.
Claim Objections
Claims 15, 19 objected to because of the following informalities:
Claim 15: “…coupled to the output of the scaling amplifier.” Scaling amplifier lacks an antecedent. In the interest of compact prosecution, the scaling amplifier and the second amplifier will be read as the same circuit.
Claim 19: Discloses generating “an amplified signal” but then references “the amplifier signal.” In the interest of compact prosecution, these signal well be read as the same signal.
Claim 19: Claim 13 discloses a “digit line.” Claim 19 then references “the bit line.” In the interest of compact prosecution, these two lines will be read as the same line.
Appropriate correction is required.
Claims 18 and 19 objected to as dependent claims depending from a claim from which they are separated by claims that do not also depend from that claim.
A series of singular dependent claims is permissible in which a dependent claim refers to a preceding claim which, in turn, refers to another preceding claim.
A claim which depends from a dependent claim should not be separated by any claim which does not also depend from said dependent claim. It should be kept in mind that a dependent claim may refer to any preceding independent claim. In general, applicant's sequence will not be changed. See MPEP § 608.01(n).
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claim 1 rejected on the ground of nonstatutory double patenting as being unpatentable over claim 1 of U.S. Patent No. 12,056,599. Although the claims at issue are not identical, they are not patentably distinct from each other.
Claim 1 of the present application reads:
1. An apparatus, comprising: a digit line; a number of access lines intersecting the digit line, wherein bits of a first number are stored serially on the digit line at respective intersections of the digit line and the number of access lines; and circuitry coupled to the digit line and configured to generate an output based on the bits of the first number and a number of signals driven on the number of access lines.
In comparison, Claim 1 of US 12,056,599 reads:
1. An apparatus, comprising: a bit line coupled to a plurality of memory elements of a memory array; a first set of word lines intersecting the bit line; a first set of memory elements of the plurality at intersections of the bit line and the first set of word lines, the first set of memory elements configured to store ordered bits of a first number; and a driver configured to drive a first set of signals on the first set of word lines, the first set of signals corresponding to ordered bits of a second number.
Both applications claim a digit/bit line, access/word lines intersecting the digit line, bits of a first number stored at the intersection of the digit and word lines, and driving signals across the word lines. The prior patented claim includes a driver generating signals over the word lines, which is absent in the present application. On the other hand, the present application discloses circuitry coupled to the digit line to receive and generate an output from the digit line. However, although each claim includes at least one element the other lacks, they remain obvious variants of each other.
A person having ordinary skill in the art, prior to the effective filing date of this application, would have found present Claim 1 obvious. The purpose of the claimed apparatus is driving a first number of word line signals to the digit line and determining stored weights at those points of intersection. Circuitry configured to drive those word line signals is an inherent requirement to that end.
Similarly, present Claim 1 merely states the expected output from the explicit drivers of the ‘599 claim. The signals “driven on the number of access lines” are the same signals the patented driver generates. Omitting an express ‘second number’ does not change the function; the output is still generated from stored bits plus driven word lines.
Independent Claims 9 and 13 are similarly rejected over similar analysis against patented claims 9 and 13 from US 12,056,599. Dependent Claims 2-8, 10-12, and 14-20 rejected as obvious variants of their respective claims and further objected to as depending from a rejected independent claim.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1-3, 7-16, and 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over US 10,998,037 B2 to Mohammed Zidan, et al. (hereafter Zidan) in view of US 10,748,603 B2 to Huseyin Ekin Sumbul, et al. (hereafter Sumbul).
Regarding Independent Claim 1, Zidan discloses an apparatus, comprising:
a digit line (Digit lines: Zidan, col.5:16);
a number of access lines intersecting the digit line (Word lines intersecting the digit line: Zidan, col.5:15), and
circuitry coupled to the digit line and configured to generate an output based on the bits of the first number and a number of signals driven on the number of access lines (Accumulators configured to determine an output based on the received values: Zidan, col.6:37-45).
Zidan discloses a memory apparatus as in claim 1, but the serial data is stored horizontally across word lines rather than serially on a vertical line of memory cells. Sumbul, however, discloses a memory array wherein bits of a first number are stored serially on the digit line at respective intersections of the digit line and the number of access lines (Data stored serially on the line of memory cells: Sumbul, col.2:53-55). Sumbul teaches weighting the rows by position results in a column voltage drop this is directly proportional to the binary stored word (Sumbul, col.5:59-62). Zidan’s architecture senses a combined bit line result after word line activity. Sumbul takes that concept a step further by mapping the multi-bit number into one column and weights the word-line signal by bit position, making the bit line voltage the binary number itself without further computation. It would have been obvious to one having ordinary skill in the art, before the effective filing date of this application, to use the efficient column inference of Sumbul with the architecture of Zidan, with a reasonable expectation of success. Both inventions are well known in the field of neural network architecture and the combination of known inventions with predictable results is obvious and not patentable.
Regarding Claim 2, Sumbul discloses the apparatus of claim 1, further comprising
bits of a third number stored, serially, on the digit line at respective intersections of the digit line and a second number of access lines, wherein the circuity is configured to generate another output based on the bits of the third number and a second number of signals driven on the second number of access lines (Inferring a second number from the same bit line by activating N word lines: Sumbul, col.3:42-50).
Regarding Claim 3, Zidan discloses the apparatus of claim 1, the circuitry further configured to:
generate a digital output in response to the output (Reading partial products on a first pass: Zidan, col.7:19-24);
shift the digital output (Shifting the output: Zidan, col.7:28-29); and
accumulate the shifted digital output to generate a first value equal to the product of the first number and a second number corresponding to the number of signals (Producing a dot product of the compute slice outputs: Zidan, col.7:37-40).
Regarding Claim 7, Zidan discloses the apparatus of claim 1, wherein
values of sequential signals (Sequential signals: Sumbul, col.2:12-16) in the number of signals double in value in ascending order (Signals values doubling with each successive signal: Sumbul, col.5:59-65).
Regarding Claim 8, Sumbul discloses the apparatus of claim 1, wherein
values of sequential signals in the number of signals double in an order from least significant bit (LSB) to most significant bit (MSB) (Disclosing the sequential signals doubling from LSB to MSB: Sumbul, col.5:59-65).
Regarding Independent Claim 9, Zidan discloses a method, comprising:
storing, serially, bits of a first number at intersections of a digit line (Digit lines: Zidan, col.5:16);
driving a first set of signals, which correspond to bits of a second number, on the first set of access lines (Driving word lines associated with a second number: Zidan, col.6:46-52); and
generating a number of output signals from the digit line (Accumulators configured to determine an output based on the received values: Zidan, col.6:37-45).
Zidan discloses a memory apparatus as in claim 9, but the serial data is stored horizontally across word lines rather than serially on a vertical line of memory cells. Sumbul, however, discloses a memory array wherein bits of a first number are stored serially on the digit line at respective intersections of the digit line and the number of access lines (Data stored serially on the line of memory cells: Sumbul, col.2:53-55). Sumbul teaches weighting the rows by position results in a column voltage drop this is directly proportional to the binary stored word (Sumbul, col.5:59-62). Zidan’s architecture senses a combined bit line result after word line activity. Sumbul takes that concept a step further by mapping the multi-bit number into one column and weights the word-line signal by bit position, making the bit line voltage the binary number itself without further computation. It would have been obvious to one having ordinary skill in the art, before the effective filing date of this application, to use the efficient column inference of Sumbul with the architecture of Zidan, with a reasonable expectation of success. Both inventions are well known in the field of neural network architecture and the combination of known inventions with predictable results is obvious and not patentable.
Regarding Claim 10, Sumbul discloses the method of claim 9, further comprising:
storing, serially, bits of a third number at intersections of the digit line and a second set of access lines (Memory cells including multiple words: Sumbul, col.3:26-30);
driving a second set of signals, which correspond to bits of a fourth number, on the second set of access lines (Different registers driving different word lines and outputting a different output: Zidan, col.6:46-52); and
generating additional output signals from the digit line (Accumulators configured to determine an output based on the received values: Zidan, col.6:37-45).
Regarding Claim 11, Zidan discloses the method of claim 9, further comprising:
generating a digital signal in response to receipt of an output signal of the number of output signals (Generating a compute slice associated with the first digital signal: Zidan, col.7:19-24);
shifting the digital signal (Shifting the signal: Zidan, col.7:28-29); and
accumulating the shifted digital signal to generate a first value (Outputting a first value following the data shift: Zidan, col.7:37-40).
Regarding Claim 12, Zidan discloses the method of claim 9, further comprising
generating a first value equal to the product of the first number and the second number (Producing a dot product of resulting numbers: Zidan, col.7:37-40).
Regarding Independent Claim 13, Zidan discloses a memory system, comprising:
at least one memory device comprising (A memory cell array: Zidan, Figure 1):
a digit line (Digit lines: Zidan, col.5:16);
a first set of access lines intersecting the digit line (Word lines intersecting the digit line: Zidan, col.5:15); and
circuitry coupled to the digit line and configured to generate,
responsive to a first set of signals corresponding to bits of an input of the neural network being driven on the first set of access lines (Word lines driving memory bit value reads: Zidan, col.6:46-52),
a value based on the bits of the synaptic weight and the bits of the input of the neural network (Accumulators configured to determine an output based on the received values: Zidan, col.6:37-45).
Zidan discloses a memory apparatus as in claim 13, but the serial data is stored horizontally across word lines rather than serially on a vertical line of memory cells. Sumbul, however, discloses a memory array wherein a number of memory elements for storing bits of a synaptic weight of a neural network, each intersection of the digit line and the first set of access lines including a memory element of the number of memory elements (Data stored serially on the line of memory cells: Sumbul, col.2:53-55). Sumbul teaches weighting the rows by position results in a column voltage drop this is directly proportional to the binary stored word (Sumbul, col.5:59-62). Zidan’s architecture senses a combined bit line result after word line activity. Sumbul takes that concept a step further by mapping the multi-bit number into one column and weights the word-line signal by bit position, making the bit line voltage the binary number itself without further computation. It would have been obvious to one having ordinary skill in the art, before the effective filing date of this application, to use the efficient column inference of Sumbul with the architecture of Zidan, with a reasonable expectation of success. Both inventions are well known in the field of neural network architecture and the combination of known inventions with predictable results is obvious and not patentable.
Regarding Claim 14, Zidan discloses the memory system of claim 13, wherein the at least one memory device further comprises:
a second set of memory elements at the intersection of the digit line and a second set of access lines (Inferring a second number from the same bit line by activating N word lines: Sumbul, col.3:42-50);
wherein bits of a second synaptic weight of the neural network are stored in the second set of memory elements (Determining the partial product for select bits: Zidan, col.9:16-19); and
wherein the circuitry is further configured to generate,
responsive to a second set of signals driven on the second set of access lines intersecting the bit line (Responsive to a sequence of activation codes: Zidan, col.10:32-35),
a second value based on the bit of the second synaptic weight and the second set of signals (Resulting in a second partial value: Zidan, col.10:35-40),
wherein the second set of signals correspond to ordered bits of a second input or a second error input of the neural network (The second signals corresponding to an ordered matrix X: Zidan, col.9:55-59).
Regarding Claim 15, Zidan discloses the memory system of claim 13, wherein
the value is a product of the synaptic weight and the input (Determining output value as a dot product of input and data weight: Zidan, col.7:61-8:8; see also, Zidan, Figure 8).
Regarding Claim 16, Zidan discloses the memory system of claim 13, wherein the circuitry comprises:
a first circuit configured to receive signals corresponding to the signals on the digit line (Sense amplifier receiving the first signal: Zidan, col.9:16-18);
a second circuit configured to shift an output of the first circuit (Shift circuit: Zidan, col.9:21-24); and
a third circuit configured to receive an output from the second circuit and generate the value or a second value (Outputting a combined dot product: Zidan, col.9:52-55).
Regarding Claim 20, Sumbul discloses the memory system of claim 13, wherein one of:
values of signals in the first set of signals double in value in ascending order (Signals values doubling with each successive signal: Sumbul, col.5:59-65); and
the values of signals in the first set of signals double in an order from least significant bit (LSB) to most significant bit (MSB) (Disclosing the sequential signals doubling from LSB to MSB: Sumbul, col.5:59-65).
Claim(s) 4-5 and 17-18 is/are rejected under 35 U.S.C. 103 as being unpatentable over US 10,998,037 B2 to Mohammed Zidan, et al. (hereafter Zidan) and US 10,748,603 B2 to Huseyin Ekin Sumbul, et al. (hereafter Sumbul), further in view of US 10,860,682 B2 to Phil Knag, et al. (hereafter Knag).
Regarding Claim 4, Zidan discloses the apparatus of claim 3, but fails to disclose the further limitations of Claim 4. Knag, however, discloses an apparatus as in Claim 3, wherein the circuitry is configured to:
receive a first output signal of the output (Circuitry receiving the first output: Knag, col.6:11-16);
provide a second signal that is a fraction of the first output signal (Dividing the output voltage by a fixed percentage: Knag, col.11:25-30); and
integrate the second signal with a second output signal of the number of output signals of the digit line (The fractional output accumulated with additional output: Knag, col.2:61-3:3).
Knag teaches performing the division and combination directly on the outputs allows the operation to be performed either on the digital output or completely in the analog domain and can be performed at low cost by capacitors (Knag, col.11:14-35). Therefore, it would have been obvious to one having ordinary skill in the art, before the effective filing date of this application, to combine the flexible, low-cost division method of Knag with the network architecture of Zidan, with a reasonable expectation of success. Both inventions are well known in the field of efficient neural network operation and the combination of known inventions with predictable results is obvious and not patentable.
Regarding Claim 5, Zidan discloses the apparatus of claim 3, but fails to disclose the further limitations of Claim 5. Knag, however, discloses an apparatus as in Claim 3, wherein the circuitry comprises:
a first amplifier having an input coupled to the digit line (Y0-4 being output analog voltages from the bitlines: Knag, col.6:11-14);
a second amplifier having at least one input coupled to an output of the first amplifier (A second amplifier coupled to the first amplifier: Knag, col.11:25-30);
a signal divider having an input coupled to an output of the second amplifier (A divider coupled to the output: Knag, col.11:30-35) and an output coupled to the at least one input of the second amplifier (Knag does not specifically disclose the output of the divider fed back into the second amplifier. There are a limited number of predictable combinations for this circuit, however, and this configuration represents the simplest method of closing the necessary feedback loop. Selecting from a limited number of predictable solutions with a reasonable expectation of success is obvious and not patentable: MEPE § 2143.I(E)); and
an analog-to-digital converter (ADC) coupled to the output of the scaling amplifier (Analog conversion taking place after the summing/division: Knag, col.11:14-17).
Knag teaches performing the division and combination directly on the outputs allows the operation to be performed either on the digital output or completely in the analog domain and can be performed at low cost by capacitors (Knag, col.11:14-35). Therefore, it would have been obvious to one having ordinary skill in the art, before the effective filing date of this application, to combine the flexible, low-cost division method of Knag with the network architecture of Zidan, with a reasonable expectation of success. Both inventions are well known in the field of efficient neural network operation and the combination of known inventions with predictable results is obvious and not patentable.
Regarding Claim 17, Zidan discloses the memory system of claim 13, but fails to disclose the further limitations of Claim 17. Knag, however, discloses a memory system as in Claim 14, wherein the circuitry comprises:
a sense amplifier coupled to the digit line and configured to generate an amplified signal (Y0-4 being output analog voltages from the bitlines: Knag, col.6:11-14);
a scaling unit configured to receive the amplified signal and generate a scaled output (A divider coupled to the output: Knag, col.11:30-35); and
an analog-to-digital converter (ADC) configured to receive the scaled output and generate the value equal to the product of the synaptic weight and the input (Analog conversion taking place after the summing/division: Knag, col.11:14-17).
Knag teaches performing the division and combination directly on the outputs allows the operation to be performed either on the digital output or completely in the analog domain and can be performed at low cost by capacitors (Knag, col.11:14-35). Therefore, it would have been obvious to one having ordinary skill in the art, before the effective filing date of this application, to combine the flexible, low-cost division method of Knag with the network architecture of Zidan, with a reasonable expectation of success. Both inventions are well known in the field of efficient neural network operation and the combination of known inventions with predictable results is obvious and not patentable.
Regarding Claim 18, Zidan discloses the memory system of claim 15, but fails to disclose the further limitations of Claim 18. Knag, however, discloses a memory system as in Claim 15, wherein the circuitry is configured to:
scale a first signal from the digit line (Dividing the output voltage by a fixed percentage: Knag, col.11:25-30); and
integrate the scaled first signal with a second signal from the digit line (The fractional output accumulated with additional output: Knag, col.2:61-3:3).
Knag teaches performing the division and combination directly on the outputs allows the operation to be performed either on the digital output or completely in the analog domain and can be performed at low cost by capacitors (Knag, col.11:14-35). Therefore, it would have been obvious to one having ordinary skill in the art, before the effective filing date of this application, to combine the flexible, low-cost division method of Knag with the network architecture of Zidan, with a reasonable expectation of success. Both inventions are well known in the field of efficient neural network operation and the combination of known inventions with predictable results is obvious and not patentable.
Claim(s) 6 and 19 is/are rejected under 35 U.S.C. 103 as being unpatentable over US 10,998,037 B2 to Mohammed Zidan, et al. (hereafter Zidan) and US 10,748,603 B2 to Huseyin Ekin Sumbul, et al. (hereafter Sumbul), further in view of US 11,430,491 B2 to Jaw-Juinn Horng, et al. (hereafter Horng).
Regarding Claim 6, Zidan discloses the apparatus of claim 3, including a digital accumulator coupled to a second output of the ADC (The digital accumulator coupled to the output of the ADC: Zidan, col.1:62-2:7), but fails to disclose the further limitations of Claim 6. Horng, however, discloses an apparatus as in Claim 3, wherein the circuitry comprises:
an amplifier having an input coupled to the digit line (A current comparator coupled to the output of the bitlines: Horng, col.3:22-28);
an analog-to-digital converter (ADC) coupled to an output of the amplifier (An analog-to-digital converter coupled to the output of the amplifier: Horng, col.3:26-33);
a carry register coupled to a first output of the ADC (A reference current circuit, carry circuit analog, coupled to the output of the ADC: Horng, col.6:23-29 and Horng, Figure 7);
a carry digital-to-analog converter (DAC) coupled to an output of the carry register (DAC circuit 132 included in the Reference Current Circuit 130: Horng, Figure 7).
Zidan discloses inferring digital partial products and shift-accumulates them to a dot product to avoid exceeding circuit limits, including a digital accumulator coupled to a second output of the ADC (The digital accumulator coupled to the output of the ADC: Zidan, col.1:62-2:7). Knag (See Claims 4&5) discloses an alternative method, wherein the output is divided during the accumulation process. Claim 6 introduces another known method of maintaining circuit boundaries during the accumulation process, splitting the ADC and feeding some bits to the accumulator and others to the DAC circuit to feed back into the register. Horng discloses this last method, disclosing a known method for carrying the analog data without exceeding the bounds of the circuit. Therefore, it would have been obvious to one having ordinary skill in the art, before the effective filing date of this application, to combine the carry-register feedback loop of Horng with the architecture of Zidan, with a reasonable expectation of success. Both inventions are well known in the field of neural network architecture and the combination of known inventions with predictable results is obvious and not patentable.
Regarding Claim 19, Zidan discloses the memory system of claim 15, but fails to disclose the further limitations of Claim 19. Horng, however, discloses a memory system as in Claim 15, wherein the circuitry comprises:
a first circuit coupled to the bit line and configured to generate an amplified signal (A current comparator coupled to the output of the bit lines: Horng, col.3:22-28);
a second circuit configured to receive the amplifier signal and generate a digital signal (An analog-to-digital converter coupled to the output of the amplifier: Horng, col.3:26-33);
a third circuit configured to receive a first portion of the digital signal and a second portion of the digital signal (A reference current circuit, carry circuit analog, coupled to the output of the ADC: Horng, col.6:23-29 and Horng, Figure 7); and
a fourth circuit coupled to an output of the third circuit and configured to convey an analog signal to the bit line (DAC circuit 132 included in the Reference Current Circuit 130: Horng, Figure 7).
Zidan discloses a digital partial products and shift-accumulates them to a dot product to avoid exceeding circuit limits. Knag (See Claims 4&5) discloses an alternative method, wherein the output is divided during the accumulation process. Claim 6 introduces another known method of maintaining circuit boundaries during the accumulation process, splitting the ADC and feeding some bits to the accumulator and others to the DAC circuit to feed back into the register. Horng discloses this last method, disclosing a known method for carrying the analog data without exceeding the bounds of the circuit. Therefore, it would have been obvious to one having ordinary skill in the art, before the effective filing date of this application, to combine the carry-register feedback loop of Horng with the architecture of Zidan, with a reasonable expectation of success. Both inventions are well known in the field of neural network architecture and the combination of known inventions with predictable results is obvious and not patentable.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
US 11,055,026 B2 to Isom Crawford, Jr.: Disclosing a memory array configured to perform logical operations on data stored in the array through a register.
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/CHRISTOPHER LANE REECE/ Examiner, Art Unit 2824
/DOUGLAS KING/ Primary Examiner, Art Unit 2824
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