Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 6/10/2024 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the Examiner.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 4-10, and 14-18 are rejected under 35 U.S.C. 103 as being unpatentable over Lin et al US 20230363182 A1 in view of Yang US 20050184371 A1. Lin et al will be referenced to as Lin henceforth.
Regarding Claim 1,
Lin teaches:
“A semiconductor package (FIG. 36A), comprising:
a lower semiconductor package (lower chip package 317, [0428]); and
an upper semiconductor package on the lower semiconductor package (upper chip package 317, [0428]), wherein the lower semiconductor package includes:
a first substrate (a backside interconnection scheme 79, [0038]); wherein the first substrate includes a plurality of first pads (annotated FIG. 36A #1), wherein the upper semiconductor package includes a plurality of connection terminals on a lower portion of the upper semiconductor package (solder bumps 516, [0429]), wherein the plurality of connection terminals are respectively attached to the plurality of first pads (FIG. 36A).”
Lin doesn’t substantially teach:
“and
a dielectric pattern on a top surface of the first substrate, wherein the dielectric pattern includes a plurality of stepwise openings that expose the plurality of first pads, wherein a cross-section of each stepwise opening of the plurality of stepwise openings has a pair of stepwise structures, wherein each stepwise structure of the pair of stepwise structures includes:
a first lateral surface;
a second lateral surface; and
a first bottom surface that connects the first lateral surface with the second lateral surface, wherein the first lateral surface is connected with a top surface of a first pad of the plurality of first pads, wherein the second lateral surface is connected with a top surface of the dielectric pattern,”
However, Yang teaches:
“and
a dielectric pattern on a top surface of the first substrate (Yang: solder mask layer 230, [0018]), FIG. 3), wherein the dielectric pattern includes a plurality of stepwise openings that expose the plurality of first pads (Yang: stepped opening 232, [0019], FIG. 3), wherein a cross-section of each stepwise opening of the plurality of stepwise openings has a pair of stepwise structures (Yang: FIG. 3: The opening has a stepwise structure on the left end of the opening and another stepwise structure on the right end of the opening.), wherein each stepwise structure of the pair of stepwise structures includes:
a first lateral surface (Yang: annotated FIG. 3 #1);
a second lateral surface (Yang: annotated FIG. 3 #1); and
a first bottom surface that connects the first lateral surface with the second lateral surface (Yang: annotated FIG. 3 #1), wherein the first lateral surface is connected with a top surface of a first pad of the plurality of first pads (Yang: annotated FIG. 3 #1), wherein the second lateral surface is connected with a top surface of the dielectric pattern (Yang: annotated FIG. 3 #1),”
It would have been obvious to one with ordinary skill in the art before the effective filing
date of the invention to recognize that the device of Lin is modifiable in view of Yang by incorporating the solder mask of Yang into Lin .
This is because the stepped opening of the solder mask layer of Yang provides better connection strength between a bump and a contact pad (Yang: [0012]). This improves the reliability of a package structure.
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Regarding Claim 4,
Lin/Yang teaches:
“The semiconductor package of claim 1, wherein the dielectric pattern includes one of a photo-imageable dielectric (PID) or a solder resist (Yang: [0018]: “Solder mask” and “solder resist” are synonyms.).”
Regarding Claim 5,
Lin/Yang teaches:
“The semiconductor package of claim 1, wherein the upper semiconductor package includes a second pad on a lower portion of the upper semiconductor package (Lin: annotated FIG. 36A #1: an upper pad is a second pad.), and wherein a connection terminal is in contact with the first pad and the second pad (Lin: annotated FIG. 36A #1).”
Regarding Claim 6,
Lin/Yang teaches:
“The semiconductor package of claim 1, wherein the lower semiconductor package includes:
a second substrate below the first substrate (Lin: frontside interconnection scheme for a logic drive or device (FISD) 101, [0390]); and
a first semiconductor chip on the second substrate (Lin: FPIC chiplet 200, [0227]: An FPIC chip is a kind of logic chip.), the first semiconductor chip being between the first substrate and the second substrate (Lin: FIG. 36A), wherein the upper semiconductor package includes:
a package substrate (Lin: circuit board 513, [0428], FIG. 36A: 513 may be a BGA substrate.); and
a second semiconductor chip on the package substrate, and wherein the first semiconductor chip and the second semiconductor chip are different types of semiconductor chips (Lin: memory IC chip 350, [0428], FIG. 36A: A: A memory chip is not logic chip.).”
Regarding Claim 7,
Lin/Yang teaches:
“The semiconductor package of claim 6, wherein the first semiconductor chip is a logic chip, and the second semiconductor chip is a memory chip (Lin: [0227], [0428]: 350 is a memory chip. 200 is a logic chip.).”
Regarding Claim 8,
Lin/Yang teaches:
“A semiconductor package (Lin: FIG. 36A), comprising:
a lower semiconductor package (Lin: lower chip package 317, [0428]); and
an upper semiconductor package on the lower semiconductor package (Lin: upper chip package 317, [0428]), wherein the lower semiconductor package includes a first substrate (Lin: backside interconnection scheme 79, [0390), wherein the first substrate includes:
a plurality of wiring patterns (Lin: interconnection metal layers 27, [0350]);
a plurality of pads on the plurality of wiring patterns (Lin: annotated FIG. 36A #1); and
a dielectric pattern that covers the plurality of wiring patterns (Yang: solder mask layer 230, [0018], FIG. 3), wherein the dielectric pattern includes:
a first opening that exposes a pad of the plurality of pads (Yang: second opening 232b, [0021], FIG. 3); and
a second opening on the first opening (Yang: first opening 232a, [0021], FIG. 3), wherein the first opening is closer than the second opening to a top surface of the pad (Yang: FIG. 3), wherein the first opening has a first width in a first direction, the first direction being parallel to a top surface of the first substrate (Yang: FIG. 3: D3 is parallel to the top surface of 210.), wherein the second opening has a second width in the first direction (Yang: D2, [0021], FIG. 3), wherein the first width is less than the second width (Yang: [0021], FIG. 3).”
Regarding Claim 9,
Lin/Yang teaches:
“The semiconductor package of claim 8, wherein the lower semiconductor package includes:
a second substrate below the first substrate (Lin: frontside interconnection scheme for a logic drive or device (FISD) 101, [0390]); and
a first semiconductor chip on the second substrate (Lin: FPIC chiplet 200, [0227]: An FPIC chip is a kind of logic chip.), the first semiconductor chip being between the first substrate and the second substrate (Lin: FIG. 36A), wherein the first width increases as a distance from the pad to the first opening in a second direction increases (Yang: FIG. 3), the second direction being perpendicular to the top surface of the first substrate (Yang: FIG. 3).”
Regarding Claim 10,
Lin/Yang teaches:
“The semiconductor package of claim 9, wherein the second width increases as a distance from the pad to the second opening in the second direction increases (Yang: FIG. 3).”
Regarding Claim 14,
Lin/Yang teaches:
“The semiconductor package of claim 8, wherein the dielectric pattern includes one of a photo-imageable dielectric (PID) or a solder resist (Yang: [0018]: “Solder mask” and “solder resist” are synonyms.).”
Regarding Claim 15,
Lin/Yang teaches:
“The semiconductor package of claim 8, wherein the upper semiconductor package includes:
a package substrate (Lin: circuit board 513, [0428], FIG. 36A: 513 may be a BGA substrate.);
a second semiconductor chip on the package substrate (Lin: memory IC chip 350, [0428], FIG. 36A); and
a plurality of connection terminals on a bottom surface of the package substrate (Lin: solder bumps 516, [0429]), wherein the plurality of connection terminals are respectively in contact with the plurality of pads (Lin: annotated FIG. 36A #1).”
Regarding Claim 16,
Lin/Yang teaches:
“A semiconductor package (Lin: FIG. 36A), comprising:
a lower semiconductor package (Lin: lower chip package 317, [0428]); and
an upper semiconductor package on the lower semiconductor package (Lin: upper chip package 317, [0428]), wherein the lower semiconductor package includes:
a lower redistribution substrate (Lin: frontside interconnection scheme for a logic drive or device (FISD) 101, [0390]);
an upper redistribution substrate on the lower redistribution substrate (Lin: a backside interconnection scheme 79, [0038]); and
a logic chip between the lower redistribution substrate and the upper redistribution substrate (Lin: FPIC chiplet 200, [0227]: An FPIC chip is a kind of logic chip.), wherein the upper redistribution substrate includes:
a plurality of dielectric layers (Lin: polymer layers 519. [0428], FIG. 36A);
a plurality of wiring patterns in the plurality of dielectric layers (Lin: metal layers 518, [00428]);
a plurality of pads on the plurality of wiring patterns (Lin: annotated FIG. 36A #1); and
a dielectric pattern that covers the plurality of wiring patterns (Yang: solder mask layer 230, [0018], FIG. 3), wherein the dielectric pattern includes:
a first opening that exposes a pad of the plurality of pads (Yang: second opening 232b, [0021], FIG. 3); and
a second opening on the first opening (Yang: first opening 232a, [0021], FIG. 3), wherein the first opening is closer than the second opening to a top surface of the pad (Yang: FIG. 3), wherein a cross-section of each opening of the first opening and the second opening has a trapezoidal shape (Yang: FIG. 3), wherein the first opening has a first diameter (Yang: D3, FIG. 3: D3 is parallel to the top surface of 210.), wherein the second opening has a second diameter (Yang: D2, [0021], FIG. 3), wherein the second diameter is greater than the first diameter (Yang: [0021], FIG. 3), wherein the first diameter increases as a distance from the top surface of the pad to the first opening increases (Yang: FIG. 3), wherein the second diameter increases as a distance from the top surface of the pad to the second opening increases (Yang: FIG. 3), and wherein the upper semiconductor package includes:
a package substrate (Lin: circuit board 513, [0428], FIG. 36A: 513 may be a BGA substrate.); and
a memory chip on the package substrate (Lin: memory IC chip 350, [0428], FIG. 36A).”
Regarding Claim 17,
Lin/Yang teaches:
“The semiconductor package of claim 16, wherein the dielectric pattern includes one of a photo-imageable dielectric (PID) or a solder resist (Yang: [0018]: “Solder mask” and “solder resist” are synonyms.).”
Regarding Claim 18,
Lin/Yang teaches:
“The semiconductor package of claim 16, comprising a connection substrate on a top surface of the lower redistribution substrate, wherein the connection substrate defines a cavity (Lin: polymer layer 92, [0390], FIG. 36A), and wherein the logic chip is in the cavity (Lin: FIG. 36A).”
Regarding Claim 19,
Lin/Yang teaches:
“The semiconductor package of claim 16, comprising:
a molding layer that covers the lower redistribution substrate (Lin: polymer layer 92, [0390], FIG. 36A); and
a conductive pillar that extends through the molding layer and connects the lower redistribution substrate with the upper redistribution substrate (Lin: through package vias (TPVs) 158, [0390], FIG. 36A), wherein the conductive pillar is spaced apart in a first direction from the logic chip (Lin: FIG. 36A), the first direction being parallel to a top surface of the lower redistribution substrate (Lin: FIG. 36A).”
Claims 2-3 are rejected under 35 U.S.C. 103 as being unpatentable over Lin/Yang as applied to claims 1, 4-10, and 14-18 above, and further in view of Akram et al US 6040239 A. Akram et al will be referenced to as Akram henceforth.
Regarding Claim 2,
Lin/Yang teaches:
“The semiconductor package of claim 1,”
Lin/Yang doesn’t substantially teach:
“wherein a first angle is between the first lateral surface and the top surface of the first pad, and the first angle is in a range of 135° to 150°”
However, Akram substantially teaches:
“wherein a first angle is between the first lateral surface and the top surface of the first pad, and the first angle is in a range of 135° to 150° (Akram: col 7 lines 48-57, FIGs. 6A-7B)”
It would have been obvious to one with ordinary skill in the art before the effective filing
date of the invention to recognize that the device of Lin/Yang is modifiable in view of Akram by optimizing the slope of the walls of the solder mask such that the connection terminal does not stick to the walls of the solder mask and the connection terminal is properly aligned.
This is because the combination of Lin/Yang and Akram does not appear to expressly state the first angle is in a range of 135° to 150°; however, where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art. See MPEP §2144.05 II A; see also In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955).
In the case at hand, Akram teaches the general conditions of claim 2. Specifically, Akram teaches that the variable of the slope of the sidewalls of a solder mask is changed to result in the desired effect of stickiness of sidewalls to a connection terminal and the alignment of a terminal. Therefore, one having ordinary skill in the at the time the application at hand would find it obvious to discover the optimum or workable ranges of the slopes of the sidewalls of the solder mask and therefore the first angle, since the contact pad is horizontal, using only routine skill in the art.
Regarding Claim 3,
Lin/Yang/Akram substantially teaches:
“The semiconductor package of claim 2, wherein a second angle is between the first lateral surface and the first bottom surface, and the second angle is in a range of 135° to 150° (Akram: col 7 lines 48-57, FIGs. 6A-7B).”
It would have been obvious to one with ordinary skill in the art before the effective filing
date of the invention to recognize that the device of Lin/Yang is modifiable in view of Akram by optimizing the slope of the walls of the solder mask such that the connection terminal does not stick to the walls of the solder mask and the connection terminal is properly aligned.
This is because the combination of Lin/Yang and Akram does not appear to expressly state the first angle is in a range of 135° to 150°; however, where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art. See MPEP §2144.05 II A; see also In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955).
In the case at hand, Akram teaches the general conditions of claim 3. Specifically, Akram teaches that the variable of the slope of the sidewalls of a solder mask is changed to result in the desired effect of stickiness of sidewalls to a connection terminal and the alignment of a terminal. Therefore, one having ordinary skill in the at the time the application at hand would find it obvious to discover the optimum or workable ranges of the slopes of the sidewalls of the solder mask and therefore the second angle, since the first bottom surface is horizontal, using only routine skill in the art.
Claims 11-13 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Lin/Yang as applied to claims 1, 4-10 and 14-18 above, and further in view of Farnworth et al US 5962921 A. Farnworth et al will be referenced to as Farnworth henceforth.
Regarding Claim 11,
Lin/Yang teaches:
“The semiconductor package of claim 8,”
Lin/Yang doesn’t substantially teach:
“wherein the first width is 80% to 95% of the second width”
However, Farnworth substantially teaches:
“wherein the first width is 80% to 95% of the second width (Farnworth: col 7 lines 6-25, col 8 lines 39-45, FIG. 3A, 4B: The width of the peripheral edges 38G and 38GG must both be a bit less than the average minimum diameter of a bump so that the bump may be electrically contacted and minimally deformed. Further, in order for FIG. 4B to be illustrated, the first width must be less than the second width. Therefore, one of ordinary skill in the art would consider the second width to be nearly the same width as the first width.)”
It would have been obvious to one with ordinary skill in the art before the effective filing
date of the invention to recognize that the device of Lin/Yang is modifiable in view of Farnworth by optimizing the sizes of the first width and second width to minimally deform a connection terminal while also electrically contacting the connecting terminal by breaking any native oxide.
This is because the combination of Lin/Yang and Farnworth does not appear to expressly state that the first width is 80% to 95% the width of the second width; however, where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art. See MPEP §2144.05 II A; see also In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955).
In the case at hand, Farnworth teaches the general conditions of claim 11. Specifically, Farnworth teaches that the variable width of the peripheral edges is changed to result in the desired effect of minimally deforming a connection terminal while also electrically contacting the connecting terminal by breaking any native oxide. Therefore, one having ordinary skill in the at the time the application at hand would find it obvious to discover the optimum or workable ranges of the first width being 80% to 95% the width of the second width using only routine skill in the art.
Regarding Claim 12,
Lin/Yang teaches:
“The semiconductor package of claim 8,”
Lin/Yang doesn’t substantially teach:
“wherein the first width is in a range of 190 μm to 210 μm, and the second width is in a range of 210 μm to 225 μm.”
However, Farnworth substantially teaches:
“wherein the first width is in a range of 190 μm to 210 μm, and the second width is in a range of 210 μm to 225 μm (Farnworth: col 7 lines 6-25, col 8 lines 39-45, FIG. 3A, 4B: The width of the peripheral edges 38G and 38GG must both be a bit less than the average minimum diameter of a bump so that the bump may be electrically contacted and minimally deformed. Further, in order for FIG. 4B to be illustrated, the first width must be less than the second width. Therefore, one of ordinary skill in the art would be motivated for the second width to be nearly the same width as the first width.).”
It would have been obvious to one with ordinary skill in the art before the effective filing
date of the invention to recognize that the device of Lin/Yang is modifiable in view of Farnworth by optimizing the sizes of the first width and second width to minimally deform a connection terminal while also electrically contacting the connecting terminal by breaking any native oxide.
This is because the combination of Lin/Yang and Farnworth does not appear to expressly state that the first width in a range of 190 μm to 210 μm and the second width is in a range of and the second width is in a range of 210 μm to 225 μm; however, where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art. See MPEP §2144.05 II A; see also In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955).
In the case at hand, Farnworth teaches the general conditions of claim 12. Specifically, Farnworth teaches that the variable width of the peripheral edges is changed to result in the desired effect of minimally deforming a connection terminal while also electrically contacting the connecting terminal by breaking any native oxide. Therefore, one having ordinary skill in the at the time the application at hand would find it obvious to discover the optimum or workable ranges of the first width being 80% to 95% the width of the second width using only routine skill in the art.
Furthermore, one of ordinary skill in the art recognizes that the exact widths of the first width and the second width are dependent on the diameter of the connection terminal. In Akram col 4 lines 25-27, a connection terminal is described as having a diameter from 3 mils to 30 mils. Since 1 mil = 25.4 μm, the diameter of a connection terminal may be in the range of 76.2 μm to 762 μm. Given that the first width and second width have nearly the same length as the diameter of the connection terminal, and a diameter of a connection terminal of approximately 250 μm, one of ordinary skill in the art would deem it obvious to discover an optimal or workable range of a first width to be 190 μm to 210 μm and of a second width to be 210 μm to 225 μm.
Regarding Claim 13,
Lin/Yang teaches:
“The semiconductor package of claim 9,”
Lin/Yang doesn’t substantially teach:
“wherein the first opening has a first depth in the second direction, the second opening has a second depth in the second direction, and the first depth and the second depth are in a range of 13 μm to 17 μm.”
However, Farnworth substantially teaches:
“wherein the first opening has a first depth in the second direction, the second opening has a second depth in the second direction, and the first depth and the second depth are in a range of 13 μm to 17 μm (Farnworth: col 7 lines 6-25, col 7 lines 38-43, col 8 lines 39-45, FIG. 3A, 4B: The size of 32 and 38 may be optimized for the dimensions of a connecting terminal. In particular, the depth of 32 may be optimized to minimize the deformation of the connecting terminal. Therefore, the depth of each opening needs to be optimized to minimize the deformation of the connecting terminal.).”
It would have been obvious to one with ordinary skill in the art before the effective filing
date of the invention to recognize that the device of Lin/Yang is modifiable in view of Farnworth by optimizing the depths of the first opening and second opening to minimally deform a connection terminal while also electrically contacting the connecting terminal by breaking any native oxide.
This is because the combination of Lin/Yang and Farnworth does not appear to expressly state the depths of the first opening and second opening; however, where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art. See MPEP §2144.05 II A; see also In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955).
In the case at hand, Farnworth teaches the general conditions of claim 13. Specifically, Farnworth teaches that the variable depth of a recess is changed to result in the desired effect of minimally deforming a contact terminal while maintaining electrical contact with a contact. Therefore, one having ordinary skill in the at the time the application at hand would find it obvious to discover the optimum or workable ranges of the depth of the first opening being between 13 μm to 17 μm and the depth of the second opening being between 13 μm to 17 μm using only routine skill in the art.
Regarding Claim 20,
Lin/Yang teaches:
“The semiconductor package of claim 16,”
Lin/Yang doesn’t substantially teach:
“wherein the first width is 80% to 95% of the second width”
However, Farnworth substantially teaches:
“wherein the first width is 80% to 95% of the second width (Farnworth: col 7 lines 6-25 ,col 8 lines 39-45, FIG. 3A, 4B: The width of the peripheral edges 38G and 38GG must both be a bit less than the average minimum diameter of a bump so that the bump may be electrically contacted and minimally deformed. Further, in order for FIG. 4B to be illustrated, the first width must be less than the second width. Therefore, one of ordinary skill in the art would be motivated for the second width to be nearly the same width as the first width.)”
It would have been obvious to one with ordinary skill in the art before the effective filing
date of the invention to recognize that the device of Lin/Yang is modifiable in view of Farnworth by optimizing the sizes of the first width and second width to minimally deform a connection terminal while also electrically contacting the connecting terminal by breaking any native oxide.
This is because the combination of Lin/Yang and Farnworth does not appear to expressly state that the first width is 80% to 95% the width of the second width; however, where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art. See MPEP §2144.05 II A; see also In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955).
In the case at hand, Farnworth teaches the general conditions of claim 11. Specifically, Farnworth teaches that the variable width of the peripheral edges is changed to result in the desired effect of minimally deforming a connection terminal while also electrically contacting the connecting terminal by breaking any native oxide. Therefore, one having ordinary skill in the at the time the application at hand would find it obvious to discover the optimum or workable ranges of the first width being 80% to 95% the width of the second width using only routine skill in the art.
Conclusion
The following prior art made of record and not relied upon are considered pertinent to applicant's disclosure. US 6107109 A, US 8222538 B1 US 20170148760 A1 for comprising a stepped solder mask structure. Further, US 20200083201 A1 is made of record but not relied upon for having a similar package structure to Applicant’s package
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ALEXANDRE XAVIER RAMIREZ whose telephone number is (571)272-2715. The examiner can normally be reached Monday - Friday 8:30 AM to 6:00 PM.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, William Partridge can be reached at (571) 270-1402. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/ALEXANDRE X RAMIREZ/Examiner, Art Unit 2812
/William B Partridge/Supervisory Patent Examiner, Art Unit 2812
Prosecution Insights