DETAILED ACTION
This action is responsive to the following communications: the Application filed on June 10, 2024, the Foreign Priority papers retrieved on December 13, 2023, and the Information Disclosure Statement filed on June 10, 2024.
Claims 1-20 are pending. Claims 1, 14 and 17 are independent.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
Acknowledgment is made of applicant’s Information Disclosure Statement (IDS) filed on June 10, 2024. This IDS has been considered.
Drawings
The drawings are objected to because all of the Figures filed on June 10, 2024 are degraded, showing dotted lines and dotted lettering and numbering, which may indicate applicant submitted Figures that were in greyscale. Applicant is reminded that solid lines used in the Drawings must be uniformly thick, black, and solid and the words and labels in the Drawings must be plain and legible. MPEP 608.02(f)(V).
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-2, 5-6, 13-15 and 17-18 are rejected under 35 U.S.C. 103 as being unpatentable over Seo (US 20150036444) in view of Lam et al. (US 20220270654).
Regarding independent claim 1, Seo discloses a semiconductor memory device [Fig. 23: 1000] comprising:
a memory cell array [Fig. 23: 1110, para. 127] comprising a memory cell [see Fig. 2, para. 70];
a bitline sense amplifier [Fig. 23: 1210] having an open bitline structure [para. 127] and comprising a plurality of switching transistors [see Fig. 18-19, para. 112-113], wherein the bitline sense amplifier is connected to the memory cell via a bitline and a complementary bitline [a pair (BL, BLB) of the bitlines crosses each other to be connected to the bitline sense amplifier, para. 127], and the plurality of switching transistors are configured to control connections between the bitline, the complementary bitline, a sensing bitline and a complementary sensing bitline based on a plurality of switching signals [see Fig. 18-19, para. 112-113].
However, Seo is silent with respect to a temperature measurement circuit configured to measure an operation temperature of the semiconductor memory device and to generate a temperature code corresponding to the operation temperature; and a sense amplifier controller configured to reduce sensing noise of the bitline sense amplifier by controlling timing of the plurality of switching signals based on the temperature code. Seo only discloses, in Figure 8, a sense amplifier 350 comprises first and second isolation/offset cancellation units 351 and 352 [para. 112] and states that noise is reduced by performing offset cancellation operation and controlling ISO/OC timing [para. 57-58]. Seo also discloses the offset cancelling operation represents an operation compensating a characteristic difference of elements in the sense amplifier due to a process variation and a temperature [para. 104].
Lam et al. teach a temperature measurement circuit [Fig. 1: 152] configured to measure an operation temperature of the semiconductor memory device and to generate a temperature code corresponding to the operation temperature [temperature sensor control circuit 152 configured to measure the operating temperature of the semiconductor device and produce a digital output, including a temperature range signal with temperature compare bits representing multiple temperature ranges, para. 19];
and a sense amplifier controller configured to control timing of the plurality of switching signals based on the temperature code [see Fig. 1, the VtC control circuit 154 is configured to receive the temperature range signal from the temperature sensor control circuit 152 and provide a Vt compensation duration signal to the sense amplifier control circuit 156. The Vt compensation duration signal is used to control a duration of a Vt compensation operation, para. 20. See Fig. 5-6, the Vt compensation code is selected based on the temperature compare bits and a sense amplifier control circuit 156 selecting among different delays via multiple delay circuits 604, para. 39-42].
It would have been obvious to a person having ordinary skill in the art before the effective filling date of the claimed invention to apply the teachings of Lam et al. to the teachings of Seo such that incorporating the temperature measurement and timing selection based on the temperature code as taught by Lam et al. into the Seo’s semiconductor memory device to reduce sensing noise margin loss across high/low temperature operation without changing Seo’s sense amplifier topology.
Regarding claim 2, Seo in combination with Lam et al. teach the limitations with respect to claim 1.
Furthermore, Lam et al. disclose wherein the sense amplifier controller is further configured to control the bitline sense amplifier to operate in a sensing mode among a plurality of sensing modes by controlling the timing of the plurality of switching signals based on a temperature range within which the operation temperature falls from among a plurality of temperature ranges [see Fig. 8: step 804-808, the voltage compensation duration signal is selected from a plurality of compensation codes responsive to temperature compare bits indicating the operating temperature of the memory. A bit line compensation signal is received, and the bit line compensation signal is latched at a high logic level, and the bit line compensation signal deactivated responsive to the voltage compensation duration signal, para. 53-54].
Regarding claim 5, Seo in combination with Lam et al. teach the limitations with respect to claim 1.
Furthermore, Seo discloses the plurality of switching transistors [see Fig. 19] comprises:
a first switching transistor [Fig. 19: OC_1] configured to control a connection between the bitline [Fig. 19: BL] and the complementary sensing bitline [Fig. 19: SABLB] based on a first switching signal [offset cancellation signal OC, para. 112-116];
a second switching transistor [Fig. 19: OC_2] configured to control a connection between the complementary bitline [Fig. 19: BLB] and the sensing bitline [Fig. 19: SABL] based on the first switching signal [offset cancellation signal OC, para. 112-116];
a third switching transistor [Fig. 19: ISO_1] configured to control a connection between the bitline [Fig. 19: BL] and the sensing bitline [Fig. 19: SABL] based on a second switching signal [isolation signal ISO, para. 112-116];
a fourth switching transistor [Fig. 19: ISO_2] configured to control a connection between the complementary bitline [Fig. 19: BLB] and the complementary sensing bitline [Fig. 19: SABLB] based on the second switching signal [isolation signal ISO, para. 112-116]; and
a fifth switching transistor [Fig. 19: E_3] configured to control a connection between the sensing bitline [Fig. 19: SABL] and the complementary sensing bitline [Fig. 19: SABLB] based on a third switching signal [equalizing signal PEQ, para. 112-116].
Regarding claim 6, Seo in combination with Lam et al. teach the limitations with respect to claim 5.
Furthermore, Seo describes an open bit line sensing flow where multiple control signals (ISO, OC, PEQ) control whether BL/BLB are connected to the sensing lines SABL/SABLB or disconnected [para. 52-53 and 109].
However, Seo is silent with respect to the operation temperature falls within a temperature range among a plurality of temperature ranges, the plurality of temperature ranges comprises a normal temperature range, a high temperature range higher than the normal temperature range, and a low temperature range lower than the normal temperature range, and
wherein the sense amplifier controller is further configured to control the timing of the second switching signal and the third switching signal to cause the bitline sense amplifier to operate in a sensing mode from among a plurality of sensing modes based on the temperature range.
Lam et al. teach the sense amplifier controller is further configured to control the bitline sense amplifier to operate in a sensing mode among a plurality of sensing modes by controlling the timing of the plurality of switching signals based on a temperature range within which the operation temperature falls from among a plurality of temperature ranges [see Fig. 8: step 804-808, the voltage compensation duration signal is selected from a plurality of compensation codes responsive to temperature compare bits indicating the operating temperature of the memory. A bit line compensation signal is received, and the bit line compensation signal is latched at a high logic level, and the bit line compensation signal deactivated responsive to the voltage compensation duration signal, para. 53-54].
It would have been obvious to a person having ordinary skill in the art before the effective filling date of the claimed invention to apply the teachings of Lam et al. to the teachings of Seo such that incorporating the temperature measurement and timing selection based on the temperature code as taught by Lam et al. into the Seo’s sense amplifier controller to reduce sensing noise margin loss across high/low temperature operation without changing Seo’s sense amplifier topology.
Regarding claim 13, Seo in combination with Lam et al. teach the limitations with respect to claim 1.
Furthermore, Seo discloses the bitline sense amplifier [see Fig. 19] comprises:
a first P-type transistor [Fig. 19: P_1] connected between a control line [Fig. 19: LA] and the complementary sensing bitline [Fig. 19: SABLB], the first P-type transistor [Fig. 19: P_1] comprising a gate electrode connected to the sensing bitline [Fig. 19: SABL];
a second P-type transistor [Fig. 19: P_2] connected between the control line [Fig. 19: LA] and the sensing bitline [Fig. 19: SABL], the second P-type transistor [Fig. 19: P_2] comprising a gate electrode connected to the complementary sensing bitline [Fig. 19: SABLB];
a first N-type transistor [Fig. 19: N_1] connected between a complementary control line [Fig. 19: LAB] and the complementary sensing bitline [Fig. 19: SABLB], the first N-type transistor comprising a gate electrode connected to the bitline [Fig. 19: BL]; and
a second N-type transistor [Fig. 19: N_2] connected between the complementary control line [Fig. 19: LAB] and the sensing bitline [Fig. 19: SABL], the second N-type transistor comprising a gate electrode connected to the complementary bitline [Fig. 19: BLB].
Regarding independent claim 14, Seo discloses a semiconductor memory device [Fig. 23: 1000] comprising:
a memory cell array [Fig. 23: 1110, para. 127] comprising a memory cell [see Fig. 2, para. 70];
a bitline sense amplifier [Fig. 23: 1210] having an open bitline structure [para. 127], wherein the bitline sense amplifier is connected to the memory cell via a bitline and a complementary bitline [a pair (BL, BLB) of the bitlines crosses each other to be connected to the bitline sense amplifier, para. 127], the bitline sense amplifier comprising:
a first switching transistor [Fig. 19: OC_1] configured to control a connection between the bitline [Fig. 19: BL] and the complementary sensing bitline [Fig. 19: SABLB] based on a first switching signal [offset cancellation signal OC, para. 112-116];
a second switching transistor [Fig. 19: OC_2] configured to control a connection between the complementary bitline [Fig. 19: BLB] and the sensing bitline [Fig. 19: SABL] based on the first switching signal [offset cancellation signal OC, para. 112-116];
a third switching transistor [Fig. 19: ISO_1] configured to control a connection between the bitline [Fig. 19: BL] and the sensing bitline [Fig. 19: SABL] based on a second switching signal [isolation signal ISO, para. 112-116];
a fourth switching transistor [Fig. 19: ISO_2] configured to control a connection between the complementary bitline [Fig. 19: BLB] and the complementary sensing bitline [Fig. 19: SABLB] based on the second switching signal [isolation signal ISO, para. 112-116]; and
a fifth switching transistor [Fig. 19: E_3] configured to control a connection between the sensing bitline [Fig. 19: SABL] and the complementary sensing bitline [Fig. 19: SABLB] based on a third switching signal [equalizing signal PEQ, para. 112-116].
However, Seo is silent with respect to a temperature measurement circuit configured to measure an operation temperature of the semiconductor memory device and to generate a temperature code corresponding to the operation temperature and a sense amplifier controller configured to reduce sensing noise of the bitline sense amplifier by controlling timing of the plurality of switching signals based on the temperature code. Seo only discloses, in Figure 8, a sense amplifier 350 comprises first and second isolation/offset cancellation units 351 and 352 [para. 112] and states that noise is reduced by performing offset cancellation operation and controlling ISO/OC timing [para. 57-58]. Seo also discloses the offset cancelling operation represents an operation compensating a characteristic difference of elements in the sense amplifier due to a process variation and a temperature [para. 104].
Lam et al. teach a temperature measurement circuit [Fig. 1: 152] configured to measure an operation temperature of the semiconductor memory device and to generate a temperature code corresponding to the operation temperature [temperature sensor control circuit 152 configured to measure the operating temperature of the semiconductor device and produce a digital output, including a temperature range signal with temperature compare bits representing multiple temperature ranges, para. 19];
and a sense amplifier controller configured to control timing of the plurality of switching signals based on the temperature code [see Fig. 1, the VtC control circuit 154 is configured to receive the temperature range signal from the temperature sensor control circuit 152 and provide a Vt compensation duration signal to the sense amplifier control circuit 156. The Vt compensation duration signal is used to control a duration of a Vt compensation operation, para. 20. See Fig. 5-6, the Vt compensation code is selected based on the temperature compare bits and a sense amplifier control circuit 156 selecting among different delays via multiple delay circuits 604, para. 39-42].
It would have been obvious to a person having ordinary skill in the art before the effective filling date of the claimed invention to apply the teachings of Lam et al. to the teachings of Seo such that incorporating the temperature measurement and timing selection based on the temperature code as taught by Lam et al. into the Seo’s semiconductor memory device to reduce sensing noise margin loss across high/low temperature operation without changing Seo’s sense amplifier topology.
Regarding claim 15, Seo in combination with Lam et al. teach the limitations with respect to claim 14.
Furthermore, Seo describes an open bit line sensing flow where multiple control signals (ISO, OC, PEQ) control whether BL/BLB are connected to the sensing lines SABL/SABLB or disconnected [para. 52-53 and 109].
However, Seo is silent with respect to the sense amplifier controller is further configured to control the bitline sense amplifier to operate in a sensing mode among a plurality of sensing modes by controlling the timing of the first switching signal, the second switching signal and the third switching signal based on a temperature range within which the operation temperature falls from among a plurality of temperature ranges.
Lam et al. teach the sense amplifier controller is further configured to control the bitline sense amplifier to operate in a sensing mode among a plurality of sensing modes by controlling the timing of the plurality of switching signals based on a temperature range within which the operation temperature falls from among a plurality of temperature ranges [see Fig. 8: step 804-808, the voltage compensation duration signal is selected from a plurality of compensation codes responsive to temperature compare bits indicating the operating temperature of the memory. A bit line compensation signal is received, and the bit line compensation signal is latched at a high logic level, and the bit line compensation signal deactivated responsive to the voltage compensation duration signal, para. 53-54].
It would have been obvious to a person having ordinary skill in the art before the effective filling date of the claimed invention to apply the teachings of Lam et al. to the teachings of Seo such that incorporating the temperature measurement and timing selection based on the temperature code as taught by Lam et al. into the Seo’s sense amplifier controller to reduce sensing noise margin loss across high/low temperature operation without changing Seo’s sense amplifier topology.
Regarding independent claim 17, Seo discloses a method of controlling a semiconductor memory device, the method comprising:
providing a bitline sense amplifier [Fig. 23: 1210] having an open bitline structure [para. 127] and comprising a plurality of switching transistors [see Fig. 18-19, para. 112-113], wherein the bitline sense amplifier is connected to the memory cell via a bitline and a complementary bitline [a pair (BL, BLB) of the bitlines crosses each other to be connected to the bitline sense amplifier, para. 127], and the plurality of switching transistors are configured to control connections between the bitline, the complementary bitline, a sensing bitline and a complementary sensing bitline based on a plurality of switching signals [see Fig. 18-19, para. 112-113].
However, Seo is silent with respect to measuring an operation temperature of the semiconductor memory device to generate a temperature code corresponding to the operation temperature and based on the temperature code, controlling timing of the plurality of switching signals to reduce sensing noise of the bitline sense amplifier. Seo only discloses, in Figure 8, a sense amplifier 350 comprises first and second isolation/offset cancellation units 351 and 352 [para. 112] and states that noise is reduced by performing offset cancellation operation and controlling ISO/OC timing [para. 57-58]. Seo also discloses the offset cancelling operation represents an operation compensating a characteristic difference of elements in the sense amplifier due to a process variation and a temperature [para. 104].
Lam et al. teach measuring an operation temperature of the semiconductor memory device to generate a temperature code corresponding to the operation temperature [temperature sensor control circuit 152 configured to measure the operating temperature of the semiconductor device and produce a digital output, including a temperature range signal with temperature compare bits representing multiple temperature ranges, para. 19]; and
based on the temperature code, controlling timing of the plurality of switching signals to reduce sensing noise of the bitline sense amplifier [see Fig. 1, the VtC control circuit 154 is configured to receive the temperature range signal from the temperature sensor control circuit 152 and provide a Vt compensation duration signal to the sense amplifier control circuit 156. The Vt compensation duration signal is used to control a duration of a Vt compensation operation, para. 20. See Fig. 5-6, the Vt compensation code is selected based on the temperature compare bits and a sense amplifier control circuit 156 selecting among different delays via multiple delay circuits 604, para. 39-42].
It would have been obvious to a person having ordinary skill in the art before the effective filling date of the claimed invention to apply the teachings of Lam et al. to the teachings of Seo such that incorporating the temperature measurement and timing selection based on the temperature code as taught by Lam et al. into the Seo’s semiconductor memory device to reduce sensing noise margin loss across high/low temperature operation without changing Seo’s sense amplifier topology.
Regarding claim 18, Seo in combination with Lam et al. teach the limitations with respect to claim 17.
Furthermore, Lam et al. disclose the controlling the timing of the plurality of switching signals includes:
controlling the bitline sense amplifier to operate in a sensing mode among a plurality of sensing modes by controlling the timing of the plurality of switching signals based on a temperature range within which the operation temperature falls from among a plurality of temperature ranges [see Fig. 8: step 804-808, the voltage compensation duration signal is selected from a plurality of compensation codes responsive to temperature compare bits indicating the operating temperature of the memory. A bit line compensation signal is received, and the bit line compensation signal is latched at a high logic level, and the bit line compensation signal deactivated responsive to the voltage compensation duration signal, para. 53-54].
Claim 20 is rejected under 35 U.S.C. 103 as being unpatentable over Seo (US 20150036444) in view of Lam et al. (US 20220270654) as applied to claim 17 above and further in view of Lee et al. (US 20240029782).
Regarding claim 20, Seo in combination with Lam et al. teach the limitations with respect to claim 17.
Furthermore, Seo describes further comprising:
performing a precharge operation comprising charging the bitline, the complementary bitline, the sensing bitline, and the complementary sensing bitline with a precharge voltage [see Fig. 7: step S110, para. 74].
However, Seo in combination with Lam et al. are silent with respect to performing a first offset compensation operation comprising connecting the bitline and the complementary sensing bitline; connecting the complementary bitline and the sensing bitline; applying a first internal voltage higher than the precharge voltage to a P-type sense amplifier of the bitline sense amplifier; and applying a second internal voltage lower than the precharge voltage to an N-type sense amplifier of the bitline sense amplifier; and
performing a second offset compensation operation comprising applying the precharge voltage to the P-type sense amplifier and applying the second internal voltage to the N-type sense amplifier.
Lee et al teach performing a first offset compensation operation comprising connecting the bitline and the complementary sensing bitline; connecting the complementary bitline and the sensing bitline; applying a first internal voltage higher than the precharge voltage to a P-type sense amplifier of the bitline sense amplifier; and applying a second internal voltage lower than the precharge voltage to an N-type sense amplifier of the bitline sense amplifier [see Lee et al.’s abstract] and
performing a second offset compensation operation comprising applying the precharge voltage to the P-type sense amplifier and applying the second internal voltage to the N-type sense amplifier [see Lee et al.’s abstract].
It would have been obvious to a person having ordinary skill in the art before the effective filling date of the claimed invention to apply the teachings of Lee et al. to the teachings of Seo in combination with Lam et al. such that applying two offset compensation operations as taught by Lee at al. to the bit line sense amplifier of Seo in combination with Lam et al. to reduce the offset noise of the bit line sense amplifier [see Lee et al.’s para. 53].
Allowable Subject Matter
Claims 3-4, 7-12, 16 and 19 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
With respect to claim 3, the applied prior art, Seo describes an open bit line sensing flow where multiple control signals (ISO, OC, PEQ) control whether BL/BLB are connected to the sensing lines SABL/SABLB or disconnected. Another applied prior art is Lam et al. teach measuring operating temperature and using that to select a duration code that controls a sense amplifier compensation pulse duration. However, both Seo and Lam et al. individually or in combination do not teach or suggest the sense amplifier controller is further configured to control the timing of the plurality of switching signals to cause a floating time during which the sensing bitline and the complementary sensing bitline are floated to decrease as the operation temperature increases. Thus, there is no teaching or suggestion in the prior art of record to provide the recited the sense amplifier controller is further configured to control the timing of the plurality of switching signals to cause a floating time during which the sensing bitline and the complementary sensing bitline are floated to decrease as the operation temperature increases.
With respect to claim 7, there is no teaching or suggestion in the prior art or record to provide the recited the sense amplifier controller is further configured to, based on the temperature range being the normal temperature range, cause the bitline sense amplifier to operate in an H-type sensing mode by during a charge sharing period, causing the sensing bitline and the complementary sensing bitline to be connected by activating the third switching signal, and during a sensing period after the charge sharing period, causing the bitline and the sensing bitline to be connected and causing the complementary bitline and the complementary sensing bitline to be connected by activating the second switching signal after the third switching signal is deactivated.
With respect to claim 8, there is no teaching or suggestion in the prior art or record to provide the recited the sense amplifier controller is further configured to, based on the temperature range being the low temperature range, cause the bitline sense amplifier to operate in a D-type sensing mode by:
during a charge sharing period, causing the sensing bitline and the complementary sensing bitline to be disconnected by deactivating the third switching signal,
during the charge sharing period, causing the bitline and the sensing bitline to be temporarily connected and causing the complementary bitline and the complementary sensing bitline to be temporarily connected by toggling the second switching signal between an activated state and a deactivated state, and
during a sensing period after the charge sharing period, causing the bitline and the sensing bitline to be connected and causing the complementary bitline and the complementary sensing bitline to be connected by activating the second switching signal.
With respect to claim 9, there is no teaching or suggestion in the prior art or record to provide the recited the sense amplifier controller is further configured to, based on the temperature range being the high temperature range, cause the bitline sense amplifier to operate in a C-type sensing mode by:
during a charge sharing period, causing the sensing bitline and the complementary sensing bitline to be disconnected by deactivating the third switching signal,
during the charge sharing period, causing the bitline and the sensing bitline to be temporarily connected and causing the complementary bitline and the complementary sensing bitline to be temporarily connected by toggling the second switching signal, and
before a sensing period after the charge sharing period, causing the bitline and the sensing bitline to be connected and causing the complementary bitline and the complementary sensing bitline to be connected by activating the second switching signal.
With respect to claim 10, there is no teaching or suggestion in the prior art or record to provide the recited the sense amplifier controller is further configured to control the timing of the second switching signal and the third switching signal to cause the bitline sense amplifier to operate in a D-type sensing mode based on the temperature range being the low temperature range, to operate in a C-type sensing mode based on the temperature range being the high temperature range, and to operate in an H-type sensing mode based on the temperature range being the normal temperature range.
With respect to claim 11, there is no teaching or suggestion in the prior art or record to provide the recited the sense amplifier controller is further configured to cause the bitline sense amplifier to operate in a D-type sensing mode by:
during a charge sharing period, causing the sensing bitline and the complementary sensing bitline to be disconnected by deactivating the third switching signal,
during the charge sharing period, causing the bitline and the sensing bitline to be temporarily connected and causing the complementary bitline and the complementary sensing bitline to be temporarily connected by toggling the second switching signal,
during a sensing period after the charge sharing period, causing the bitline and the sensing bitline to be connected and causing the complementary bitline and the complementary sensing bitline to be connected by activating the second switching signal, and
based on the operation temperature increasing, causing a floating time during which the sensing bitline and the complementary sensing bitline are floated to decrease by delaying a time point at which the second switching signal is deactivated after the toggling of the second switching signal.
With respect to claim 12, there is no teaching or suggestion in the prior art or record to provide the recited the sense amplifier controller is further configured to cause the bitline sense amplifier to operate in a D-type sensing mode by:
during a charge sharing period, causing the sensing bitline and the complementary sensing bitline to be disconnected by deactivating the third switching signal,
before a sensing period after the charge sharing period, causing the bitline and the sensing bitline to be connected and causing the complementary bitline and the complementary sensing bitline to be connected by activating the second switching signal, and
based on the operation temperature increasing, causing a floating time during which the sensing bitline and the complementary sensing bitline are floated to decreases by adjusting a time point at which the second switching signal is activated to a time point earlier in the charge sharing period.
With respect to claim 16, the applied prior art, Seo describes an open bit line sensing flow where multiple control signals (ISO, OC, PEQ) control whether BL/BLB are connected to the sensing lines SABL/SABLB or disconnected. Another applied prior art is Lam et al. teach measuring operating temperature and using that to select a duration code that controls a sense amplifier compensation pulse duration. However, both Seo and Lam et al. individually or in combination do not teach or suggest the sense amplifier controller is further configured to control the timing of the plurality of switching signals to cause a floating time during which the sensing bitline and the complementary sensing bitline are floated to decrease as the operation temperature increases. Thus, there is no teaching or suggestion in the prior art of record to provide the recited the sense amplifier controller is further configured to control the timing of the plurality of switching signals to cause a floating time during which the sensing bitline and the complementary sensing bitline are floated to decrease as the operation temperature increases.
With respect to claim 19, the applied prior art, Seo describes an open bit line sensing flow where multiple control signals (ISO, OC, PEQ) control whether BL/BLB are connected to the sensing lines SABL/SABLB or disconnected. Another applied prior art is Lam et al. teach measuring operating temperature and using that to select a duration code that controls a sense amplifier compensation pulse duration. However, both Seo and Lam et al. individually or in combination do not teach or suggest the controlling the timing of the plurality of switching signals comprises controlling the timing of the plurality of switching signals to cause a floating time during which the sensing bitline and the complementary sensing bitline are floated to decrease as the operation temperature increases. Thus, there is no teaching or suggestion in the prior art of record to provide the recited the controlling the timing of the plurality of switching signals comprises controlling the timing of the plurality of switching signals to cause a floating time during which the sensing bitline and the complementary sensing bitline are floated to decrease as the operation temperature increases.
Conclusion
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/DUY H LUONG/Examiner, Art Unit 2825
/ALEXANDER SOFOCLEOUS/Supervisory Patent Examiner, Art Unit 2825