Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 7-9, 14-15, and 17 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Takeoka et al. “Takeoka”, WO 2021251128 (this document is dated 12-16-2021, all citations below are directed to the US counterpart US 2023/0125825).
Regarding Claim 7, Takeoka discloses a semiconductor element (30; Figs. 2,10; ¶ 0055 “semiconductor element 30”) comprising:
an element front surface (30a; Fig. 10; ¶ 0056 “surface 30a”) and an element back surface (30b; Fig. 10; ¶ 00566 “surface 30b”) facing an opposite side from the element front surface (Fig. 10; ¶ 0056);
a first electrode (right side 34; Fig. 5, see also Fig. 14; ¶ 0060 “electrodes 34 are disposed on the element obverse surface 30a”) and a second electrode (left side 34; Fig. 5, see also Fig. 16; ¶ 0060 “electrodes 34 are disposed on the element obverse surface 30a”) that are formed over the element front surface (Figs. 14, 16; ¶ 0060 “electrodes 34 are disposed on the element obverse surface 30a”);
a plurality of first electrode terminals (36, 36A, 361, 362; Fig. 14; ¶ 0064, 0066-0067) in contact with the first electrode (Fig. 14; ¶ 0064 “seed layer 361a is in contact with the relevant electrode 34”);
a plurality of second electrode terminals (36, 36B, 361, 362; Fig. 16; ¶ 0064, 0066, 0070-0073) in contact with the second electrode (Fig. 16; ¶ 0064 “seed layer 361a is in contact with the relevant electrode 34”;
a first region (321; Figs. 10-15; ¶ 0058 “switching circuit 321”) in which the plurality of first electrode terminals (36A) are arranged (¶ 0067 “terminals 36A are electrically connected to the switching circuit 321”); and
a second region (322; Figs. 10, 13, 16; ¶ 0058 “control circuit 322”) in which the plurality of second electrode terminals (36B) are arranged (¶ 0070 “terminals 36B are electrically connected to the control circuit 322”),
wherein the number of the second electrode terminals (36B) per unit area in the second region (Fig. 2; ¶ 0086 “36B sparsely arranged in the second region 302”) is smaller than (Fig. 2) the number of the first electrode terminals (36A) per unit area in the first region (Fig. 2; ¶ 0086 “36A densely arranged in the first region 301”), and
wherein at least one dummy terminal (36C; Fig. 19; ¶ 0094 “electrode terminals 36C are “dummy electrode terminals” not connected to any of the first leads 10A, 10B and 10C, the second leads 21 and the third leads 22”) is provided in the second region (Fig. 19; ¶ 0094 “electrode terminals 36C are located in the second region 302”).
Regarding Claim 8, Takeoka discloses wherein the at least one dummy terminal (36C) is arranged to be closer to the second electrode terminals (36B) than the first electrode terminals (36A; Fig. 19; in this instance dummy terminals 36C are closer to second electrode terminals 36B that are located on the left side of dummy terminals 36C then dummy terminal 36C are to first electrode terminals 36A that are located furthest to the right of dummy terminals 36C).
Regarding Claim 9, Takeoka discloses
wherein the second electrode terminals (36B) are arranged to be spaced apart from the first electrode terminals (36A) in a first direction (Y; Fig. 19 the second electrode terminals 36B, that are on the left side in the Y direction, are spaced apart from the first electrode terminals 36A, that are on the right side in the Y direction), when viewed from a thickness direction of the semiconductor element (Fig. 19; ¶ 0093 “FIG. 19 is a plan view”),
wherein the semiconductor element further comprises a third electrode (34; Figs. 14-16; ¶ 0094 “electrode terminals 36C are similar in configuration to the electrode terminals 36A and 36B”, ¶ 0063 “as shown in FIGS. 14 to 16, each electrode terminal 36 is in contact with an electrode 34” therefore a third electrode 34 is associated with each dummy terminal 36C) formed in the second region of the element front surface (¶ 0094 “electrode terminals 36C are located in the second region 302” therefore the third electrode 34 of dummy terminals 36C are also located in the second region),
wherein the third electrode is provided near the second electrode (¶ 0094 “electrode terminals 36C are located in the second region 302” therefore the third electrode 34 of the dummy terminal 36C is near the second electrode 36B that is also in the second region) between the first electrode and the second electrode in the first direction (Fig. 19 the third electrode 34 of the dummy terminal 36C is between the first electrode 36A and the second electrode 36B), and
wherein the at least one dummy terminal is in contact with the third electrode (¶ 0094 “electrode terminals 36C are similar in configuration to the electrode terminals 36A and 36B”, ¶ 0063 “as shown in FIGS. 14 to 16, each electrode terminal 36 is in contact with an electrode 34” therefore the at least one dunny terminal 36C is in contact with the third electrode 34).
Regarding Claim 14, Takeoka discloses
wherein the second electrode terminals (36B) are arranged to be spaced apart from the first electrode terminals (36A) in a first direction (Y; Fig. 19; ¶ 0093 “FIG. 19 is a plan view” the second electrode terminals 36B, that are on the left side in the Y direction, are spaced apart from the first electrode terminals 36A, that are on the right side in the Y direction), when viewed from a thickness direction of the semiconductor element (Fig. 19; ¶ 0093 “FIG. 19 is a plan view”),
wherein the plurality of second electrode terminals (36B) are arranged to be spaced apart from one another in a second direction perpendicular to the first direction (X; Fig. 19 the second electrode terminals 36B are spaced apart from one another in the vertical direction), when viewed from the thickness direction (Fig. 19; ¶ 0093 “FIG. 19 is a plan view”), and
wherein the at least one dummy terminal includes a plurality of dummy terminals (Fig. 19; ¶ 0093 “a plurality of electrode terminals 36C”), which are provided to be spaced apart from one another in the second direction (Fig. 19 the plurality of dummy terminals 36C are spaced apart from one another in the X (vertical) direction).
Regarding Claim 15, Takeoka discloses wherein the at least one dummy terminal (36C) includes a plurality of dummy terminals (Fig. 19; ¶ 0093 “a plurality of electrode terminals 36C”), which are provided to surround the second electrode terminals when viewed from a thickness direction of the semiconductor element (Fig. 19 in this instance the line of six dummy terminals 36C surround the right side of the line of three second electrode terminals 36B that are located directly on the left side of the dummy terminals 36C).
Regarding Claim 17, Takeoka discloses
wherein each of the first electrode terminals (36A) includes a first seed layer (361a; Figs. 14-15; ¶ 0064 “seed layer 361a”) in contact with the first electrode (Figs. 14-15; ¶ 0064 “seed layer 361a is in contact with the relevant electrode 34”), and a first plating layer (361b; Figs. 14-15; ¶ 0064 “plating layer 361b”) laminated on the first seed layer (Figs. 14-15; ¶ 0064 “plating layer 361b is sacked on the seed layer 361a” and “plating layer 361b may be formed by electroplating”),
wherein each of the second electrode terminals (36B) includes a second seed layer (361a; Fig. 16; ¶ 0064 “seed layer 361a”) in contact with the second electrode (Fig. 16; ¶ 0064 “seed layer 361a is in contact with the relevant electrode 34”), and a second plating layer (361b; Fig. 16; ¶ 0064 “plating layer 361b”) laminated on the second seed layer (Fig. 16; ¶ 0064 “plating layer 361b is sacked on the seed layer 361a” and “plating layer 361b may be formed by electroplating”), and
wherein the at least one dummy terminal (36C) includes a third seed layer (361a; ¶ 0094 “electrode terminals 36C are similar in configuration to the electrode terminals 36A and 36B”, ¶ 0064 “seed layer 361a”, therefore dummy terminal 36C also includes a third seed layer 361a) in contact with the third electrode (¶ 0064 “seed layer 361a is in contact with the relevant electrode 34”), and a third plating layer (361b; ¶ 0064 “plating layer 361b”) laminated on the third seed layer (¶ 0064 “plating layer 361b is sacked on the seed layer 361a” and “plating layer 361b may be formed by electroplating”).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-6, 10-13, 16, and 18-19 are rejected under 35 U.S.C. 103 as being unpatentable over Takeoka et al. “Takeoka”, WO 2021251128 (this document is dated 12-16-2021, all citations below are directed to the US counterpart US 2023/0125825).
Regarding Claim 1, Takeoka discloses a semiconductor element (30; Figs. 2,10; ¶ 0055 “semiconductor element 30”) comprising:
an element front surface (30a; Fig. 10; ¶ 0056 “surface 30a”) and an element back surface (30b; Fig. 10; ¶ 00566 “surface 30b”) facing an opposite side from the element front surface (Fig. 10; ¶ 0056);
a first electrode (right side 34; Fig. 5, see also Fig. 14; ¶ 0060 “electrodes 34 are disposed on the element obverse surface 30a”) and a second electrode (left side 34; Fig. 5, see also Fig. 16; ¶ 0060 “electrodes 34 are disposed on the element obverse surface 30a”) that are formed over the element front surface (Figs. 14, 16; ¶ 0060 “electrodes 34 are disposed on the element obverse surface 30a”);
a plurality of first electrode terminals (36, 36A, 361, 362; Fig. 14; ¶ 0064, 0066-0067) in contact with the first electrode (Fig. 14; ¶ 0064 “seed layer 361a is in contact with the relevant electrode 34”);
a plurality of second electrode terminals (36, 36B, 361, 362; Fig. 16; ¶ 0064, 0066, 0070-0073) in contact with the second electrode (Fig. 16; ¶ 0064 “seed layer 361a is in contact with the relevant electrode 34”;
a first region (321; Figs. 10-15; ¶ 0058 “switching circuit 321”) in which the plurality of first electrode terminals (36A) are arranged (¶ 0067 “terminals 36A are electrically connected to the switching circuit 321”); and
a second region (322; Figs. 10, 13, 16; ¶ 0058 “control circuit 322”) in which the plurality of second electrode terminals (36B) are arranged (¶ 0070 “terminals 36B are electrically connected to the control circuit 322”),
wherein the number of the second electrode terminals (36B) per unit area in the second region (Fig. 2; ¶ 0086 “36B sparsely arranged in the second region 302”) is smaller than (Fig. 2) the number of the first electrode terminals (36A) per unit area in the first region (Fig. 2; ¶ 0086 “36A densely arranged in the first region 301”), and
wherein an area of each of the second electrode terminals is larger than (¶ 0067 “The shape of the electrode terminals 36A as viewed in the z direction (the planar shape) is not particularly limited and may be circular, elliptical (oval), rectangular or polygonal as appropriate.” and “The dimensions of the electrode terminals 36A are not particularly limited.”, ¶ 0072 “the value of the electric current flowing through the electrode terminals 36B per unit area can be increased”, therefore it would be obvious to try different combinations of sizes of 36A and 36B in order to change the ratio between the two, and Takeoka definitely encourages playing around with different sizes of 36A and 36B to determine what is optimal) an area of each of the plurality of first electrode terminals when viewed from a thickness direction (Z; Fig. 1; ¶ 0040 “the thickness direction of the semiconductor device A10 is defined as the z direction” and “in the thickness direction (plan view)”) which is perpendicular (Fig. 1; ¶ 0040 “a direction perpendicular”) to the element front surface (Fig. 1).
Takeoka does not specifically disclose wherein an area of each of the second electrode terminals is larger than an area of each of the plurality of first electrode terminals when viewed from a thickness direction.
MPEP 2144.04(IV)( A) describes changes in size/proportion - In re Rose, 220 F.2d 459, 105 USPQ 237 (CCPA 1955) (Claims directed to a lumber package "of appreciable size and weight requiring handling by a lift truck" were held unpatentable over prior art lumber packages which could be lifted by hand because limitations relating to the size of the package were not sufficient to patentably distinguish over the prior art.); In re Rinehart, 531 F.2d 1048, 189 USPQ 143 (CCPA 1976) ("mere scaling up of a prior art process capable of being scaled up, if such were the case, would not establish patentability in a claim to an old process so scaled." 531 F.2d at 1053, 189 USPQ at 148.). In Gardner v. TEC Syst., Inc., 725 F.2d 1338, 220 USPQ 777 (Fed. Cir. 1984), cert. denied, 469 U.S. 830, 225 USPQ 232 (1984), the Federal Circuit held that, where the only difference between the prior art and the claims was a recitation of relative dimensions of the claimed device and a device having the claimed relative dimensions would not perform differently than the prior art device, the claimed device was not patentably distinct from the prior art device.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention for Takeoka to have wherein an area of each of the second electrode terminals is larger than an area of each of the plurality of first electrode terminals when viewed from a thickness direction so that an optimal physical and electrical connection can be achieved, between the first electrode terminals 36A and first leads 10A-10C (Fig. 10; ¶ 0067), and between the second electrode terminals 36B and both the second and third leads 21, 22 (Figs. 10, 13; ¶ 0070), in order to maximize the reliability of the semiconductor element.
Regarding Claim 2, Takeoka discloses
wherein the first region (321) is a region in which a first transistor and a second transistor connected in series with each other are formed (¶ 0058 “the switching circuit 321 is divided into two regions…each region is formed with one n-channel MOSFET”),
wherein the second region (322) is a region in which a control circuit (¶ 0058 “control circuit 322”) configured to control the first transistor and the second transistor is formed (¶ 0058 “the control circuit 322… operates to drive the switching circuit 321 normally”),
wherein the plurality of first electrode terminals (36A) are electrically connected to the first transistor and the second transistor (Figs. 10-15; ¶ 0067 “electrode terminals 36A are electrically connected to the switching circuit 321”), and
wherein the plurality of second electrode terminals (36B) are electrically connected to the control circuit (Figs. 10, 13, 16; ¶ 0070 “electrode terminals 36B are electrically connected to the control circuit 322”).
Regarding Claim 3, Takeoka discloses
wherein a shape of each of the second electrode terminals (¶ 0070 “The shape of the electrode terminals 36B as viewed in the z direction (the planar shape) is not particularly limited and may be circular, elliptical (oval), rectangular or polygonal as appropriate.”) viewed from the thickness direction is different from (Figs. 2, 3, 5) a shape of each of the first electrode terminals viewed from the thickness direction (¶ 0067 “The shape of the electrode terminals 36A as viewed in the z direction (the planar shape) is not particularly limited and may be circular, elliptical (oval), rectangular or polygonal as appropriate.”), and
wherein the shape of each of the first electrode terminals viewed from the thickness direction is circular (¶ 0067 “The shape of the electrode terminals 36A as viewed in the z direction (the planar shape)…may be circular”).
Regarding Claim 4, Takeoka discloses wherein the shape of each of the second electrode terminals viewed from the thickness direction is rectangular (¶ 0070 “The shape of the electrode terminals 36B as viewed in the z direction (the planar shape)…may be…rectangular”).
Regarding Claim 5, Takeoka discloses
wherein each of the first electrode terminals (36, 36A, 361, 362; Fig. 14; ¶ 0064 “As shown in FIGS. 14 to 16, each electrode terminal 36 includes a pillar portion 361 and a solder portion 362.”) includes a first seed layer (361a; Fig. 14; ¶ 0064 “seed layer 361a”) in contact with the first electrode (Fig. 14; ¶ 0064 “seed layer 361a is in contact with the relevant electrode 34”), and a first plating layer (361b; Fig. 14; ¶ 0064 “plating layer 361b”) laminated on the first seed layer (Fig. 14; ¶ 0064 “plating layer 361b is sacked on the seed layer 361” and “plating layer 361b may be formed by electroplating”), and
wherein each of the second electrode terminals (36, 36B, 361, 362; Fig. 16; ¶ 0064 “As shown in FIGS. 14 to 16, each electrode terminal 36 includes a pillar portion 361 and a solder portion 362.”) includes a second seed layer (361a; Fig. 16; ¶ 0064 “seed layer 361a”) in contact with the second electrode (Fig. 16; ¶ 0064 “seed layer 361a is in contact with the relevant electrode 34”), and a second plating layer (361b; Fig. 16; ¶ 0064 “plating layer 361b”) laminated on the second seed layer (Fig. 16; ¶ 0064 “plating layer 361b is sacked on the seed layer 361a” and “plating layer 361b may be formed by electroplating”).
Regarding Claim 6, Takeoka discloses wherein a thickness of the first seed layer and a thickness of the second seed layer are equal to each other (¶ 0064 “The seed layer 361a may be formed by electroless plating. Yet, the material and the method for forming the seed layer 361a are not particularly limited. For example, the seed layer 361a may be formed by sputtering.”, noting that the thickness of 361a looks the same in Figs. 14-16).
Takeoka does not specifically disclose wherein a thickness of the first seed layer and a thickness of the second seed layer are equal to each other.
MPEP 2144.04(IV)( A) describes changes in size/proportion - In re Rose, 220 F.2d 459, 105 USPQ 237 (CCPA 1955) (Claims directed to a lumber package "of appreciable size and weight requiring handling by a lift truck" were held unpatentable over prior art lumber packages which could be lifted by hand because limitations relating to the size of the package were not sufficient to patentably distinguish over the prior art.); In re Rinehart, 531 F.2d 1048, 189 USPQ 143 (CCPA 1976) ("mere scaling up of a prior art process capable of being scaled up, if such were the case, would not establish patentability in a claim to an old process so scaled." 531 F.2d at 1053, 189 USPQ at 148.). In Gardner v. TEC Syst., Inc., 725 F.2d 1338, 220 USPQ 777 (Fed. Cir. 1984), cert. denied, 469 U.S. 830, 225 USPQ 232 (1984), the Federal Circuit held that, where the only difference between the prior art and the claims was a recitation of relative dimensions of the claimed device and a device having the claimed relative dimensions would not perform differently than the prior art device, the claimed device was not patentably distinct from the prior art device.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention for Takeoka to have wherein a thickness of the first seed layer and a thickness of the second seed layer are equal to each other, by using the same manufacturing process, for consistency, to form the first seed layer and the second seed layer of equal thickness, thereby simplifying the manufacturing process and reducing the total manufacturing costs.
Regarding Claim 10, Takeoka does not specifically disclose wherein a height dimension of the at least one dummy terminal is smaller than a height dimension of each of the second electrode terminals.
MPEP 2144.04(IV)( A) describes changes in size/proportion - In re Rose, 220 F.2d 459, 105 USPQ 237 (CCPA 1955) (Claims directed to a lumber package "of appreciable size and weight requiring handling by a lift truck" were held unpatentable over prior art lumber packages which could be lifted by hand because limitations relating to the size of the package were not sufficient to patentably distinguish over the prior art.); In re Rinehart, 531 F.2d 1048, 189 USPQ 143 (CCPA 1976) ("mere scaling up of a prior art process capable of being scaled up, if such were the case, would not establish patentability in a claim to an old process so scaled." 531 F.2d at 1053, 189 USPQ at 148.). In Gardner v. TEC Syst., Inc., 725 F.2d 1338, 220 USPQ 777 (Fed. Cir. 1984), cert. denied, 469 U.S. 830, 225 USPQ 232 (1984), the Federal Circuit held that, where the only difference between the prior art and the claims was a recitation of relative dimensions of the claimed device and a device having the claimed relative dimensions would not perform differently than the prior art device, the claimed device was not patentably distinct from the prior art device.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention for Takeoka to have wherein a height dimension of the at least one dummy terminal (36C) is smaller than a height dimension of each of the second electrode terminals (36B) because “electrode terminals 36C are “dummy electrode terminals” not connected to any of the first leads 10A, 10B and 10C, the second leads 21 and the third leads 22” (¶ 0094) therefore a smaller height dimension of dummy terminal 36C prevents a short circuit to any of the leads and thereby improves the performance and reliability of the semiconductor element.
Regarding Claim 11, Takeoka does not specifically disclose wherein a height dimension of the at least one dummy terminal is smaller than a height dimension of each of the first electrode terminals.
MPEP 2144.04(IV)( A) describes changes in size/proportion - In re Rose, 220 F.2d 459, 105 USPQ 237 (CCPA 1955) (Claims directed to a lumber package "of appreciable size and weight requiring handling by a lift truck" were held unpatentable over prior art lumber packages which could be lifted by hand because limitations relating to the size of the package were not sufficient to patentably distinguish over the prior art.); In re Rinehart, 531 F.2d 1048, 189 USPQ 143 (CCPA 1976) ("mere scaling up of a prior art process capable of being scaled up, if such were the case, would not establish patentability in a claim to an old process so scaled." 531 F.2d at 1053, 189 USPQ at 148.). In Gardner v. TEC Syst., Inc., 725 F.2d 1338, 220 USPQ 777 (Fed. Cir. 1984), cert. denied, 469 U.S. 830, 225 USPQ 232 (1984), the Federal Circuit held that, where the only difference between the prior art and the claims was a recitation of relative dimensions of the claimed device and a device having the claimed relative dimensions would not perform differently than the prior art device, the claimed device was not patentably distinct from the prior art device.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention for Takeoka to have wherein a height dimension of the at least one dummy terminal (36C) is smaller than a height dimension of each of the first electrode terminals (36A) because “electrode terminals 36C are “dummy electrode terminals” not connected to any of the first leads 10A, 10B and 10C, the second leads 21 and the third leads 22” (¶ 0094) therefore a smaller height dimension of dummy terminal 36C prevents a short circuit to any of the leads and thereby improves the performance and reliability of the semiconductor element.
Regarding Claim 12, Takeoka discloses
wherein an insulating layer (35; Figs. 14-16; ¶ 0062 “insulating layer 35”) having a first opening (35a; Figs. 14-15; ¶ 0062 “insulating layer 35 includes a plurality of openings 35a” and “Each opening 35a exposes one of the electrodes 34.”) and a second opening (35a; Fig. 16; ¶ 0062 “insulating layer 35 includes a plurality of openings 35a” and “Each opening 35a exposes one of the electrodes 34.”) is formed in the element front surface (¶ 0062 “formed on the element obverse surface 30a”),
wherein the first electrode terminals (36A) are electrically connected to the first electrode (34) at the first opening (Figs. 14-15; ¶ 0064 “each electrode terminal 36 includes a pillar portion 361” and “seed layer 361a is in contact with the relevant electrode 34”, ¶ 0063 “each electrode terminal 36 is in contact with an electrode 34 through an opening 35a of the insulating layer 35” and “electrode terminals 36 are electrically conductive”),
wherein the second electrode terminals (36B) are electrically connected to the second electrode (34) at the second opening (Fig. 16; ¶ 0064 “each electrode terminal 36 includes a pillar portion 361” and “seed layer 361a is in contact with the relevant electrode 34”, ¶ 0063 “each electrode terminal 36 is in contact with an electrode 34 through an opening 35a of the insulating layer 35” and “electrode terminals 36 are electrically conductive”),
wherein the at least one dummy terminal (36C) is provided over the insulating layer (Figs. 14-16; ¶ 0094 “electrode terminals 36C are similar in configuration to the electrode terminals 36A and 36B”, ¶ 0063 “each electrode terminal 36…partly overlaps with an overlapping portion 35b of the insulating layer 35”), and
wherein an area of the at least one dummy terminal (36A) viewed from a thickness direction (Fig. 19; ¶ 0093 “FIG. 19 is a plan view”) of the semiconductor element (30) is larger than an area of each of the first electrode terminals (36A) viewed from the thickness direction (¶ 0094 “the shape as viewed in the z direction (the planar shape) is not particularly limited, the electrode terminals 36C having a large area are preferable”).
Takeoka does not specifically disclose wherein an area of the at least one dummy terminal viewed from a thickness direction of the semiconductor element is larger than an area of each of the first electrode terminals viewed from the thickness direction.
MPEP 2144.04(IV)( A) describes changes in size/proportion - In re Rose, 220 F.2d 459, 105 USPQ 237 (CCPA 1955) (Claims directed to a lumber package "of appreciable size and weight requiring handling by a lift truck" were held unpatentable over prior art lumber packages which could be lifted by hand because limitations relating to the size of the package were not sufficient to patentably distinguish over the prior art.); In re Rinehart, 531 F.2d 1048, 189 USPQ 143 (CCPA 1976) ("mere scaling up of a prior art process capable of being scaled up, if such were the case, would not establish patentability in a claim to an old process so scaled." 531 F.2d at 1053, 189 USPQ at 148.). In Gardner v. TEC Syst., Inc., 725 F.2d 1338, 220 USPQ 777 (Fed. Cir. 1984), cert. denied, 469 U.S. 830, 225 USPQ 232 (1984), the Federal Circuit held that, where the only difference between the prior art and the claims was a recitation of relative dimensions of the claimed device and a device having the claimed relative dimensions would not perform differently than the prior art device, the claimed device was not patentably distinct from the prior art device.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention for Takeoka to have wherein an area of the at least one dummy terminal viewed from a thickness direction of the semiconductor element is larger than an area of each of the first electrode terminals viewed from the thickness direction because “electrode terminals 36C having a large area are preferable” (¶ 0094) and “increases the total area of the electrode terminals 36 formed in the second region 302” (¶ 0094) to improve the performance and reliability of the semiconductor element.
Regarding Claim 13, Takeoka does not specifically disclose wherein a height dimension of the at least one dummy terminal is equal to a height dimension of each of the second electrode terminals.
MPEP 2144.04(IV)( A) describes changes in size/proportion - In re Rose, 220 F.2d 459, 105 USPQ 237 (CCPA 1955) (Claims directed to a lumber package "of appreciable size and weight requiring handling by a lift truck" were held unpatentable over prior art lumber packages which could be lifted by hand because limitations relating to the size of the package were not sufficient to patentably distinguish over the prior art.); In re Rinehart, 531 F.2d 1048, 189 USPQ 143 (CCPA 1976) ("mere scaling up of a prior art process capable of being scaled up, if such were the case, would not establish patentability in a claim to an old process so scaled." 531 F.2d at 1053, 189 USPQ at 148.). In Gardner v. TEC Syst., Inc., 725 F.2d 1338, 220 USPQ 777 (Fed. Cir. 1984), cert. denied, 469 U.S. 830, 225 USPQ 232 (1984), the Federal Circuit held that, where the only difference between the prior art and the claims was a recitation of relative dimensions of the claimed device and a device having the claimed relative dimensions would not perform differently than the prior art device, the claimed device was not patentably distinct from the prior art device.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention for Takeoka to have wherein a height dimension of the at least one dummy terminal is equal to a height dimension of each of the second electrode terminals because there are no leads (10A-10C, 21, 22) below the at least one dummy terminal (therefore, there is no risk of an electrical short) and having a height dimension of the at least one dummy terminal equal to a height dimension of each of the second electrode terminals accommodates a consistent and simplified manufacturing process, thereby reducing the total manufacturing cost of the semiconductor element.
Regarding Claim 16, Takeoka discloses wherein a shape of the at least one dummy terminal viewed from a thickness direction of the semiconductor element is rectangular (¶ 0094 “Although the shape as viewed in the z direction (the planar shape) is not particularly limited, the electrode terminals 36C having a large area are preferable.” and “The electrode terminals 36C are similar in configuration to the electrode terminals 36A and 36B.”, ¶ 0072 “other preferable shapes include…a rectangle”, ¶ 0067 “viewed in the z direction (the planar shape) is not particularly limited and may be…rectangular”, therefore dummy terminal 36C is rectangular when “similar in configuration” to first and second electrode terminals 36A and 36B).
Takeoka does not specifically disclose wherein a shape of the at least one dummy terminal viewed from a thickness direction of the semiconductor element is rectangular.
MPEP 2144.04(IV)( A) describes changes in size/proportion - In re Rose, 220 F.2d 459, 105 USPQ 237 (CCPA 1955) (Claims directed to a lumber package "of appreciable size and weight requiring handling by a lift truck" were held unpatentable over prior art lumber packages which could be lifted by hand because limitations relating to the size of the package were not sufficient to patentably distinguish over the prior art.); In re Rinehart, 531 F.2d 1048, 189 USPQ 143 (CCPA 1976) ("mere scaling up of a prior art process capable of being scaled up, if such were the case, would not establish patentability in a claim to an old process so scaled." 531 F.2d at 1053, 189 USPQ at 148.). In Gardner v. TEC Syst., Inc., 725 F.2d 1338, 220 USPQ 777 (Fed. Cir. 1984), cert. denied, 469 U.S. 830, 225 USPQ 232 (1984), the Federal Circuit held that, where the only difference between the prior art and the claims was a recitation of relative dimensions of the claimed device and a device having the claimed relative dimensions would not perform differently than the prior art device, the claimed device was not patentably distinct from the prior art device.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention for Takeoka to have wherein a shape of the at least one dummy terminal viewed from a thickness direction of the semiconductor element is rectangular because “electrode terminals 36C having a large area are preferable” (¶ 0093) to improve the performance and reliability of the semiconductor element.
Regarding Claim 18, Takeoka discloses a semiconductor device (A60; Fig. 25; ¶ 0106-0110) comprising:
a substrate (81; Fig. 25; ¶ 0108 “substrate 81”) having a substrate front surface (Fig. 25; ¶ 0106 “FIG. 25 is a plan view”) on which a plurality of first front surface wirings (right side 82; Fig. 25; ¶ 0108 “wires 82 are…formed on the substrate 81”) and a plurality of second front surface wirings (left side 82; Fig. 25; ¶ 0106 “wires 82 are…formed on the substrate 81”) are formed;
the semiconductor element of Claim 1 (30, Fig. 25; ¶ 0107, 0109 “semiconductor element 30”, see the rejection of Claim 1 supra), which is mounted on both the plurality of first front surface wirings and the plurality of second front surface wirings (Fig. 25; ¶ 0109 “semiconductor element 30 is flip-chip bonded with the element obverse surface 30a directed toward the wiring board 80”, ¶ 0107 “semiconductor element 30 of the semiconductor device A50 is mounted on a wiring board and the electrode terminals 36 are connected to the wiring of the wiring board”); and
a sealing resin (40; ¶ 0106 “For convenience, FIG. 25 shows the sealing resin 40 as transparent.”) which seals the semiconductor element (¶ 0109 “sealing resin 40 (omitted in FIG. 25) covers the entirety of the semiconductor element 30”),
wherein the plurality of first electrode terminals (36A) are individually connected electrically to the plurality of first front surface wirings (Fig. 25; ¶ 0109 “electrode terminals 36 are appropriately connected to the wires 82 of the wiring board 80”), and
wherein the plurality of second electrode terminals (36B) are individually connected electrically to the plurality of second front surface wirings (Fig. 25; ¶ 0109 “electrode terminals 36 are appropriately connected to the wires 82 of the wiring board 80”).
Regarding Claim 19, Takeoka discloses a semiconductor device (A10; Figs. 1-16; ¶ 0038 “semiconductor device A10”) comprising:
a plurality of first leads (10A-10C; Figs. 2-4, 10; ¶ 0038 “plurality of first leads 10A, 10B and 10C”) and a plurality of second leads (21; Figs. 2-4; ¶ 0038 “plurality of second leads 21”);
the semiconductor element of Claim 1 (30; Figs. 2-3, 5, 10-16; ¶ 0038 “semiconductor element 30”, see the rejection of Claim 1 supra), which is mounted on both the plurality of first leads and the plurality of second leads (Figs. 2, 10-16; ¶ 0041 “first leads 10A, 10B and 10C, the second leads 21…support the semiconductor element 30”, ¶ 0055 “semiconductor element 30 is supported on the first leads 10A, 10B and 10C, the second leads 21”); and
a sealing resin (40; Figs. 6-16; ¶ 0038 “sealing resin 40”) which seals the semiconductor element (¶ 0055 “semiconductor element 30 is covered with the sealing resin 40”),
wherein the plurality of first electrode terminals (36A) are individually connected electrically to the plurality of first leads (Figs. 2-3, 10, 14-15; ¶ 0067 “electrode terminals 36A are also connected to the…first leads 10A, 10B and 10C”), and
wherein the plurality of second electrode terminals (36B) are individually connected electrically to the plurality of second leads (Figs. 2-3; ¶ 0070 “electrode terminals 36B are connected to the…second lead 21”).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Fujii JP 20200077723, Wu et al. US 2023/0163069, and Fujii et al. JP 2020077694 disclose a semiconductor element having a first electrode, a second electrode, a plurality of first electrode terminals in contact with the first electrode, and a plurality of second electrode terminals in contact with the second electrode.
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/R.K./Examiner, Art Unit 2818
/JEFF W NATALINI/Supervisory Patent Examiner, Art Unit 2818
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