DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Objections
Claim 1-20 are objected to because of the following informalities:
Claim 1 recites the limitation "a die bond pad of the plurality of die bond pads" (emphasis added) in lines 14-15. There is insufficient antecedent basis for this limitation in the claim. For the purpose of examination, the Examiner assumes the above limitation of “a die bond pad of the plurality of die bond pads” (as recited in lines 14-15) is:
“a bond pad of the plurality of bond pads” (emphasis added).
(The Applicant must use consistent language when reciting the same elements in the claims).
Claim 2 recites the limitation "the second terminals" (emphasis added) in line 1. There is insufficient antecedent basis for this limitation in the claim. For the purpose of examination, the Examiner assumes the above limitation of “the second terminals” (as recited in line 1) is:
“the second terminal” (emphasis added).
Claim 3 recites the limitation "the second terminals" (emphasis added) in line 2. There is insufficient antecedent basis for this limitation in the claim. For the purpose of examination, the Examiner assumes the above limitation of “the second terminals” (as recited in line 2) is:
“the second terminal” (emphasis added).
Claim 5 recites the limitation "the second terminals" (emphasis added) in line 1. There is insufficient antecedent basis for this limitation in the claim. For the purpose of examination, the Examiner assumes the above limitation of “the second terminals” (as recited in line 1) is:
“the second terminal” (emphasis added).
Claim 6 recites the limitation "the second terminals" (emphasis added) in line 2. There is insufficient antecedent basis for this limitation in the claim. For the purpose of examination, the Examiner assumes the above limitation of “the second terminals” (as recited in line 2) is:
“the second terminal” (emphasis added).
Claim 7 recites the limitation "the second terminals" (emphasis added) in lines 2 and 5. There is insufficient antecedent basis for this limitation in the claim. For the purpose of examination, the Examiner assumes the above limitation of “the second terminals” (as recited in lines 2 and 5) is:
“the second terminal” (emphasis added).
Claim 12 recites the limitation "a die bond pad of the plurality of die bond pads" (emphasis added) in line 11. There is insufficient antecedent basis for this limitation in the claim. For the purpose of examination, the Examiner assumes the above limitation of “a die bond pad of the plurality of die bond pads” (as recited in line 11) is:
“a bond pad of the plurality of bond pads” (emphasis added).
Claim 12 recites the limitation "the second terminals" (emphasis added) in line 13. There is insufficient antecedent basis for this limitation in the claim. For the purpose of examination, the Examiner assumes the above limitation of “the second terminals” (as recited in line 13) is:
“the second terminal” (emphasis added).
Claim 13 recites the limitation "the second terminals" (emphasis added) in lines 2-3. There is insufficient antecedent basis for this limitation in the claim. For the purpose of examination, the Examiner assumes the above limitation of “the second terminals” (as recited in lines 2-3) is:
“the second terminal” (emphasis added).
Claim 14 recites the limitation "the second terminals" (emphasis added) in line 4. There is insufficient antecedent basis for this limitation in the claim. For the purpose of examination, the Examiner assumes the above limitation of “the second terminals” (as recited in line 4) is:
“the second terminal” (emphasis added).
Claim 16 recites the limitation "the second terminals" (emphasis added) in line 1. There is insufficient antecedent basis for this limitation in the claim. For the purpose of examination, the Examiner assumes the above limitation of “the second terminals” (as recited in line 1) is:
“the second terminal” (emphasis added).
Claim 17 recites the limitation "the second terminals" (emphasis added) in lines 2 and 6. There is insufficient antecedent basis for this limitation in the claim. For the purpose of examination, the Examiner assumes the above limitation of “the second terminals” (as recited in lines 2 and 6) is:
“the second terminal” (emphasis added).
Claim 17 is not clear because it recites the limitation “the plurality of groups1” (emphasis added) in line 3. For the purpose of examination, the Examiner assumes the above limitation of “the plurality of groups1” (as recited in line 3) is:
“the plurality of groups” (emphasis added).
Claim 20 recites the limitation "wherein the first and second wafers are bonded together such that the first ends of the electrical interconnect means are electrically coupled to the die bond pads of the plurality of die bond pads" (emphasis added) in lines 9-11. There is insufficient antecedent basis for this limitation in the claim. For the purpose of examination, the Examiner assumes the above limitation of “wherein the first and second wafers are bonded together such that the first ends of the electrical interconnect means are electrically coupled to the die bond pads of the plurality of die bond pads” (as recited in lines 9-11) is:
“wherein the first and second wafers are bonded together such that the first end of the electrical interconnect means is electrically coupled to a bond pad of the plurality of bond pads” (emphasis added).
(The Applicant must use consistent language when reciting the same elements in the claims).
Appropriate correction is required.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-20 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Ramanathan et al. (U.S 2006/0040471 A1).
As to claim 1, Ramanathan et al. disclose in Fig. 2C a solid state drive (SSD) wafer device, comprising: a first semiconductor wafer (202) comprising first and second major surfaces (top and bottom surfaces) (Fig. 2C, para. [0012]), and a plurality of memory dies {“active devices” 222 may be memory dies (“DRAM” or “SRAM”), para. [0012], [0015]}, each memory die (“active device” 222) of the plurality of memory dies (“active devices” 222) comprising a plurality of bond pads (“conductors” 226) at the first major surface (top surface) (see Fig. 2C, para. [0012], [0014]-[0015]); and a second semiconductor wafer (201) comprising third and fourth major surfaces (bottom and top surfaces of 214) (Fig. 2C, para. [0012]), and a plurality of electrical interconnects (comprising “interconnect structure” 214, “conductors” 216 and 219), each electrical interconnect (comprising “interconnect structure” 214, “conductors” 216 and 219) comprising a first terminal (“conductor” 216) at the third major surface (bottom surface of 214/201), at a first end of the electrical interconnect (comprising “interconnect structure” 214, “conductors” 216 and 219) (Fig. 2C, para. [0014]), and a second terminal (“conductor” 219) at the fourth major surface (top surface of 214), at a second end of the electrical interconnect (comprising “interconnect structure” 214, “conductors” 216 and 219) opposite the first end (Fig. 2C, para. [0013], [0018], [0022]), the second terminal (conductor” 219) of each of the electrical interconnects (comprising “interconnect structure” 214, “conductors” 216 and 219) configured to transfer signals between the second semiconductor wafer (201) and an external device (such as “another integrated circuit device” or “a computer system”, para. [0003]) (Fig. 2C, para. [0003]); wherein the first major surface (top surface) of the first semiconductor wafer (202) is coupled to the third major surface (bottom surface of 214/201) of the second semiconductor wafer (201), with the first terminal (“conductor” 216) of each of the plurality of electrical interconnects (comprising “interconnect structure” 214, “conductors” 216 and 219) bonded to a bond pad (“conductor” 226) of the plurality of bond pads (“conductors” 226) (Fig. 2C, para. [0014]).
As to claim 2, as applied to claim 1 above, Ramanathan et al. disclose in Fig. 2C all claimed limitations including the limitation: wherein the second terminal (“conductor” 219) of the plurality of electrical interconnects (comprising “interconnect structure” 214, “conductors” 216 and 219) cluster together in a rectangular grid pattern at a center of the fourth major surface (top surface of 214) of the second semiconductor wafer (201) (Fig. 2C).
As to claim 3, as applied to claims 1 and 2 above, Ramanathan et al. disclose in Fig. 2C all claimed limitations including the SSD wafer device further comprising one or more SSD controllers (“logic circuitry” or “transistors”, para. [0015], [0030]) electrically coupled to the second terminal (“conductor” 219) of the plurality of electrical interconnects (comprising “interconnect structure” 214, “conductors” 216 and 219) (Fig. 2C, para. [0015], [0030]).
As to claim 4, as applied to claims 1-3 above, Ramanathan et al. disclose in Fig. 2C all claimed limitations including the limitation: wherein the at least one SSD controller (“logic circuitry” or “transistors”, para. [0015], [0030]) is flip-chip bonded to the second terminal (“conductor” 219) of at least some of the plurality of electrical interconnects (comprising “interconnect structure” 214, “conductors” 216 and 219) (Fig. 2C).
As to claim 5, as applied to claim 1 above, Ramanathan et al. disclose in Fig. 2C all claimed limitations including the limitation: wherein the second terminal (“conductor” 219) of the plurality of electrical interconnects (comprising “interconnect structure” 214, “conductors” 216 and 219) are clustered together in a plurality of groups at the fourth major surface (top surface of 214) of the second semiconductor wafer (201) (Fig. 2C, para. [0018]).
As to claim 6, as applied to claims 1 and 5 above, Ramanathan et al. disclose in Fig. 2C all claimed limitations including the SSD wafer device further comprising: one or more SSD controllers (“logic circuitry” or “transistors”, para. [0015], [0030]) electrically coupled to the second terminal (“conductor” 219) of the plurality of electrical interconnects (comprising “interconnect structure” 214, “conductors” 216 and 219) (Fig. 2C, para. [0015], [0030]).
As to claim 7, as applied to claims 1 and 5 above, Ramanathan et al. disclose in Fig. 2C all claimed limitations including the SSD wafer device further comprising: a plurality of signal/data connectors (“the vias 250”, para. [0018]) directly coupled to the second terminal (“conductor” 219) of the plurality of electrical interconnects (comprising “interconnect structure” 214, “conductors” 216 and 219) (Fig. 2C, para. [0018]); and an SSD controller (“logic circuitry” or “transistors”, para. [0015], [0030]) coupled to the plurality of signal/data connectors (“the vias 250”, para. [0018], Fig. 2C) to transfer one or both of signals and data to and from the second terminal (“conductor” 219) of the plurality of electrical interconnects (comprising “interconnect structure” 214, “conductors” 216 and 219) (Fig. 2C, para. [0018]).
As to claim 8, as applied to claims 1, 5 and 7 above, Ramanathan et al. disclose in Fig. 2C all claimed limitations including the limitation: wherein the SSD controller (“logic circuitry” or “transistors”, para. [0015], [0030]) comprises a master SSD controller (“active devices” 212 can be “transistors”, para. [0030]), and the plurality of signal/data connectors comprise SSD controllers (“logic circuitry” or “transistors”, para. [0015], [0030]) coupled to the master SSD controller (“active devices” 212 can be “transistors”, para. [0030]) (Fig. 2C, para. [0030]).
As to claim 9, as applied to claim 1 above, Ramanathan et al. disclose in Fig. 2C all claimed limitations including the limitation: wherein the first and second semiconductor wafers (202, 201) include matching circular footprints (Fig. 2C).
As to claim 10, as applied to claim 1 above, Ramanathan et al. disclose in Fig. 2C all claimed limitations including the limitation: wherein the second ends (at 219) of the electrical interconnects (comprising “interconnect structure” 214, “conductors” 216 and 219) are exposed at the fourth major surface (top surface of 214) upon thinning of the second semiconductor wafer (201) (see Figs. 2C-2E).
As to claim 11, as applied to claim 1 above, Ramanathan et al. disclose in Fig. 2C all claimed limitations including the SSD wafer device further comprising pads (“conductors” 216, 219) formed at the first and second ends of each of the electrical interconnects (comprising “interconnect structure” 214, “conductors” 216 and 219) (Fig. 2C, para. [0014], [0030]).
As to claim 12, Ramanathan et al. disclose in Fig. 2C a solid state drive (SSD) wafer device, comprising: a first semiconductor wafer (202) comprising first and second major surfaces (top and bottom surfaces) (Fig. 2C, para. [0012]), and a plurality of memory dies {“active devices” 222 may be memory dies (“DRAM” or “SRAM”), para. [0012], [0015]}, each memory die (“active device” 222) comprising a plurality of bond pads (“conductors” 226) at the first major surface (top surface) (see Fig. 2C, para. [0012], [0014]-[0015]); a second semiconductor wafer (201) bonded to the first semiconductor wafer (202) (Fig. 2C), the second semiconductor wafer (201) comprising third and fourth major surfaces (bottom and top surfaces of 214) (Fig. 2C, para. [0012]), and a plurality of electrical interconnects (comprising “interconnect structure” 214, “conductors” 216 and 219), each electrical interconnect (comprising “interconnect structure” 214, “conductors” 216 and 219) comprising a first terminal (“conductor” 216) at the third major surface (bottom surface of 214/201), at a first end of the electrical interconnect (comprising “interconnect structure” 214, “conductors” 216 and 219) (Fig. 2C, para. [0014]), and a second terminal (“conductor” 219) at the fourth major surface (top surface of 214), at a second end of the electrical interconnect (comprising “interconnect structure” 214, “conductors” 216 and 219) opposite the first end (Fig. 2C, para. [0013], [0018], [0022]), the first terminal (“conductor” 216) of each of the plurality of electrical interconnects (comprising “interconnect structure” 214, “conductors” 216 and 219) bonded to a bond pad (“conductor” 226) of the plurality of bond pads (“conductors” 226) (Fig. 2C, para. [0014]); and one or more SSD controllers (“logic circuitry” or “transistors”, para. [0015], [0030]) electrically coupled to the second terminal (“conductor” 219) of the plurality of electrical interconnects (comprising “interconnect structure” 214, “conductors” 216 and 219) (Fig. 2C, para. [0015], [0030]).
As to claim 13, as applied to claim 12 above, Ramanathan et al. disclose in Fig. 2C all claimed limitations including the limitation: wherein at least one SSD controller (“logic circuitry” or “transistors”, para. [0015], [0030]) of the one or more SSD controllers (“logic circuitry” or “transistors”, para. [0015], [0030]) comprises bond pads (“the vias 250”, para. [0018]) that are directly coupled to the second terminal (“conductor” 219) of the plurality of electrical interconnects (comprising “interconnect structure” 214, “conductors” 216 and 219) (Fig. 2C, para. [0015], [0018], [0030]).
As to claim 14, as applied to claim 12 above, Ramanathan et al. disclose in Fig. 2C all claimed limitations including the limitation: wherein the second terminal (“conductor” 219) of the plurality of interconnects (comprising “interconnect structure” 214, “conductors” 216 and 219) are grouped together in a single cluster (Fig. 2C), the one or more SSD controllers (“logic circuitry” or “transistors”, para. [0015], [0030]) comprising a single controller (“logic circuitry” or “transistors”, para. [0015], [0030]) mounted to the fourth major surface (top surface of 214) of the second semiconductor wafer (201) on top of the cluster of second terminal (219) (Fig. 2C, para. [0012], [0015], [0018], [0030]).
As to claim 15, as applied to claims 12 and 14 above, Ramanathan et al. disclose in Fig. 2C all claimed limitations including the limitation: wherein the single controller (“logic circuitry” or “transistors”, para. [0015], [0030]) is flip-chip bonded to the second terminal (“conductor” 219) of at least some of the plurality of electrical interconnects (comprising “interconnect structure” 214, “conductors” 216 and 219) (Fig. 2C).
As to claim 16, as applied to claim 12 above, Ramanathan et al. disclose in Fig. 2C all claimed limitations including the limitation: wherein the second terminal (“conductor” 219) of the plurality of electrical interconnects (comprising “interconnect structure” 214, “conductors” 216 and 219) are clustered together in a plurality of groups at the fourth major surface (top surface of 214) of the second semiconductor wafer (201) (Fig. 2C, para. [0018]).
As to claim 17, as applied to claims 12 and 16 above, Ramanathan et al. disclose in Fig. 2C all claimed limitations including the SSD wafer device further comprising:
a plurality of signal/data connectors (“the vias 250”, para. [0018]) directly coupled to the second terminal (“conductor” 219) of the plurality of electrical interconnects (comprising “interconnect structure” 214, “conductors” 216 and 219) in the plurality of groups (Fig. 2C, para. [0018]); and wherein the one or more controllers (“logic circuitry” or “transistors”, para. [0015], [0030]) comprise an SSD controller (“logic circuitry” or “transistors”, para. [0015], [0030]) coupled to the plurality of signal/data connectors (“the vias 250”, para. [0018], Fig. 2C) to transfer one or both of signals and data to and from the second terminal (“conductor” 219) of the plurality of electrical interconnects (comprising “interconnect structure” 214, “conductors” 216 and 219) (Fig. 2C, para. [0018]).
As to claim 18, as applied to claims 12, 16 and 17 above, Ramanathan et al. disclose in Fig. 2C all claimed limitations including the limitation: wherein the SSD controller (“logic circuitry” or “transistors”, para. [0015], [0030]) comprises a master SSD controller (“active devices” 212 can be “transistors”, para. [0030]), and the plurality of signal/data connectors comprise SSD controllers (“logic circuitry” or “transistors”, para. [0015], [0030]) coupled to the master SSD controller (“active devices” 212 can be “transistors”, para. [0030]) (Fig. 2C, para. [0030]).
As to claim 19, as applied to claim 12 above, Ramanathan et al. disclose in Fig. 2C all claimed limitations including the limitation: wherein the second ends (at 219) of the electrical interconnects (comprising “interconnect structure” 214, “conductors” 216 and 219) are exposed at the fourth major surface (top surface of 214) upon thinning of the second semiconductor wafer (201) (see Figs. 2C-2E).
As to claim 20, Ramanathan et al. disclose in Fig. 2C a solid state drive (SSD) wafer device, comprising: a first semiconductor wafer (202) comprising first and second major surfaces (top and bottom surfaces) (Fig. 2C, para. [0012]), and a plurality of NAND dies {“active devices” 222 may be memory dies (“DRAM” or “SRAM”), para. [0012], [0015]}, each NAND die (“active device” 222) of the plurality of NAND dies (“active devices” 222) comprising a plurality of bond pads (“conductors” 226) at the first major surface (top surface) (see Fig. 2C, para. [0012], [0014]-[0015]); a second semiconductor wafer (201) coupled to the first semiconductor wafer (202) (Fig. 2C), the second semiconductor wafer (201) comprising third and fourth major surfaces (bottom and top surfaces of 214) (Fig. 2C, para. [0012]), and electrical interconnect means (comprising “interconnect structure” 214, “conductors” 216 and 219) comprising a first end (as indicated at 216) at the third major surface (bottom surface of 214/201) and a second end (as indicated at 219) at the fourth major surface (top surface of 214) (Fig. 2C, para. [0013]-[0014], [0018]); wherein the first and second wafers (202, 201) are bonded together such that the first end (as indicated at 216) of the electrical interconnect means (comprising “interconnect structure” 214, “conductors” 216 and 219) is electrically coupled to a bond pad (“conductor” 226) of the plurality of bond pads (“conductors” 226) (Fig. 2C, para. [0014]).
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 1, 12-13, and 20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1, 8-9, and 12 of U.S. Patent No. 12,009,354. Although the claims at issue are not identical, they are not patentably distinct from each other because all the limitations recited in claims 1, 12-13, and 20 of the present invention are recited within claims 1, 8-9, and 12 of U.S. Patent No. 12,009,354.
Application No. 18/738,801 (present invention)
U.S 12,009,354 B2 (reference)
Claim 1: a solid state drive (SSD) wafer device, comprising: a first semiconductor wafer comprising first and second major surfaces, and a plurality of memory dies, each memory die of the plurality of memory dies comprising a plurality of bond pads at the first major surface (see col. 10, claim 1, lines 17-21 of the U.S 12,009,354); and
a second semiconductor wafer comprising third and fourth major surfaces, and a plurality of electrical interconnects, each electrical interconnect comprising a first terminal at the third major surface, at a first end of the electrical interconnect, and a second terminal at the fourth major surface, at a second end of the electrical interconnect opposite the first end (see col. 10, claim 1, lines 23-29 of the U.S 12,009,354),
the second terminal of each of the electrical interconnects configured to transfer signals between the second semiconductor wafer and an external device (see col. 10, claim 1, lines 29-32 of the U.S 12,009,354);
wherein the first major surface of the first semiconductor wafer is coupled to the third major surface of the second semiconductor wafer, with the first terminal of each of the plurality of electrical interconnects bonded to a die bond pad of the plurality of die bond pads (see col. 10, claim 1, lines 33-37 of the U.S 12,009,354).
Claim 1: “a solid state drive (SSD) wafer device, comprising: a first semiconductor wafer comprising first and second major surfaces, a plurality of memory dies, each memory die of the plurality of memory dies comprising a plurality of bond pads at the first major surface…”; and
“a second semiconductor wafer comprising third and fourth major surfaces, and a plurality of electrical interconnects, each electrical interconnect comprising a first terminal at the third major surface, at a first end of the electrical interconnect, and a second terminal at the third major surface, at a second end of the electrical interconnect opposite the first end”,
“the second terminal of each of the electrical interconnects configured to transfer signals between the second semiconductor wafer and an external device”;
“wherein the first major surface of the first semiconductor wafer is coupled to the third major surface of the second semiconductor wafer, with the first terminal of each of the plurality of electrical interconnects bonded to a die bond pad of the plurality of die bond pads…”.
Claim 12: a solid state drive (SSD) wafer device, comprising: a first semiconductor wafer comprising first and second major surfaces, and a plurality of memory dies, each memory die comprising a plurality of bond pads at the first major surface (see col. 10, claim 8, line 65 – col. 11, line 2 of the U.S 12,009,354);
a second semiconductor wafer bonded to the first semiconductor wafer, the second semiconductor wafer comprising third and fourth major surfaces, and a plurality of electrical interconnects, each electrical interconnect comprising a first terminal at the third major surface, at a first end of the electrical interconnect, and a second terminal at the fourth major surface, at a second end of the electrical interconnect opposite the first end, the first terminal of each of the plurality of electrical interconnects bonded to a die bond pad of the plurality of die bond pads (see col. 11, claim 8, lines 3-13 of the U.S 12,009,354);
and one or more SSD controllers electrically coupled to the second terminals of the plurality of electrical interconnects (see col. 11, claim 8, lines 13-15 of the U.S 12,009,354).
Claim 8: “a solid state drive (SSD) wafer device, comprising: a first semiconductor wafer comprising first and second major surfaces, a plurality of memory dies, each memory die comprising a plurality of bond pads at the first major surface…”;
“a second semiconductor wafer bonded to the first semiconductor wafer, the second semiconductor wafer comprising third and fourth major surfaces, and a plurality of electrical interconnects, each electrical interconnect comprising a first terminal at the third major surface, at a first end of the electrical interconnect, and a second terminal at the third major surface, at a second end of the electrical interconnect opposite the first end, the first terminal of each of the plurality of electrical interconnects bonded to a die bond pad of the plurality of die bond pads”; and
“one or more SSD controllers positioned in the one or more cutouts and electrically coupled to the second terminals of the plurality of electrical interconnects”.
Claim 13: the SSD wafer device of claim 12, wherein at least one SSD controller of the one or more SSD controllers comprises bond pads that are directly coupled to the second terminals of the plurality of electrical interconnects (see col. 11, claim 9, lines 16-19 of the U.S 12,009,354).
Claim 9: the SSD wafer device of claim 8, “wherein at least one SSD controller of the one or more SSD controllers comprises bond pads that are directly coupled to the second terminals of the plurality of electrical interconnects”.
Claim 20: a solid state drive (SSD) wafer device, comprising: a first semiconductor wafer comprising first and second major surfaces, and a plurality of NAND dies, each NAND die of the plurality of NAND dies comprising a plurality of bond pads at the first major surface (see col. 12, claim 12, lines 5-9 of the U.S 12,009,354);
a second semiconductor wafer coupled to the first semiconductor wafer, the second semiconductor wafer comprising third and fourth major surfaces, and electrical interconnect means comprising a first end at the third major surface and a second end at the fourth major surface (see col. 12, claim 12, lines 11-16 of the U.S 12,009,354);
wherein the first and second wafers are bonded together such that the first ends of the electrical interconnect means are electrically coupled to the die bond pads of the plurality of die bond pads (see col. 12, claim 12, lines 17-22 of the U.S 12,009,354).
Claim 12: “a solid state drive (SSD) wafer device, comprising: a first semiconductor wafer comprising first and second major surfaces, a plurality of NAND dies, each NAND die of the plurality of NAND dies comprising a plurality of bond pads at the first major surface…”;
“a second semiconductor wafer coupled to the first semiconductor wafer, the second semiconductor wafer comprising third and fourth major surfaces, and electrical interconnect means comprising first ends at the third major surface and second ends at the third major surface”;
“wherein the first and second wafers are bonded together such that the first ends of the electrical interconnect means are electrically coupled to the die bond pads of the plurality of die bond pads…”.
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure: Periyannan et al. (U.S 2022/0093476 A1), Ramanathan et al. (U.S 2006/0292823 A1), Kobrinsky et al. (U.S 2006/0220197 A1), Morrow et al. (US 2005/0059217 A1), and Morrow et al. (US 2004/0262772 A1) disclose first and second wafers bonded together, wherein the first wafer having a plurality of bond pads, and the second wafer having a plurality of electrical interconnects.
Contact Information
Any inquiry concerning this communication or earlier communications from the examiner should be directed to THANH Y TRAN whose telephone number is (571)272-2110. The examiner can normally be reached M-F, 10am-10pm (flex) (PST).
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/Thanh Y. Tran/Primary Examiner, Art Unit 2817 September 12, 2026
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