DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
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Claims 1 and 17 are provisionally rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-15 of copending Application No. 19/008,155 (reference application). Although the claims at issue are not identical, they are not patentably distinct from each other because application claims 1 and 17 are anticipated by claims 1-15 of the copending Application, and it is not patentably distinct from claims 1-15 of the copending Application.
Under examination claims
copending Application Claims
1. A semiconductor device comprising:
a channel layer comprising a first group III-V semiconductor material;
a barrier layer provided on an upper surface of the channel layer, the barrier layer comprising a second group III-V semiconductor material that is different than the first group III-V semiconductor material;
a plurality of sources/drains spaced apart from each other on an upper surface of the barrier layer;
a gate insulating layer covering the upper surface of the barrier layer and upper surfaces of the plurality of sources/drains;
a gate provided on an upper surface of the gate insulating layer, the gate not overlapping the plurality of sources/drains; a plurality of source/drain electrodes electrically connected to corresponding sources/drains among the plurality of sources/drains; and
a gate electrode electrically connected to the gate, wherein the plurality of source/drain electrodes has a diagonally symmetrical arrangement.
Anticipated by copending Application claim 6:
6. The power amplifier of claim 1, wherein each of the first transistor and the second transistor comprise:
a buffer layer;
a channel layer provided on an upper surface of the buffer layer, the channel layer comprising the group III-V semiconductor material;
a barrier layer provided on an upper surface of the channel layer, the barrier layer comprising a group III-V semiconductor material different from the group III-V semiconductor material of the channel layer;
a plurality of sources/drains provided to be spaced apart from each other on an upper surface of the barrier layer;
a gate insulating layer provided on the upper surface of the barrier layer and upper surfaces of the plurality of sources/drains;
a gate provided on an upper surface of the gate insulating layer so as not to overlap with the plurality of sources/drains when viewed in a direction perpendicular from the upper surface of the gate insulating layer towards the plurality of sources/drains;
a plurality of source/drain electrodes electrically connected to corresponding sources/drains among the plurality of sources/drains; and
a gate electrode electrically connected to the gate, and wherein the plurality of source/drain electrodes have a symmetrical arrangement structure in a diagonal direction when viewed from the top.
17. An electronic apparatus comprising:
a substrate comprising a first semiconductor material;
a first semiconductor device provided on the substrate; and
a second semiconductor device provided on the substrate and comprising a second semiconductor material that is different than the first semiconductor material, wherein the second semiconductor device comprises:
a channel layer comprising a first group III-V semiconductor material; a barrier layer provided on an upper surface of the channel layer, the barrier layer including a second group III-V semiconductor material that is different than the first group III-V semiconductor material;
a plurality of sources/drains spaced apart from each other on an upper surface of the barrier layer;
a gate insulating layer covering the upper surface of the barrier layer and upper surfaces of the plurality of sources/drains;
a gate provided on an upper surface of the gate insulating layer, the gate not overlapping the plurality of sources/drains;
a plurality of source/drain electrodes electrically connected to corresponding sources/drains among the plurality of sources/drains; and
a gate electrode electrically connected to the gate, and wherein the plurality of source/drain electrodes has a diagonally symmetrical arrangement.
Anticipated by copending Application claims 6 and 7:
6. The power amplifier of claim 1, wherein each of the first transistor and the second transistor comprise:
a buffer layer;
a channel layer provided on an upper surface of the buffer layer, the channel layer comprising the group III-V semiconductor material;
a barrier layer provided on an upper surface of the channel layer, the barrier layer comprising a group III-V semiconductor material different from the group III-V semiconductor material of the channel layer;
a plurality of sources/drains provided to be spaced apart from each other on an upper surface of the barrier layer;
a gate insulating layer provided on the upper surface of the barrier layer and upper surfaces of the plurality of sources/drains;
a gate provided on an upper surface of the gate insulating layer so as not to overlap with the plurality of sources/drains when viewed in a direction perpendicular from the upper surface of the gate insulating layer towards the plurality of sources/drains;
a plurality of source/drain electrodes electrically connected to corresponding sources/drains among the plurality of sources/drains; and
a gate electrode electrically connected to the gate, and wherein the plurality of source/drain electrodes have a symmetrical arrangement structure in a diagonal direction when viewed from the top (as claimed in copending Application claim 6);
wherein the third transistor is provided on a substrate comprising the group IV semiconductor material,
the substrate comprises a plurality of grooves formed in an upper surface of the substrate, and
an insulating layer is provided on the third transistor and the plurality of grooves (note: the transistor is equivalent to the claimed limitation of “the first semiconductor device”) (as claimed in copending Application claim 7).
This is a provisional nonstatutory double patenting rejection because the patentably indistinct claims have not in fact been patented.
Allowable Subject Matter
Claims 2-9 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The primary reason for the allowance of the claims is the inclusion of the limitation, along with the other claimed features, “wherein the plurality of sources/drains comprises: a first source/drain provided on a first quadrant of the upper surface of the barrier layer;
a second source/drain provided on a second quadrant of the upper surface of the barrier layer;
a third source/drain provided on a third quadrant of the upper surface of the barrier layer; and
a fourth source/drain provided on a fourth quadrant of the upper surface of the barrier layer”, as recited in claim 2.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1 and 10-16 are rejected under 35 U.S.C. 103 as being unpatentable over Briere (U.S. 2014/0097471 A1, hereinafter refer to Briere) in view of Lin et al. (U.S. 2015/0243657 A1, hereinafter refer to Lin) and Wakabayashi (JP 2008-277690 A hereinafter refer to Wakabayashi).
Regarding Claim 1: Briere discloses a semiconductor device (see Briere, Fig.5 as shown below and ¶ [0007]) comprising:
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a channel layer comprising a first group III-V semiconductor material (see Briere, Fig.5 as shown above);
a barrier layer provided on an upper surface of the channel layer, the barrier layer comprising a second group III-V semiconductor material that is different than the first group III-V semiconductor material (see Briere, Fig.5 as shown above and ¶ [0020]);
a plurality of sources/drains (512) spaced apart from each other on an upper surface of the barrier layer (see Briere, Fig.5 as shown above);
a gate insulating layer (544) covering the upper surface of the barrier layer (see Briere, Fig.5 as shown above);
a gate (510) provided on an upper surface of the gate insulating layer (544), the gate (510) not overlapping the plurality of sources/drains (512) (see Briere, Fig.5 as shown above).
Briere is silent upon explicitly disclosing wherein a gate insulating layer covering upper surfaces of the plurality of sources/drains;
a plurality of source/drain electrodes electrically connected to corresponding sources/drains among the plurality of sources/drains; and
a gate electrode electrically connected to the gate.
For support see Lin, which teaches wherein a gate insulating layer (220) covering upper surfaces of the plurality of sources/drains (120/130) (see Lin, Fig.2 as shown below and ¶ [0066]- ¶ [0067]);
a plurality of source/drain electrodes (152/154/165/175/160/170) electrically connected to corresponding sources/drains (120/130) among the plurality of sources/drains (120/130) (see Lin, Fig.2 as shown below and ¶ [0066]- ¶ [0067]); and
a gate electrode (185/180) electrically connected to the gate (145) (see Lin, Fig.2 as shown below and ¶ [0066]- ¶ [0067]).
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Thus, it would have been obvious to one of ordinary skill in the art before effective filing date of the claimed invention to combine the teachings of Briere and Lin to enable the gate insulating layer to cover upper surfaces of the plurality of sources/drains, wherein the plurality of source/drain electrodes electrically to be connected to corresponding sources/drains among the plurality of sources/drains and the gate electrode electrically to be connected to the gate as taught by Lin in order to improve the resistance of the source/drain electrode and electrically connect the transistor to the external device.
The combination of Briere and Lin is silent upon explicitly disclosing wherein the plurality of source/drain electrodes has a diagonally symmetrical arrangement.
For support see Wakabayashi, which teaches wherein the plurality of source/drain electrodes has a diagonally symmetrical arrangement (see Wakabayashi, Fig.1 as shown below and pages.4-5).
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Thus, it would have been obvious to one of ordinary skill in the art before effective filing date of the claimed invention to combine the teachings of Briere, Lin, and Wakabayashi to enable the plurality of source/drain electrodes to have a diagonally symmetrical arrangement as taught by Wakabayashi in order to obtain combined four transistor elements having common source/drain electrodes.
Regarding Claim 10: Briere as modified teaches a semiconductor device as set forth in claim 1 as above. The combination of Briere, Lin, and Wakabayashi further teaches wherein the gate (G) comprises: a central gate (G) arranged in a central portion of the upper surface of the gate insulating layer (note: not shown) (see Wakabayashi, Fig.1 as shown above); and
a plurality of branch gates (G) extending between two adjacent sources/drains (S/D) among the plurality of sources/drains (S/D) (see Wakabayashi, Fig.1 as shown above).
Regarding Claims 11 and 12: Briere as modified teaches a semiconductor device as set forth in claim 10 as above. The combination of Briere, Lin, and Wakabayashi is silent upon explicitly disclosing wherein each of the plurality of branch gates has a serpentine curve shape (as claimed in claim 11).
However, the combination of Briere, Lin, and Wakabayashi teaches wherein each of the plurality of branch gates (G) has a straight line shape (see Wakabayashi, Fig.1 as shown above) (as claimed in claim 12).
Hence, the configuration of the claimed branch gates was a matter of choice which a person of ordinary skill in the art would have found obvious absent persuasive evidence that the particular configuration of the claimed branch gates was significant.
Regarding Claim 13: Briere as modified teaches a semiconductor device as set forth in claim 10 as above. The combination of Briere, Lin, and Wakabayashi further teaches wherein the gate insulating layer (544) covers a sidewall of the barrier layer (516) and a sidewall of the channel layer (518) (see Briere, Fig.5 as shown above).
Regarding Claim 14: Briere as modified teaches a semiconductor device as set forth in claim 13 as above. The combination of Briere, Lin, and Wakabayashi further teaches wherein each of the plurality of branch gates (546/548) extends along a surface of the gate insulating layer (544) to face the sidewall of the barrier layer (516) and the sidewall of the channel layer (518) (see Briere, Fig.5 as shown above).
Regarding Claim 15: Briere as modified teaches a semiconductor device as set forth in claim 1 as above. The combination of Briere, Lin, and Wakabayashi further teaches wherein a passivation layer (150) configured to cover the gate insulating layer (220) and the gate (140/145), wherein the gate electrode (185/180) and the plurality of source/drain electrodes (152/154/165/175/160/170) pass through the passivation layer (150) (see Lin, Fig.2 as shown above).
Regarding Claim 16: Briere as modified teaches a semiconductor device as set forth in claim 1 as above. The combination of Briere, Lin, and Wakabayashi further teaches wherein the plurality of sources/drains comprises a first source/drain, a second source/drain, and a third source/drain that extend in a first direction (see Wakabayashi, Fig.1 as shown above),
wherein the first source/drain, the second source/drain, and the third source/drain are sequentially arranged in a second direction that is perpendicular to the first direction (see Wakabayashi, Fig.1 as shown above), and
wherein the gate comprises: a first branch gate extending in the first direction between the first source/drain and the second source/drain (see Wakabayashi, Fig.1 as shown above); and
a second branch gate extending in the first direction between the second source/drain and the third source/drain (see Wakabayashi, Fig.1 as shown above).
Claim(s) 17-19 are rejected under 35 U.S.C. 103 as being unpatentable over Marino (U.S. 2012/0305992 A1, hereinafter refer to Marino) in view of Briere (U.S. 2014/0097471 A1, hereinafter refer to Briere), Lin et al. (U.S. 2015/0243657 A1, hereinafter refer to Lin), and Wakabayashi (JP 2008-277690 A hereinafter refer to Wakabayashi).
Regarding Claim 17: Marino discloses an electronic apparatus (see Marino, Fig.1 as shown below and ¶ [0003]) comprising:
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a substrate (100) comprising a first semiconductor material (see Marino, Fig.1 as shown above);
a first semiconductor device (1) provided on the substrate (100) (see Marino, Fig.1 as shown above); and
a second semiconductor device (11) provided on the substrate (11) and comprising a second semiconductor material that is different than the first semiconductor material (see Marino, Fig.1 as shown above), wherein the second semiconductor device (11) comprises:
a channel layer (7) comprising a first group III-V semiconductor material (see Marino, Fig.1 as shown above);
a barrier layer (9) provided on an upper surface of the channel layer (7), the barrier layer (9) including a second group III-V semiconductor material that is different than the first group III-V semiconductor material (see Marino, Fig.1 as shown above);
a plurality of sources/drains (8/9) spaced apart from each other (see Marino, Fig.1 as shown above).
Marino is silent upon explicitly disclosing wherein a plurality of sources/drains spaced apart from each other on an upper surface of the barrier layer;
a gate insulating layer covering the upper surface of the barrier layer and upper surfaces of the plurality of sources/drains;
a gate provided on an upper surface of the gate insulating layer, the gate not overlapping the plurality of sources/drains;
For support see Briere, which teaches wherein a plurality of sources/drains (512) spaced apart from each other on an upper surface of the barrier layer (516) (see Briere, Fig.5 as shown above and ¶ [0007]);
a gate insulating layer (544) covering the upper surface of the barrier layer (516) and upper surfaces of the plurality of sources/drains (see Briere, Fig.5 as shown above and ¶ [0007]);
a gate (510) provided on an upper surface of the gate insulating layer (544), the gate (510) not overlapping the plurality of sources/drains (512) (see Briere, Fig.5 as shown above and ¶ [0007]).
Thus, it would have been obvious to one of ordinary skill in the art before effective filing date of the claimed invention to combine the teachings of Marino and Briere to enable plurality of sources/drains to be formed spaced apart from each other on an upper surface of the barrier layer, and the gate insulating layer to cover the upper surface of the barrier layer and the gate to be provided on an upper surface of the gate insulating layer, the gate not overlapping the plurality of sources/drains as taught by Briere in order to obtain a III-nitride devices that utilize a field plate defined by a dielectric body.
The combination of Marino and Briere is silent upon explicitly disclosing wherein a gate insulating layer covering the upper surface of the barrier layer and upper surfaces of the plurality of sources/drains;
a plurality of source/drain electrodes electrically connected to corresponding sources/drains among the plurality of sources/drains; and
a gate electrode electrically connected to the gate.
For support see Lin, which teaches wherein a gate insulating layer (220) covering the upper surfaces of the plurality of sources/drains (120/130) (see Lin, Fig.2 as shown above and ¶ [0066]- ¶ [0067]);
a plurality of source/drain electrodes (152/154/165/175/160/170) electrically connected to corresponding sources/drains (120/130) among the plurality of sources/drains (120/130) (see Lin, Fig.2 as shown above and ¶ [0066]- ¶ [0067]); and
a gate electrode (185/180) electrically connected to the gate (145) (see Lin, Fig.2 as shown above and ¶ [0066]- ¶ [0067]).
Thus, it would have been obvious to one of ordinary skill in the art before effective filing date of the claimed invention to combine the teachings of Marino, Briere, and Lin to enable the gate insulating layer to cover upper surfaces of the plurality of sources/drains, wherein the plurality of source/drain electrodes electrically to be connected to corresponding sources/drains among the plurality of sources/drains and the gate electrode electrically to be connected to the gate as taught by Lin in order to improve the resistance of the source/drain electrode and electrically connect the transistor to the external device.
The combination of Marino, Briere, and Lin is silent upon explicitly disclosing wherein the plurality of source/drain electrodes has a diagonally symmetrical arrangement.
For support see Wakabayashi, which teaches wherein the plurality of source/drain electrodes has a diagonally symmetrical arrangement (see Wakabayashi, Fig.1 as shown above and pages.4-5).
Thus, it would have been obvious to one of ordinary skill in the art before effective filing date of the claimed invention to combine the teachings of Marino, Briere, Lin, and Wakabayashi to enable the plurality of source/drain electrodes to have a diagonally symmetrical arrangement as taught by Wakabayashi in order to obtain combined four transistor elements having common source/drain electrodes.
Regarding Claim 18: Marino as modified teaches an electronic apparatus as set forth in claim 17 as above. The combination of Marino, Briere, Lin, and Wakabayashi further teaches wherein the first semiconductor device (1) is one of a transistor, a light-emitting device, or a sensor device (see Marino, Fig.1 as shown above).
Regarding Claim 19: Marino as modified teaches an electronic apparatus as set forth in claim 17 as above. The combination of Marino, Briere, Lin, and Wakabayashi further teaches wherein the substrate (100) comprises a recessed groove in an upper surface of the substrate (100), and wherein the second semiconductor device (11) is provided in the groove such that the gate electrode (see Marino, Fig.1 as shown above).
The combination of Marino, Briere, Lin, and Wakabayashi is silent upon explicitly disclosing wherein the plurality of source/drain electrodes face an outside of the groove.
However, practicing the combination of Marino, Briere, Lin, and Wakabayashi to modify the combination of Marino and Briere second semiconductor device to include plurality of source/drain electrodes electrically connected to corresponding sources/drains among the plurality of sources/drains and the gate electrode electrically connected to the gate according to the teachings of Lin necessarily results the claimed limitation of “the plurality of source/drain electrodes face an outside of the groove” as now specified in claim 19 (for support see Thei et al. (U.S. 2013/0146893 A1, hereinafter refer to Thei), Fig.3E).
Claim(s) 20 is rejected under 35 U.S.C. 103 as being unpatentable over Marino (U.S. 2012/0305992 A1, hereinafter refer to Marino), Briere (U.S. 2014/0097471 A1, hereinafter refer to Briere), Lin et al. (U.S. 2015/0243657 A1, hereinafter refer to Lin), and Wakabayashi (JP 2008-277690 A hereinafter refer to Wakabayashi) as applied to claim 17 above, and further in view of Lee et al. (U.S. 2019/0096782 A1, hereinafter refer to Lee).
Regarding Claim 20: Marino as modified teaches an electronic apparatus as applied to claim 17 above. The combination of Marino, Briere, Lin, and Wakabayashi is silent upon explicitly disclosing wherein the gate electrode and the plurality of source/drain electrodes face an upper surface of the substrate.
For support see Lee, which teaches wherein the gate electrode (23g) and the plurality of source/drain electrodes (23s/23d) face an upper surface of the substrate (7) (see Lee, Fig.1 and ¶ [0004]).
Thus, it would have been obvious to one of ordinary skill in the art before effective filing date of the claimed invention to combine the teachings of Marino, Briere, Lin, Wakabayashi, and Lee to enable the gate electrode and the plurality of source/drain electrodes to face an upper surface of the substrate as taught by Lee in order to obtain a highly integrated semiconductor device having improved reliability.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to BITEW A DINKE whose telephone number is (571)272-0534. The examiner can normally be reached M-F 7 a.m. - 5 p.m..
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/BITEW A DINKE/Primary Examiner, Art Unit 2812
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