DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-3, are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Hayashi, US 2017/039649 (corresponding to US10,269,831).
In re Claim 1, Hayashi discloses a display apparatus 500 (Fig. 14) comprising: a display element 520; a semiconductor pattern marked as (P1, P2) (Fig. A) including a first area P1 (consisting of 42) with a first thickness (marked as T1 in Fig. A) and a second area P2 (comprising of 42 and 41) with a second thickness T2 wherein the second thickness T2 is greater than the first thickness T1; a first transistor 2a including a first channel region C1, and corresponding to a portion of P1 between 62S and 62D as a part of the semiconductor pattern (P2, P1) and a first gate electrode 22 of which at least a part overlaps the first channel region C1; and a second transistor 1a including a second channel region C2 as a part of the semiconductor pattern (P1, P2) and a second gate electrode 21 of which at least a part overlaps the second channel region C2, wherein the second area P2 of the semiconductor pattern (P1, P2) comprises a corner portion (Fig. 14) of the semiconductor pattern (P1, P2) (Figs. 1-15; [0003 – 0120]).
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Fig. A. Hayashi’s Fig. 7 annotated to show the details cited
In re Claim 2, Hayashi discloses the display apparatus of claim 1, wherein the first transistor 2a includes a driving transistor, and the second transistor 1a includes a switching transistor, and the first channel region C1 overlaps the second area P1, and the second channel region C2 overlaps the first area P1 (Figs. 1-15; [0003 – 0120]).
In re Claim 3, Hayashi discloses the display apparatus of claim 2, wherein the first channel region C1 and the second channel region C2 are integrally provided (Figs. 1-15; [0003 – 0120]).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 8-10 are rejected under 35 U.S.C. 103 as being unpatentable over Hayashi as applied to claim 1 above.
In re Claim 8, Hayashi discloses all limitations of Claim 8, except for that edges of the corner portion of the semiconductor pattern (P1, P2) have an arc shape. Due to high level of knowledge and skills of personal capable to operate very sophisticated and expensive equipment in semiconductor technology, it would have been an obvious matter of design choice of one of ordinary skill in the semiconductor art to use the edges of the corner portion of the semiconductor pattern (P1, P2) having an arc shape, since such a modification would have involved a mere change in the shape of a component. In re Dailey, 357 F.2d 669, 149 USPQ 47 (CCPA 1966) (MPEP2144.04.IV.B).
In re Claim 9, Hayashi discloses all limitations of Claim 9, except for that a curvature of inner edges of the corner portion of the semiconductor pattern (P1, P2) is greater than a curvature of outer edges of the corner portion of the semiconductor pattern (P1, P2). Due to high level of knowledge and skills of personal capable to operate very sophisticated and expensive equipment in semiconductor technology, it would have been an obvious matter of design choice of one of ordinary skill in the semiconductor art to use a curvature of inner edges of the corner portion of the semiconductor pattern (P1, P2) is greater than a curvature of outer edges of the corner portion of the semiconductor pattern (P1, P2), since such a modification would have involved a mere change in the shape of a component. In re Dailey, 357 F.2d 669, 149 USPQ 47 (CCPA 1966) (MPEP2144.04.IV.B).
In re Claim 10, Hayashi discloses all limitations of Claim 10, except for that the first thickness T1 is 200 Å to 300 Å, and the second thickness T2 is 400 Å to 600 Å. It is known in the art that thickness is a result effective variable – because volume depends on it. Due to high level of knowledge and skills of personal capable to operate very sophisticated and expensive equipment in semiconductor technology, it would have been an obvious matter of design choice of one of ordinary skill in the semiconductor art to use the first thickness T1 is 200 Å to 300 Å, and the second thickness T2 is 400 Å to 600 Å, since it has been held that discovering an optimum value of a result effective variable involves only routine skill in the art. In re Boesch, 617 F.2d 272, 205 USPQ 215 (CCPA 1980) (MPEP2144.04).
Allowable Subject Matter
Claims 4-7 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Reason for indicating allowable subject matter
In re Claim 4: The prior art of record cited by the current office action, alone or in combination, fail to anticipate or render obvious such limitation of claim 4 as: “the semiconductor pattern comprises polycrystalline silicon, and a size of a crystalline grain included in the first area is greater than a size of a crystalline grain included in the second area”, in combination with limitations of Claims 1 and 2 on which it depends.
In re Claim 7: The prior art of record cited by the current office action, alone or in combination, fail to anticipate or render obvious such limitation of claim 7 as: “an insulating layer having a contact hole through which a part of the semiconductor pattern is exposed; and a conductive pattern on the insulating layer and of which at least a part is buried in the contact hole, wherein the contact hole overlaps the second area” in combination with limitations of Claim 1 on which it depends.
Claims 11-29 are allowed.
The following is an examiner’s statement of reasons for allowance:
In re Claim 11, prior-art fails to disclose a method of manufacturing a display apparatus, comprising steps of “forming an amorphous material layer; forming a sub-pattern including a first preliminary area and a second preliminary area having different thicknesses by half-etching the amorphous material layer; forming a polycrystalline material layer by crystallizing the amorphous material layer having the sub-pattern formed thereon.” Therefore, the claimed method differs from prior art methods on this point and there is no evidence it would have been obvious to make this change.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to NIKOLAY K YUSHIN whose telephone number is (571)270-7885. The examiner can normally be reached Monday-Friday (7-7 PST).
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Yara B. Green can be reached at 5712703075. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/NIKOLAY K YUSHIN/Primary Examiner, Art Unit 2893
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