DETAILED ACTION
Notice of AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Claim(s) 1-2, and 4-10 which are directed to Invention I, and Species II in the reply filed on 07/15/2026 is acknowledged.
Information Disclosure Statement
The information disclosure statement (IDS) filed on 05/09/2025, 09/29/2025, and 06/10/2026 is/are in compliance with provisions of 37 CFR 1.97. Accordingly, the information disclosure is being considered by the Examiner.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-2, 4-5. And 8-10 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Ho-Ming Tong et al, (hereinafter TONG), US 20240128146 A1.
Regarding Claim 1, TONG teaches a system-in-package (SIP) (Fig. 20, 19, semiconductor package), comprising:
a first package substrate (Fig. 20, 403, HTC supporter) supporting a logic die (Fig. 20, 401, processor die or a logic die, [0064]);
a second package substrate (Fig. 20, 4021, control die) supporting a stack of memory dies (Fig. 20, 4022, DRAM dies); and
semiconductor pillar bricks (Fig. 20, 440, spacers) coupled between the first package substrate (Fig. 20, 403, HTC supporter) and the second package substrate (Fig. 20, 4021, control die).
Regarding Claim 2, TONG teaches the SIP (Fig. 20, 19, semiconductor package) of claim 1, in which the semiconductor pillar bricks (Figs. 20, 440, spacers) comprise:
a silicon block (annotated Figure 20, 440, spacers, HTC material [0117], HTC material can be composed of silicon, etc., [0062]); and
through silicon vias (TSVs) (annotated Figure 20, 440 LTC/HTC spacer interconnects, [0061]) extending through the silicon block (annotated Figure 20, 440, spacers, HTC material [0117], HTC material can be composed of silicon, etc., [0062]).
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Regarding Claim 4, TONG teaches the SIP (Fig. 20, 19, semiconductor package) of claim 1, further comprising:
an embedded molding compound (EMC) (Fig. 20, 4503A, cold plate analogous to Figs. 6A-6E, 106, molding compound, [0088]) on the stack of memory dies (Fig. 20, 4022, DRAM dies) and the second package substrate (Fig. 20, 4021, control die); and
through mold vias (TMVs) (annotated Figure 20 analogous to Fig. 4, TMVs within the molding compound, 106, [0063]; TDVs or TSDVs 1521 in the spacers, 1511 and/or TMVs – not shown, [0068]; Fig. 2, 9323, plurality of TMVs formed in the mold layer, 9322, [0016]) extending between the stack of memory dies (Figs. 4/20, 102/4022, DRAM dies) and the second package substrate (Fig. 20, 4021, control die).
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Regarding Claim 5, TONG teaches the SIP (Fig. 20, 19, semiconductor package) of claim 4, further comprising a cooling lid (Fig. 20, 4503, heat sink including 4503B, the metal lid, [0090]) on the embedded molding compound (EMC) (Figs. 20, 4503A, cold plate analogous to Figs. 6A-6E shows manufacturing operations to build the semiconductor package, 10 in Fig. 4, 106, molding compound, [0088]).
Regarding Claim 8, TONG teaches the SIP (Fig. 20, 19, semiconductor package) of claim 1, in which the first package substrate (Fig. 20, 403, HTC supporter) comprises a redistribution layer (RDL) (Fig. 20, 4042, analogous to Figs. 4/5, 1035 and 1514, surface bonding layers can be part of the wiring layers or redistribution layers (RDL), [0074]).
Regarding Claim 9, TONG teaches the SIP (Fig. 20, 19, semiconductor package) of claim 1, in which the second package substrate (Figs. 20, 4021, control die) comprises a redistribution layer (RDL) (annotated Figure 20, analogous to Fig. 1B, 911).
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Regarding Claim 10, TONG teaches the SIP (Fig. 20, 19, semiconductor package) of claim 1, in which the stack of memory dies (Fig. 20, 4022, DRAM dies) comprises a high-bandwidth memory (HBM) dynamic random-access memory (DRAM) stack (Fig. 20, 4021, memory structure, IC blocks covering 3D IC such as high-bandwidth-memory (HBM) dynamic random-access memory (DRAM) stack, [0005]).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 6 is/are rejected under 35 U.S.C. 103 as being unpatentable over TONG, as applied to Claims 1-2, 4-5, 8-10 as above, and further in view of Weston Bertrand et al, (hereinafter BERTRAND), US 20230128903 A1.
Regarding Claim 6, TONG the SIP (Fig. 20, 19, semiconductor package) of claim 1, in which the embedded molding compound (EMC) (Figs. 20, 4503A, heat spreader analogous to Figs. 6A-6E, 106, molding compound, [0088]) comprises a thermally conductive material (Fig. 20, 4503A, HTC layer, (e.g. made of diamond), [0070]),
Though TONG teaches the SIP, in which the embedded molding compound (EMC) comprises a HTC material made of diamond, which is the good thermally conductive material, TONG does not explicitly disclose the SIP, in which the embedded molding compound (EMC) ) comprises a thermally conductive material.
BERTRAND teaches the SIP (Fig. 1. illustrates a side view of a legacy stacked die package. [0027]) , in which the embedded molding compound (EMC) comprises a thermally conductive material (Fig. 4A, 439, thermal block may include a thermally conductive mold material that may be used to conduct thermal energy from the base die, 426 to the TIM, 432, [0041]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to have modified TONG to incorporate the teachings of BERTRAND, such that the SIP, in which the embedded molding compound (EMC) comprises a thermally conductive material, so that the thermal block may be used to conduct thermal energy from the base die to the TIM (BERTRAND, [0041]).
Claim(s) 7 is/are rejected under 35 U.S.C. 103 as being unpatentable over TONG, as applied to Claims 1-2, 4-5, 8-10 as above, and further in view of Jong Hoon Kim et al, (hereinafter KIM), US 20200273800 A1.
Regarding Claim 7, TONG teaches the SIP of claim 1.
TONG does not explicitly disclose the SIP, further comprising a planarization layer between the logic die and the second package substrate.
KIM teaches the SIP (Fig. 7, 11), further comprising a planarization layer (Fig. 7, 690L, adhesive layer) between the logic die (Fig. 7, 300, first semiconductor chip) and the second package substrate (Fig. 7, 400, second semiconductor chip).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to have modified TONG to incorporate the teachings of KIM, such that the SIP, further comprising a planarization layer between the logic die and the second package substrate, so that the adhesive layer, 690L may prevent the second semiconductor chip, 400 from being inclined when the protrusion, 435 of the second semiconductor chip, 400 is bonded to and supported by the bridge die, 500, and further the adhesive layer, 690L may support and help the second semiconductor chip, 400 to maintain a horizontal level (KIM, [0059]).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
US 20140225248 A1 – Figure 4
STATEMENT OF RELEVANCE – A die package with a heat spreader integrated in a power distribution network of the die package.
US 20190206833 A1 – Figure 1
STATEMENT OF RELEVANCE – A cross-sectional illustration of an embedded wafer level ball grid array (eWLB) or embedded panel level ball grid array (ePLB) package on package (PoP) stacking which is an important system in package (SiP).
US 20220209391 A1 – Figure 1
STATEMENT OF RELEVANCE – A cross-sectional view of a disclosed an antenna in package (AIP), wherein a metal pillar, 132a1 is coupled between the package substrate, 110 and the bottom side package substrate, 130.
US 20220344247 A1 – Figure 1B
STATEMENT OF RELEVANCE – A cross-sectional illustration of an ultra-thin, hyper-density semiconductor package, 150, wherein the pillars, 154 coupled between a substrate, 108 and a pitch translation interposer, 106 to the package, 128.
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/SESHA SAIRAMAN SRINIVASAN/ Examiner, Art Unit 2817
/ALI NARAGHI/ Primary Examiner, Art Unit 2817
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