DETAILED ACTION
The Amendment filed April 08, 2026 has been entered. Claims 1-20 are pending. Claims 3 and 13 have been cancelled. Claims 1 and 11 are independent.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of AIA 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-2 and 11-12 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Tachibana (US 2022/0093162).
Regarding independent claims 1 and its method independent claim 11, Tachibana discloses a pre-charge system comprising:
a pre-charge circuit (see e.g., FIG. 2: LPR1-n), arranged to perform time-division pre-charge (see FIG. 12, time-division) upon a plurality of bit-line groups of a memory array according to a plurality of pre-charge timing control signals wherein the memory array comprises a plurality of memory cells each coupled to one of the plurality of bit-line groups (FIG. 2: LPRE1 for LBL11, LPRE2 for LBL21 and LPREn for LBLn1) (see FIGS. 2 and 12 and accompanying disclosure); and
a timing controller circuit (FIG. 1: Controller 14), arranged to generate and output the plurality of pre-charge timing control signals to the pre-charge circuit (see e.g., FIGS. 1-2 and 12, and accompanying disclosure).
wherein the plurality of bit-line groups comprise a first bit-line group that corresponds to a same memory cell column of the memory array (see e.g., FIG. 2: the plurality of bit line groups, LBL11 through LBLn1, and LBL11 memory cells, LBL21 memory cells and LBLn1 memory cells), and one pre-charging of a same bit-line included in the first bit-line group is divided into a plurality of phases that are sequentially enabled by the plurality of pre-charge timing control signals (see e. g., FIG. 12, i.e., sequentially enabled to Pre-charging (LPRE) – Word line enabling (WL) – Bit line activated).
Regarding claims 2 and 12, which depends from claims 1 and 11, respectively.
Tachibana discloses each of the plurality of memory cells is a static random access memory (SRAM) cell (FIG. 3).
Claim Rejections - 35 USC § 103
The following is a quotation of AIA 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 4-5 and 14-15 are rejected under AIA 35 U.S.C. 103 as being unpatentable over Tachibana (US 2022/0093162) in view of e.g., Robison et al. (US 2019/0189196).
Regarding claims 4 and 14, Tachibana teaches the limitations of claims 1 and 11, respectively.
Tachibana further teaches the pre-charge circuit comprises: a plurality of pre-charge sub-circuits, coupled to the plurality of bit-line groups, respectively, wherein each of the plurality of pre-charge sub-circuits receives the plurality of pre-charge timing control signals, and comprises: an equalizer; and a pre-charge device; wherein the plurality of pre-charge timing control signals generated from the timing controller circuit enable the equalizer and the pre-charge device sequentially (see e.g., FIGS. 1-2 and accompanying disclosure).
Tachibana does not explicitly disclose an equalizer.
However, an equalizer in pre-charging circuit is a well-known technology in memory devices.
Further, segmented pre-charge circuit being enabled sequentially is a well-known technology for a type of memory for its purpose.
For support, of the above asserted facts, see for example, Robison et al. (US 2019/0189196), FIGS 2-3 and accompanying disclosure, i.e., PCH_1 through PCN_N.
It would have been obvious to one of ordinary skill in the art before the effective filing date to apply the teaching of Robison et al. to the teaching of Tachibana such that a memory, as taught by Tachibana, utilizes sequential bit-line pre-charging, as taught by Robison et al., for the purpose of charging segment of memory arrays, thereby saving power including leakage current.
Regarding claims 5 and 15, Tachibana teaches the limitations of claims 1 and 11, respectively.
Tachibana further teaches the pre-charge circuit comprises: a plurality of pre-charge sub-circuits, coupled to the plurality of bit-line groups, respectively, wherein each of the plurality of pre-charge sub-circuits receives the plurality of pre-charge timing control signals, and comprises: a first pre-charge device; and a second pre-charge device, wherein pre-charge strength of the second pre-charge device is larger than pre-charge strength of the first pre-charge device; wherein the plurality of pre-charge timing control signals generated from the timing controller circuit enable the first pre-charge device and the second pre-charge device sequentially (see e.g., FIGS. 1-2 and accompanying disclosure).
Tachibana does not explicitly disclose pre-charge strength.
Robison et al. teach the deficiencies in e.g., FIGS. 2-3 and accompanying disclosure, i.e., sequential pre-charging with different strength.
It would have been obvious to one of ordinary skill in the art before the effective filing date to apply the teaching of Robison et al. to the teaching of Tachibana such that a memory, as taught by Tachibana, utilizes sequential bit-line pre-charging, as taught by Robison et al., for the purpose of charging segment of memory arrays, thereby saving power including leakage current.
Claims 6-10 and 16-20 are rejected under AIA 35 U.S.C. 103 as being unpatentable over Tachibana (US 2022/0093162) in view of Yang et al. (US 9,685,224).
Regarding claims 6-7 and 16-17, Tachibana teaches the limitations of claims 1 and 11, respectively.
Tachibana does not explicitly disclose the timing controller circuit comprises: an adjustable delay circuit, arranged to adjust an interval between two of the plurality of pre-charge timing control signals; and the adjustable delay circuit operates in response to a user input.
However, the claimed limitation is a well-known technology for a type of memory for its purpose.
For support, of the above asserted facts, see for example, Yang et al. (US 9,685,224), e.g., col. 6, lines 35-40: … a delay circuit to delay activation of the pre charge circuits …; and col. 9, line 58: … receive a delay signal CKPB_DLY.
It would have been obvious to one of ordinary skill in the art before the effective filing date to utilize static random access memory used as configuration random access memory in pre-charging circuits because these conventional technology are well established in the art of the memory devices.
Regarding claims 8 and 18, Tachibana teaches the limitations of claims 1 and 11, respectively.
Tachibana does not explicitly disclose the limitations of claims 8 and 18.
Yang et al. teach the deficiencies, i.e., the timing controller circuit comprises: a tracking circuit, arranged to adjust an interval between two of the plurality of pre-charge timing control signals by monitoring at least one parameter of the memory array (e.g., col. 6, lines 7-40, i.e., sequentially controlling pre-charge signals by adjusting RC delay (claimed monitoring at least one parameter of the memory array)).
It would have been obvious to one of ordinary skill in the art before the effective filing date to apply the teaching of Yang et al. to the teaching of Tachibana such that a memory, as taught by Tachibana, utilizes timing circuitry, as taught by Yang et al., for the purpose of controlling charging segment of memory arrays, thereby improving memory performance.
Yang et al.’ timing control circuit do not explicitly disclose a tracking circuit.
However, a tracking circuit tracks signals in a memory device is a well-known technology for a type of memory for its purpose.
It would have been obvious to one of ordinary skill in the art before the effective filing date to utilize static random access memory used as configuration random access memory in tracking circuits because these conventional technology are well established in the art of the memory devices.
Regarding claims 9 and 19, Tachibana and Yang et al. teach the limitations of claims 8 and 18, respectively.
Yang et al. further teach the at least one parameter of the memory array comprises a number of memory cells in a bit-line direction (e.g., FIG. 1., i.e., RC delay in bit-line direction).
It would have been obvious to one of ordinary skill in the art before the effective filing date to further modify the invention of Yang et al. for the same purpose of controlling charging segment of memory arrays, thereby improving memory performance.
Regarding claims 10 and 20, Tachibana and Yang et al. teach the limitations of claims 8 and 18, respectively.
Yang et al. further teach the at least one parameter of the memory array comprises a number of memory cells in a word-line direction (e.g., FIG. 1., i.e., RC delay in word-line direction).
It would have been obvious to one of ordinary skill in the art before the effective filing date to further modify the invention of Yang et al. for the same purpose of controlling charging segment of memory arrays, thereby improving memory performance.
Response to Argument
Applicant’s arguments filed 04/08/2026, with respect to the rejection(s) of claims under 35 USC 102 and 103, have been fully considered but are moot in view of the new ground(s) of rejection.
Therefore, it is respectfully submitted that the examiner maintains the rejection.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SUNG IL CHO whose telephone number is (571)270-0137. The examiner can normally be reached on M-Th, 7:30AM-5PM; Every other F, 7:30AM-4PM EST.
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/SUNG IL CHO/ Primary Examiner, Art Unit 2825
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