DETAILED ACTION
This action is responsive to the following communications: the Application filed June 11, 2024, and the information disclosure statement (IDS) filed June 11, 2024. This application has PRO 63/472,354 06/12/2023.
Claims 1-20 are pending. Claims 1 and 11 are independent.
Notice of Pre-AIA or AIA Status
The present application is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on June 11, 2024 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of AIA 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-2, 6-7, 11-12 and 16-17 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Yang et al. (US 9,685,224).
Regarding independent claims 1 and its method independent claim 11, Yang et al. disclose a pre-charge system (see e.g., FIG. 1) comprising:
a pre-charge circuit (125), arranged to perform time-division pre-charge (FIG. 1, columns in 113[P] pre-charged when BLSS1 enabled, and columns in 113[1] pre-charged when BLSS2 enabled; also see e.g., col. 7, lines 32-35: … The selective maintenance of at least some of the bit line pairs BL/BLB in the precharge state …) upon a plurality of bit-line groups of a memory array according to a plurality of pre-charge timing control signals wherein the memory array comprises a plurality of memory cells each coupled to one of the plurality of bit-line groups (see FIG. 1: 113 along with MCs); and
a timing controller circuit (111 CNT), arranged to generate and output the plurality of pre-charge timing control signals to the pre-charge circuit (see e.g., FIG. 1 and accompanying disclosure, e.g., col. 4, lines 18-30: … controller 111…).
Regarding claims 2 and 12, which depends from claims 1 and 11, respectively.
Yang et al. disclose each of the plurality of memory cells is a static random access memory (SRAM) cell (FIG. 1: MC, and col. 2, line 36: SRAM).
Regarding claims 6 and 16, which depends from claims 1 and 11, respectively.
Yang et al. disclose the timing controller circuit comprises: an adjustable delay circuit, arranged to adjust an interval between two of the plurality of pre-charge timing control signals (e.g., col. 6, lines 35-40: … a delay circuit to delay activation of the precharge circuits …; further, delaying (adjusting) pre-charging is a well-known technology in a memory device).
Regarding claims 7 and 17, which depends from claims 6 and 16, respectively.
Yang et al. disclose the adjustable delay circuit operates in response to a user input (col. 9, line 58: receive a delay signal CKPB_DLY).
Claim Rejections - 35 USC § 103
The following is a quotation of AIA 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 3-5 and 13-15 are rejected under AIA 35 U.S.C. 103 as being unpatentable over Yang et al. (US 9,685,224) in view of e.g., Robison et al. (US 2019/0189196).
Regarding claims 3 and 13, Yang et al. teach the limitations of claims 1 and 11, respectively.
Yang et al. further teach the pre-charge circuit comprises: a plurality of pre-charge sub-circuit groups, each comprising at least one pre-charge sub-circuit coupled to at least one of the plurality of bit-line groups and receiving one of the plurality of pre-charge timing control signals; wherein the plurality of pre-charge timing control signals generated from the timing controller circuit enable the plurality of pre-charge sub-circuit groups sequentially (see e.g., col. 6, lines 35-40: … a delay circuit … to precharge in a sequence …).
Further, segmented pre-charge circuit being enabled sequentially is a well-known technology for a type of memory for its purpose.
For support, of the above asserted facts, see for example, Robison et al., FIGS 2-3 and accompanying disclosure, i.e., PCH_1 through PCN_N.
It would have been obvious to one of ordinary skill in the art before the effective filing date to apply the teaching of Robison et al. to the teaching of Yang et al. such that a memory, as taught by Yang et al., utilizes sequential bit-line pre-charging, as taught by Robison et al., for the purpose of charging segment of memory arrays, thereby saving power including leakage current.
Regarding claims 4 and 14, Yang et al. teach the limitations of claims 1 and 11, respectively.
Yang et al. further teach the pre-charge circuit comprises: a plurality of pre-charge sub-circuits, coupled to the plurality of bit-line groups, respectively, wherein each of the plurality of pre-charge sub-circuits receives the plurality of pre-charge timing control signals, and comprises: an equalizer; and a pre-charge device; wherein the plurality of pre-charge timing control signals generated from the timing controller circuit enable the equalizer and the pre-charge device sequentially (see e.g., FIG. 1 and accompanying disclosure).
Yang et al. do not explicitly disclose an equalizer.
However, an equalizer in pre-charging circuit is a well-known technology in memory devices.
Further, segmented pre-charge circuit being enabled sequentially is a well-known technology for a type of memory for its purpose.
For support, of the above asserted facts, see for example, Robison et al. (US 2019/0189196), FIGS 2-3 and accompanying disclosure, i.e., PCH_1 through PCN_N.
It would have been obvious to one of ordinary skill in the art before the effective filing date to apply the teaching of Robison et al. to the teaching of Yang et al. such that a memory, as taught by Yang et al., utilizes sequential bit-line pre-charging, as taught by Robison et al., for the purpose of charging segment of memory arrays, thereby saving power including leakage current.
Regarding claims 5 and 15, Yang et al. teach the limitations of claims 1 and 11, respectively.
Yang et al. further teach the pre-charge circuit comprises: a plurality of pre-charge sub-circuits, coupled to the plurality of bit-line groups, respectively, wherein each of the plurality of pre-charge sub-circuits receives the plurality of pre-charge timing control signals, and comprises: a first pre-charge device; and a second pre-charge device, wherein pre-charge strength of the second pre-charge device is larger than pre-charge strength of the first pre-charge device; wherein the plurality of pre-charge timing control signals generated from the timing controller circuit enable the first pre-charge device and the second pre-charge device sequentially (see e.g., FIG. 1 and accompanying disclosure).
Yang et al. do not explicitly disclose pre-charge strength.
Robison et al. teach the deficiencies in e.g., FIGS. 2-3 and accompanying disclosure, i.e., sequential pre-charging with different strength.
It would have been obvious to one of ordinary skill in the art before the effective filing date to apply the teaching of Robison et al. to the teaching of Yang et al. such that a memory, as taught by Yang et al., utilizes sequential bit-line pre-charging, as taught by Robison et al., for the purpose of charging segment of memory arrays, thereby saving power including leakage current.
Claims 8-10 and 18-20 are rejected under AIA 35 U.S.C. 103 as being unpatentable over Yang et al. (US 9,685,224).
Regarding claims 8 and 18, Yang et al. teach the limitations of claims 1 and 11, respectively.
Yang et al. further teach the timing controller circuit comprises: a tracking circuit, arranged to adjust an interval between two of the plurality of pre-charge timing control signals by monitoring at least one parameter of the memory array (e.g., col. 6, lines 7-40, i.e., sequentially controlling pre-charge signals by adjusting RC delay (claimed monitoring at least one parameter of the memory array)).
Yang et al. do not explicitly disclose a tracking circuit.
However, a tracking circuit tracks signals in a memory device is a well-known technology for a type of memory for its purpose.
It would have been obvious to one of ordinary skill in the art before the effective filing date to utilize static random access memory used as configuration random access memory in tracking circuits because these conventional technology are well established in the art of the memory devices.
Regarding claims 9 and 19, Yang et al. teach the limitations of claims 8 and 18, respectively.
Yang et al. further teach the at least one parameter of the memory array comprises a number of memory cells in a bit-line direction (e.g., FIG. 1., i.e., RC delay in bit-line direction)
Regarding claims 10 and 20, Yang et al. teach the limitations of claims 8 and 18, respectively.
Yang et al. further teach the at least one parameter of the memory array comprises a number of memory cells in a word-line direction (e.g., FIG. 1., i.e., RC delay in word-line direction)
Conclusion
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/SUNG IL CHO/Primary Examiner, Art Unit 2825