DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1 – 5, 12, and 13 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Randall et al. (US 2008/0192452).
Regarding claim 1, Randall teaches (FIG. 4, 5, 9):
A decoupling capacitor structure comprising:
a first interposer (21) having a first surface and an opposing second surface; and
a decoupling capacitor (22) having a first surface and an opposing second surface, wherein the decoupling capacitor contains alternating dielectric layers and internal electrode layers (FIG. 9), the internal electrode layers containing first internal electrode layers and second internal electrode layers, wherein the decoupling capacitor further contains a first external terminal (26 top) that is electrically connected to the first internal electrode layers and disposed on a first surface of the decoupling capacitor, a second external terminal (26 bottom) that is electrically connected to the first internal electrode layers and disposed on the second surface of the decoupling capacitor, a third external terminal (26’ top) that is electrically connected to the second internal electrode layers and disposed on the first surface of the decoupling capacitor, and a fourth external terminal (26’ bottom) that is electrically connected to the second internal electrode layers and disposed on the second surface of the decoupling capacitor,
wherein the decoupling capacitor is disposed adjacent the first interposer such that the first surface of the decoupling capacitor is adjacent the second surface of the first interposer (FIG. 4), and
wherein the first external terminal and the third external terminal are electrically connected to the first interposer (through 35).
Regarding claim 2, Randall teaches (FIG. 4, 5, 9):
The decoupling capacitor structure of claim 1, further comprising: a second interposer (31 – examiner notes that the instant application generally defines “interposer” as “includes an insulating material and one or more conductive pathways”; a PCB meets these limitations) having a first surface and an opposing second surface, wherein the decoupling capacitor is disposed between the first interposer and the second interposer such that the second surface of the decoupling capacitor is adjacent the first surface of the second interposer, and wherein the second external terminal and the fourth external terminal are electrically connected to the second interposer (FIG. 4).
Regarding claim 3, Randall teaches (FIG. 2):
The decoupling capacitor structure of claim 1, wherein the decoupling capacitor is one of a plurality of decoupling capacitors, wherein each decoupling capacitor of the plurality of decoupling capacitors has a first surface and an opposing second surface, wherein each decoupling capacitor of the plurality of decoupling capacitors contains alternating dielectric layers and internal electrode layers, the internal electrode layers containing first internal electrode layers and second internal electrode layers, wherein each decoupling capacitor of the plurality of decoupling capacitors further contains a first external terminal that is electrically connected to the first internal electrode layers and disposed on a first surface of the decoupling capacitor, a second external terminal that is electrically connected to the first internal electrode layers and disposed on the second surface of the decoupling capacitor, a third external terminal that is electrically connected to the second internal electrode layers and disposed on the first surface of the decoupling capacitor, and a fourth external terminal that is electrically connected to the second internal electrode layers and disposed on the second surface of the decoupling capacitor.
Regarding claim 4, Randall teaches (FIG. 2):
The decoupling capacitor structure of claim 3, wherein each decoupling capacitor of the plurality of decoupling capacitors is disposed adjacent the first interposer such that the first surface of each decoupling capacitor of the plurality of decoupling capacitors is adjacent the second surface of the first interposer, and wherein the first external terminal and the third external terminal of each decoupling capacitor of the plurality of decoupling capacitors are electrically connected to the first interposer.
Regarding claim 5, Randall teaches (FIG. 4, 5, 9):
The decoupling capacitor structure of claim 4, further comprising: a second interposer (31 – examiner notes that the instant application generally defines “interposer” as “includes an insulating material and one or more conductive pathways”; a PCB meets these limitations) having a first surface and an opposing second surface, wherein each decoupling capacitor of the plurality of decoupling capacitors is disposed between the first interposer and the second interposer such that the second surface of each decoupling capacitor of the plurality of decoupling capacitors is adjacent the first surface of the second interposer, and wherein the second external terminal and the fourth external terminal of each decoupling capacitor of the plurality of decoupling capacitors are electrically connected to the second interposer (FIG. 4).
Regarding claim 12, Randall teaches:
The decoupling capacitor structure of claim 1, wherein the first interposer comprises at least one first via (30) extending from the first surface of the first interposer to the second surface of the first interposer, the at least one first via filled with a conductive material (FIG. 4, [0034]).
Regarding claim 13, Randall teaches:
The decoupling capacitor structure of claim 12, wherein the at least one first via includes two first vias, one of the two first vias in contact with the first external terminal and the other of the two first vias in contact with the third external terminal to electrically connect the first external terminal and the third external terminal with the first interposer (FIG. 4).
Claims 15 – 23 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Naito et al. (US 6,606,237).
Regarding claim 15, Naito teaches (FIG. 10, 17, and associated text):
A decoupling capacitor assembly comprising:
a substrate (60) defining a cavity (61) therein; and
a decoupling capacitor structure (11) disposed in the cavity, the decoupling capacitor structure comprising:
a first interposer (69) having a first surface and an opposing second surface; and
a decoupling capacitor having a first surface and an opposing second surface, wherein the decoupling capacitor contains alternating dielectric layers and internal electrode layers, the internal electrode layers containing first internal electrode layers and second internal electrode layers, wherein the decoupling capacitor further contains a first external terminal that is electrically connected to the first internal electrode layers and disposed on a first surface of the decoupling capacitor, a second external terminal that is electrically connected to the first internal electrode layers and disposed on the second surface of the decoupling capacitor, a third external terminal that is electrically connected to the second internal electrode layers and disposed on the first surface of the decoupling capacitor, and a fourth external terminal that is electrically connected to the second internal electrode layers and disposed on the second surface of the decoupling capacitor (FIG. 17),
wherein the decoupling capacitor is disposed adjacent the first interposer such that the first surface of the decoupling capacitor is adjacent the second surface of the first interposer (FIG. 10), and
wherein the first external terminal and the third external terminal are electrically connected to the first interposer (65, 66).
Regarding claim 16, Naito teaches (FIG. 10):
The decoupling capacitor assembly of claim 15, wherein the decoupling capacitor structure further comprises a second interposer (70) having a first surface and an opposing second surface, wherein the decoupling capacitor is disposed between the first interposer and the second interposer such that the second surface of the decoupling capacitor is adjacent the first surface of the second interposer, and wherein the second external terminal and the fourth external terminal are electrically connected to the second interposer (67, 68).
Regarding claim 17, Naito teaches a plurality of capacitor units throughout the disclosure:
The decoupling capacitor assembly of claim 15, wherein the decoupling capacitor structure is one of a plurality of decoupling capacitor structures disposed in the cavity.
Regarding claim 18, Naito teaches:
The decoupling capacitor assembly of claim 17, wherein a resin (62) surrounds the plurality of decoupling capacitor structures in the cavity.
Regarding claim 19, Naito teaches:
The decoupling capacitor assembly of claim 15, wherein the first interposer is electrically connected to the substrate (65 – 68).
Regarding claim 20, Naito teaches a plurality of capacitor units with individual connections (FIG. 17):
The decoupling capacitor assembly of claim 15, wherein the decoupling capacitor is one of a plurality of decoupling capacitors in the decoupling capacitor structure, wherein each decoupling capacitor of the plurality of decoupling capacitors has a first surface and an opposing second surface, wherein each decoupling capacitor of the plurality of decoupling capacitors contains alternating dielectric layers and internal electrode layers, the internal electrode layers containing first internal electrode layers and second internal electrode layers, wherein each decoupling capacitor of the plurality of decoupling capacitors further contains a first external terminal that is electrically connected to the first internal electrode layers and disposed on a first surface of the decoupling capacitor, a second external terminal that is electrically connected to the first internal electrode layers and disposed on the second surface of the decoupling capacitor, a third external terminal that is electrically connected to the second internal electrode layers and disposed on the first surface of the decoupling capacitor, and a fourth external terminal that is electrically connected to the second internal electrode layers and disposed on the second surface of the decoupling capacitor.
Regarding claim 21, Naito teaches (FIG. 10):
A method of forming a reduced component structure, the method comprising:
disposing a plurality of components adjacent a first sacrificial plate;
applying a resin (62) around the plurality of components;
forming one or more vias (col 17 - 18) through the first sacrificial plate;
filling the one or more vias with a conductive material (col 17 - 18); and
removing at least a portion of the first sacrificial plate along a Z-direction (col 17 - 18).
Regarding claim 22, Naito teaches:
The method of claim 21, wherein removing at least a portion of the first sacrificial plate comprises grinding the first sacrificial plate along a first surface of the first sacrificial plate (col 17 - 18).
Regarding claim 23, Naito teaches:
The method of claim 21, further comprising, after applying the resin: disposing a second sacrificial plate adjacent the plurality of components, the second sacrificial plate opposite the first sacrificial plate along the Z-direction such that the plurality of components are sandwiched between the first sacrificial plate and the second sacrificial plate (col 17 - 18).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 6 – 11, and 14 are rejected under 35 U.S.C. 103 as being unpatentable over Randall et al. (US 2008/0192452) as applied to claim 5 above, and further in view of Naito et al. (US 6,606,237).
Regarding claim 6, Randall teaches (FIG. 4):
The decoupling capacitor structure of claim 5, wherein the first interposer comprises at least one first via (30) extending from the first surface of the first interposer to the second surface of the first interposer.
Randall teaches electrical connections 35 in the second interposer, but fails to expressly disclose
wherein the second interposer comprises at least one second via extending from the first surface of the second interposer to the second surface of the second interposer
However, Naito teaches embedded decoupling capacitor structures with upper and lower resin plate members 69 and 70 having holes formed in the resin plate members as necessary to complete the desired circuits.
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to form through hole connections as disclosed by Naito to enable electrical connections through the structure of Randall in a conventional manner.
Regarding claim 7, Randall teaches:
The decoupling capacitor structure of claim 6, wherein the at least one first via and the at least one second via are filled with a conductive material ([0034]).
Regarding claim 8, Randall teaches:
The decoupling capacitor structure of claim 6, wherein the at least one first via is in contact with one of the first external terminal or the third external terminal of a respective one decoupling capacitor of the plurality of decoupling capacitors (FIG. 4).
Regarding claim 9, Randall teaches:
The decoupling capacitor structure of claim 6, wherein the at least one second via is in contact with one of the second external terminal or the fourth external terminal of a respective one decoupling capacitor of the plurality of decoupling capacitors (FIG. 4).
Regarding claim 10, Randall teaches:
The decoupling capacitor structure of claim 6, wherein the at least one first via includes two first vias, one of the two first vias in contact with a first external terminal of a respective one decoupling capacitor of the plurality of decoupling capacitors and the other of the two first vias in contact with the third external terminal of the respective one decoupling capacitor to electrically connect the first external terminal and the third external terminal of the respective one decoupling capacitor with the first interposer (FIG. 4).
Regarding claim 11, Randall teaches:
The decoupling capacitor structure of claim 10, wherein the at least one second via includes two second vias, one of the two second vias in contact with the second external terminal of the respective one decoupling capacitor and the other of the two second vias in contact with the fourth external terminal of the respective one decoupling capacitor to electrically connect the second external terminal and the fourth external terminal of the respective one decoupling capacitor with the second interposer (FIG. 4).
Regarding claim 14, Naito teaches (col 17 - 18):
The decoupling capacitor structure of claim 2, wherein the first interposer is a first sacrificial plate and the second interposer is a second sacrificial plate, and wherein each of the first sacrificial plate and the second sacrificial plate is configured to be ground to reduce a height of each of the first sacrificial plate and the second sacrificial plate.
Claims 24 – 28 are rejected under 35 U.S.C. 103 as being unpatentable over Bultitude et al. (US 2019/0080982) in view of Naito et al. (US 6,606,237).
Regarding claim 24, Bultitude teaches (FIG. 3):
A multilayer decoupling capacitor structure comprising:
a plurality of interposers (10); and
a plurality of decoupling capacitors ([0066]), each decoupling capacitor of the plurality of decoupling capacitors having a first surface and an opposing second surface, and
wherein the at least two layers are stacked adjacent to one another such that one interposer of the plurality of interposers is common to the at least two layers (FIG. 3).
Bultitude fails to expressly disclose the internal capacitor structure:
wherein each decoupling capacitor contains alternating dielectric layers and internal electrode layers, the internal electrode layers containing first internal electrode layers and second internal electrode layers, wherein each decoupling capacitor further contains a first external terminal that is electrically connected to the first internal electrode layers and disposed on a first surface of the decoupling capacitor, a second external terminal that is electrically connected to the first internal electrode layers and disposed on the second surface of the decoupling capacitor, a third external terminal that is electrically connected to the second internal electrode layers and disposed on the first surface of the decoupling capacitor, and a fourth external terminal that is electrically connected to the second internal electrode layers and disposed on the second surface of the decoupling capacitor, wherein the plurality of interposers and the plurality of decoupling capacitors are arranged in at least two layers, each layer comprising at least one decoupling capacitor of the plurality of decoupling capacitors disposed between two interposers of the plurality of interposers,
However, Naito teaches embedded capacitor structures having internal electrodes and external electrodes, embedded in a substrate with interposer layers over the top and bottom.
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to include the capacitor structures of Naito as the embedded and stacked capacitor devices of Bultitude for the predictable advantage of using conventional capacitor devices in the stacked structure.
Regarding claim 25, Bultitude teaches (FIG. 3):
The multilayer decoupling capacitor structure of claim 24, wherein the at least two layers includes a first layer and a second layer, wherein the first layer includes a first interposer of the plurality of interposers, a second interposer of the plurality of interposers, and a first set of the plurality of decoupling capacitors disposed between the first interposer and the second interposer, and wherein the second layer includes the second interposer, a third interposer of the plurality of interposers, and a second set of the plurality of decoupling capacitors disposed between the second interposer and the third interposer.
Regarding claim 26, Bultitude teaches (FIG. 3):
The multilayer decoupling capacitor structure of claim 25, wherein the first layer and the second layer are stacked adjacent to one another along a stacking direction, and wherein each decoupling capacitor of the first set of the plurality of decoupling capacitors is aligned along the stacking direction with a respective one decoupling capacitor of the second set of the plurality of decoupling capacitors.
Regarding claim 27, Bultitude teaches (FIG. 14):
The multilayer decoupling capacitor structure of claim 25, wherein the first layer and the second layer are stacked adjacent to one another along a stacking direction, and wherein each decoupling capacitor of the first set of the plurality of decoupling capacitors is offset along a longitudinal direction from a respective one decoupling capacitor of the second set of the plurality of decoupling capacitors, the longitudinal direction perpendicular to the stacking direction.
Regarding claim 28, Bultitude teaches (FIG. 3):
The multilayer decoupling capacitor structure of claim 24, wherein at least one interposer of the plurality of interposers comprises at least one via extending from a first surface of the at least one interposer to a second surface of the at least one interposer, the at least one via filled with a conductive material (12).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to CORY W ESKRIDGE whose telephone number is (571)272-0543. The examiner can normally be reached M - F 9 - 5.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Julio Madonado can be reached at 571-272-1864. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/CORY W ESKRIDGE/Primary Examiner, Art Unit 2898
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