DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDSs) submitted on 11/20/2024, 3/14/2025, 3/25/2025, and 9/16/2025 are in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statements are being considered by the examiner.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
The title of the invention has been suggested as, “MULTILAYER STRUCTURES COMPRISING ELECTRONIC COMPONENT LAYERS AND INTERPOSERS ALTERNATELY STACKED ON EACH OTHER, AND ASSEMBLIES COMPRISING MULTILAYER STRUCTURES”.
Drawings
The drawings are objected to because
In paragraph [00133], semiconductor structure 610 is mentioned when referring Fig. 1. Fig. 1 does not have a semiconductor structure labeled as 610. The Examiner believes that one of the semiconductor structures 630 in Fig. 1 should be semiconductor structure 610, but labeled wrongly as 630.
Fig. 13A has misplaced labels 914 and 916 hanging on the top left corner of the figure. These labels should be either removed or placed at their correct locations.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-4, 6-15, 17, and 19 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Bultitude (US 2019/0080982 A1).
Regarding claim 1, Bultitude teaches a multilayer structure (high density multicomponent
package 30, Fig. 3, [0050]) comprising:
a plurality of interposers (interposers 10, Fig. 3, [0050]);
a plurality of electronic components (electronic component 1, electronic component 2, electronic component 3, and electronic component 4, Fig. 3, [0050]: “In FIG. 3, four electronic components are illustrated for the purposes of discussion without limit thereto.” and “While four electronic components are a sufficient number to illustrate the invention it is to be understood that the invention can be extended from two components to any number of electronic components and a large variety of variations as will be realized. It is preferable that the number of components is at least two to no more than 100.”) disposed between the plurality of interposers (interposers 10, Fig. 3);
a first external terminal (interconnect 34 at the top, labeled as first external terminal in Illustrative Fig. 1, which is an annotated version of Fig. 3, [0050]) disposed on a first external surface (first external surface, Illustrative Fig. 1); and
a second external terminal (interconnect 34 on the bottom, labeled as second external terminal in Illustrative Fig. 1) disposed on a second external surface (second external surface, Illustrative Fig. 1), the second external surface opposite the first external surface,
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wherein the plurality of interposers (interposers 10, Illustrative Fig. 1) and the plurality of electronic components (electronic component 1, electronic component 2, electronic component 3, and electronic component 4, Illustrative Fig. 1) are arranged in at least two layers (see first layer and second layer in Illustrative Fig. 1), each layer comprising at least one electronic component (first layer includes electronic component 3 and second layer includes electronic component 2, Illustrative Fig. 1) of the plurality of electronic components (electronic component 1, electronic component 2, electronic component 3, and electronic component 4, Illustrative Fig. 1) disposed between two interposers (electronic component 3 is between the first and second interposers and electronic component 2 is between the second and third interposers as shown in Illustrative Fig. 1) of the plurality of interposers (interposers 10, Illustrative Fig. 1),
wherein the at least two layers (first layer and second layer, Illustrative Fig. 1) are stacked adjacent to one another (the layers are directly on top of each other, Illustrative Fig. 1) such that one interposer of the plurality of interposers (second interposer, Illustrative Fig. 1) is common to adjacent layers of the at least two layers (first layer and second layer, Illustrative Fig. 1), and
wherein the first external terminal (first external terminal, Illustrative Fig. 1) is electrically connected to a first electronic component (electronic component 3, Illustrative Fig. 1) of the plurality of electronic components (electronic component 1, electronic component 2, electronic component 3, and electronic component 4, Illustrative Fig. 1) and the second external terminal (electronic component 3, Illustrative Fig. 1) is electrically connected to a second electronic component (electronic component 2, Illustrative Fig. 1) of the plurality of electronic components (electronic component 1, electronic component 2, electronic component 3, and electronic component 4, Illustrative Fig. 1).
Regarding claim 2, Bultitude teaches the multilayer structure of claim 1, wherein the plurality of electronic components (electronic component 1, electronic component 2, electronic component 3, and electronic component 4, Illustrative Fig. 1) includes at least one of a capacitor ([0066]: “Each electronic component is preferably independently selected from the group consisting of capacitor, resistor, varistor, inductor, diode, fuse, overvoltage discharge device, sensor, switch, electrostatic discharge suppressor, semiconductor and integrated circuit. It is preferred that the capacitor is an MLCC and more preferably at least one of the electronic components is an MLCC.”), a resistor, an inductor, a fuse, a transistor, a diode, a transformer, a sensor, an electrostatic discharge device, a memory device, a radio frequency device, a low noise amplifier, a power amplifier, a power management device, an antenna, a microelectromechanical system, or a parasitic element.
Regarding claim 3, Bultitude teaches the multilayer structure of claim 1, wherein the at least two layers (first layer and second layer, Illustrative Fig. 1) includes a first layer (first layer, Illustrative Fig. 1) and a second layer (second layer, Illustrative Fig. 1), wherein the first layer (first layer, Illustrative Fig. 1) includes a first interposer (first interposer, Illustrative Fig. 1) of the plurality of interposers (interposers 10, Illustrative Fig. 1), a second interposer (second interposer, Illustrative Fig. 1) of the plurality of interposers (interposers 10, Illustrative Fig. 1), and a first set of the plurality of electronic components (electronic component 3, Illustrative Fig. 1) disposed between the first interposer (first interposer, Illustrative Fig. 1) and the second interposer (second interposer, Illustrative Fig. 1), and wherein the second layer (second layer, Illustrative Fig. 1) includes the second interposer (second interposer, Illustrative Fig. 1), a third interposer (third interposer, Illustrative Fig. 1) of the plurality of interposers (interposers 10, Illustrative Fig. 1), and a second set of the plurality of electronic components (electronic component 2, Illustrative Fig. 1) disposed between the second interposer (second interposer, Illustrative Fig. 1) and the third interposer (third interposer, Illustrative Fig. 1).
Regarding claim 4, Bultitude teaches the multilayer structure of claim 3, wherein the first layer (first layer, Illustrative Fig. 1) and the second layer (second layer, Illustrative Fig. 1) are stacked adjacent to one another along a stacking direction (vertical direction, Illustrative Fig. 1), and wherein each electronic component (electronic component 3, Illustrative Fig. 1) of the first set of the plurality of electronic components (electronic component 3, Illustrative Fig. 1) is aligned along the stacking direction (vertical direction, Illustrative Fig. 1 ) with a respective one electronic component (electronic component 2, Illustrative Fig. 1) of the second set of the plurality of electronic components (electronic component 2, Illustrative Fig. ).
Regarding claim 6, Bultitude teaches the multilayer structure of claim 3, wherein the first set of the plurality of electronic components (electronic component 3, Illustrative Fig. 1) includes the first electronic component (electronic component 3, Illustrative Fig. 1).
Regarding claim 7, Bultitude teaches the multilayer structure of claim 3, wherein the second set of the plurality of electronic components (electronic component 2, Illustrative Fig. 1) includes the second electronic component (electronic component 2, Illustrative Fig. 1).
Regarding claim 8, Bultitude teaches the multilayer structure of claim 1, wherein the plurality of interposers (interposers 10, Illustrative Fig. 1) includes a first interposer (first interposer, Illustrative Fig. 1) and a second interposer (second interposer, Illustrative Fig. 1), and wherein the first interposer (first interposer, Illustrative Fig. 1) defines the first external surface (first external surface, Illustrative Fig. 1: first external surface is the top surface of the first interposer) and the second interposer (second interposer, Illustrative Fig. 1) defines the second external surface (second external surface, Illustrative Fig. 1: second external surface is the bottom surface of the second interposer).
Regarding claim 9, Bultitude teaches the multilayer structure of claim 8, wherein the at least two layers (first layer and second layer, Illustrative Fig. 1) includes a first layer (first layer, Illustrative Fig. 1) and a second layer (second layer, Illustrative Fig. 1), and wherein the first layer (first layer, Illustrative Fig. 1) includes the first interposer (first interposer, Illustrative Fig. 1) and the second layer (second layer, Illustrative Fig. 1) includes the second interposer (second interposer, Illustrative Fig. 1).
Regarding claim 10, Bultitude teaches the multilayer structure of claim 1, wherein the plurality of interposers (interposers 10, Illustrative Fig. 1) includes a first interposer (first interposer, Illustrative Fig. 1), and wherein the first interposer (first interposer, Illustrative Fig. 1) defines the first external surface (first external surface, Illustrative Fig. 1: first external surface is the top surface of the first interposer) and the second electronic component (electronic component 3, Illustrative Fig. 1) defines the second external surface (third external surface, Illustrative Fig. 1: while second external surface is the second external surface of Illustrative Fig. 1 in claim 8, second external surface is the third external surface of Illustrative Fig. 1 in claim 10. This does not cause a conflict as claim 1 defines the second external surface broadly).
Regarding claim 11, Bultitude teaches the multilayer structure of claim 1, further comprising one or more additional first external terminals (see additional first external terminal in Illustrative Fig. 1) disposed along the first external surface (first external surface, Illustrative Fig. 1), wherein each additional first external terminal (additional first external terminal, Illustrative Fig. 1) is electrically connected to a respective one electronic component (electronic component 3, Illustrative Fig. 1) of the plurality of electronic components (electronic component 1, electronic component 2, electronic component 3, and electronic component 4, Illustrative Fig. 1).
Regarding claim 12, Bultitude teaches the multilayer structure of claim 1, further comprising one or more additional second external terminals (see additional second external terminal in Illustrative Fig. 1) disposed along the second external surface (second external surface, Illustrative Fig. 1), wherein each additional second external terminal (additional second external terminal, Illustrative Fig. 1) is electrically connected to a respective one electronic component (electronic component 2, Illustrative Fig. 1) of the plurality of electronic components (electronic component 1, electronic component 2, electronic component 3, and electronic component 4, Illustrative Fig. 1).
Regarding claim 13, Bultitude teaches the multilayer structure of claim 1, further comprising one or more additional first external terminals (see additional first external terminal in Illustrative Fig. 1) disposed along the first external surface (first external surface, Illustrative Fig. 1) and one or more additional second external terminals (see additional second external terminal in Illustrative Fig. 1) disposed along the second external surface (second external surface, Illustrative Fig. 1), wherein each additional first external terminal (additional first external terminal, Illustrative Fig. 1) and each additional second external terminal (additional first external terminal, Illustrative Fig. 1) is electrically connected to a respective one electronic component (electronic component 4 and electronic component 1, respectively; Illustrative Fig. 1) of the plurality of electronic components (electronic component 1, electronic component 2, electronic component 3, and electronic component 4, Illustrative Fig. 1).
Regarding claim 14, Bultitude teaches the multilayer structure of claim 1, wherein at least one interposer (first interposer, Illustrative Fig. 1) of the plurality of interposers (interposers 10, Illustrative Fig. 1) comprises at least one via (via 14’ (see Fig. 1A), labeled as first via in Illustrative Fig. 1, [0049]) extending from a first surface (bottom surface of first interposer, Illustrative Fig. 1) of the at least one interposer (first interposer, Illustrative Fig. 1) to a second surface (top surface of first interposer, Illustrative Fig. 1) of the at least one interposer (first interposer, Illustrative Fig. 1), the at least one via (first via, Illustrative Fig. 1) filled with a conductive material ([0047]: “The via may be filled … with electrically conductive material”), and wherein the at least one via (via Illustrative Fig. 1) contacts a terminal (external termination 326, Illustrative Fig. 1, [0050]) of a respective one electronic component (electronic component 3, Illustrative Fig. 1) of the plurality of electronic components (electronic component 1, electronic component 2, electronic component 3, and electronic component 4, Illustrative Fig. 1) to electrically connect the terminal of the respective one electronic component (external termination 326, Illustrative Fig. 1) with the at least one interposer (first interposer, Illustrative Fig. 1).
Regarding claim 15, Bultitude teaches the multilayer structure of claim 1, wherein at least one interposer (first interposer, Illustrative Fig. 1) of the plurality of interposers (interposers 10, Illustrative Fig. 1) comprises a first via (via 14’ (see Fig. 1A), labeled as first via in Illustrative Fig. 1, [0049]) and a second via (via 14’ (see Fig. 1A), labeled as second via in Illustrative Fig. 1, [0049]), wherein the first via (first via, Illustrative Fig. 1) contacts the first external terminal (first external terminal, Illustrative Fig. 1) and the first electronic component (electronic component 3, Illustrative Fig. 1) to electrically connect the first external terminal (first external terminal, Illustrative Fig. 1) with the first electronic component (electronic component 3, Illustrative Fig. 1), and wherein the second via (second via, Illustrative Fig. 1) contacts the second external terminal (second external terminal, Illustrative Fig. 1) and the second electronic component (electronic component 2, Illustrative Fig. 1) to electrically connect the second external terminal (second external terminal, Illustrative Fig. 1) with the second electronic component (electronic component 2, Illustrative Fig. 1).
Regarding claim 17, Bultitude teaches the multilayer structure of claim 1, wherein the plurality of electronic components (electronic component 1, electronic component 2, electronic component 3, and electronic component 4, Illustrative Fig. 1) includes at least one capacitor (electronic component 3, [0059]: “electronic component 2 is an inductor and electronic components 1 and 3 are MLCC's.”, where MLCC stands for multi-layer ceramic capacitors ([0004]). A person of ordinary skill in the art aiming to form a Pi filter would arrange the electronic components as in [0059]) electrically connected to at least one inductor (electronic component 2, Illustrative Fig. 1, [0054]: electrical component 2 is an inductor) to form a filter (see the Fig. 8 which is a Pi filter ([0059])), and wherein the at least one capacitor (electronic component 3, Illustrative Fig. 1) and the at least one inductor (electrical component 2, Illustrative Fig. 1) are disposed in different layers (first layer and second layer, Illustrative Fig. 1) of the at least two layers (first layer and second later, Illustrative Fig. 1), the different layers (first layer and second later, Illustrative Fig. 1) stacked together along a stacking direction (vertical direction, Illustrative Fig. 1).
Regarding claim 19, Bultitude teaches a microelectronic assembly (Fig. 4, [0051]) comprising:
a semiconductor structure (while not shown in Fig. 4, [0051]: “A connector, 44, is in electrical contact with external termination 328 and active trace 382 wherein the active traces, 38, are integral to the electronic circuit of a device.”, and a person of ordinary skill in the art before the effective filing date of the claimed invention would understand that a device includes a semiconductor structure);
an assembly interposer (high density multicomponent package 30, Fig. 4, [0051]) electrically connected to the semiconductor structure (Fig. 4, [0051]: “A connector, 44, is in electrical contact with external termination 328 and active trace 382 wherein the active traces, 38, are integral to the electronic circuit of a device.”);
a package substrate (substrate 36, Fig. 4, [0051]) electrically connected to the assembly interposer (high density multicomponent package 30, Fig. 4);
a multilayer structure (high density multicomponent package 30 has a multilayer structure, see Illustrative Fig. 2, which is an annotated version of Fig. 4) comprising:
a plurality of interposers (interposers 10 (see Fig. 3 for the labels of interposers), also indicated as first interposer, second interposer, and third interposer in Illustrative Fig. 2); and
a plurality of electronic components (electronic component 2 and electronic component 3, Illustrative Fig. 2 (see also Fig. 3 for the labels of electronic components), [0040]) disposed between the plurality of interposers (interposers 10, Illustrative Fig. 2),
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wherein the plurality of interposers (interposers 10, Illustrative Fig. 2) and the plurality of electronic components (electronic component 2 and electronic component 3, Illustrative Fig. 2) are arranged in at least two layers (first layer and second layer in Illustrative Fig. 2), each layer (first layer and second layer, Illustrative Fig. 2) comprising at least one electronic component (electronic component 2 or electronic component 3, Illustrative Fig. 2) of the plurality of electronic components (electronic component 2 and electronic component 3, Illustrative Fig. 2) disposed between two interposers (electronic component 2 between the second and electronic component 3, Illustrative Fig. 2) of the plurality of interposers, and
wherein the at least two layers (first layer and second layer, Illustrative Fig. 1) are stacked adjacent to one another (on top of each other, Illustrative Fig. 2) such that one interposer (second interposer, Illustrative Fig. 2) of the plurality of interposers (first, second and third interposers, Illustrative Fig. 2) is common to adjacent layers (first layer and second later, Illustrative Fig. 2) of the at least two layers (first layer and second later, Illustrative Fig. 2); and
a circuit board ([0051]: substrate 36 includes active circuit traces 38, and therefore the substrate acts also as a circuit board),
wherein the multilayer structure (high density multicomponent package 30, Illustrative Fig. 2) is electrically connected to the package substrate (substrate 36, Illustrative Fig. 2) and the circuit board (substrate 36 with active traces 38, Illustrative Fig. 2).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim 5 is rejected under 35 U.S.C. 103 as being unpatentable over Bultitude (US 2019/0080982 A1) as applied to claims 1-4, 6-15, 17, and 19 above, and further in view of Semmelmeyer (US 2013/0187292 A1).
Regarding claim 5, Bultitude teaches the multilayer structure of claim 3, wherein the first layer (first layer, Illustrative Fig. 1) and the second layer (second layer, Illustrative Fig. 1) are stacked adjacent to one another along a stacking direction (vertical direction, Illustrative Fig. 1).
Bultitude, however, does not teach that
each electronic component of the first set of the plurality of electronic components is offset along a longitudinal direction from a respective one electronic component of the second set of the plurality of electronic components, the longitudinal direction perpendicular to the stacking direction.
Semmelmeyer, on the other hand, teaches a multilayer structure (three-dimensional integrated circuit (3DIC) 70, Fig. 4, [0035]) comprising a first set of the plurality of electronic components (first level dies 56, 58, 60, Figs. 3-4, [0033]) in a first layer, a second set of the plurality of electronic components (second level dies 52, 54, Figs. 3-4, [0033]) in a second layer stacked along a stacking direction (vertical direction, Figs. 3-4) on the first layer, and an interposer (interposer 62, Figs. 3-4, [0033]) between the layers, wherein
each electronic component (first level dies 56, 58, 60, Figs. 3-4,) of the first set of the plurality of electronic components (first level dies 56, 58, 60, Figs. 3-4,) is offset along a longitudinal direction (left-right direction in Fig. 3) from a respective (the ones that connect to each other) one electronic component (second level dies 52, 54, Figs. 3-4) of the second set of the plurality of electronic components (second level dies 52, 54, Figs. 3-4) , the longitudinal direction (left-right direction in Fig. 3) perpendicular to the stacking direction (vertical direction in Fig. 3).
A person of ordinary skill in the art before the effective filing date of the claimed invention would already know that electronic components can have different widths, as also evidenced by McConnell (US 20140002952 A1, Fig. 10, [0087]: two capacitors MLCCs have different widths), and including an offset between the electronic components in adjacent layer would minimize the wiring lengths (see Fig. 3 of Semmemeyer). Therefore, a person of ordinary skill in the art who uses electronic components with different widths would be motivated to include an offset along longitudinal direction between respective electronic components in different layers to optimize wiring in the multilayer structure.
Claim 16 is rejected under 35 U.S.C. 103 as being unpatentable over Bultitude (US 2019/0080982 A1) as applied to claims 1-4, 6-15, 17, and 19 above, and further in view of Ritter (US 2007/0096254 A1).
Regarding claim 16, Bultitude teaches the multilayer structure of claim 1, wherein the plurality of electronic components (electronic component 1, electronic component 2, electronic component 3, and electronic component 4, Illustrative Fig. 1) includes at least one decoupling capacitor (electronic component 3, Illustrative Fig. 1, [0059]: “electronic component 2 is an inductor and electronic components 1 and 3 are MLCC's.”, where MLCC stands for multi-layer ceramic capacitors ([0004] and capacitors in a Pi filter are decoupling capacitors). A person of ordinary skill in the art aiming to form a Pi filter would arrange the electronic components as in [0059]), the decoupling capacitor (electronic component 3, Illustrative Fig. 1) having a first surface (top surface of electronic component 3, Illustrative Fig. 1) and an opposing second surface (bottom surface of electronic component 3, Illustrative Fig. 1).
Bultitude, however, does not disclose the internal structure of the electronic component 3, and therefore does not teach that
the decoupling capacitor contains alternating dielectric layers and internal electrode layers, the internal electrode layers containing first internal electrode layers and second internal electrode layers, wherein the decoupling capacitor further contains a first external terminal that is electrically connected to the first internal electrode layers and disposed on a first surface of the decoupling capacitor, a second external terminal that is electrically connected to the first internal electrode layers and disposed on the second surface of the decoupling capacitor, a third external terminal that is electrically connected to the second internal electrode layers and disposed on the first surface of the decoupling capacitor, and a fourth external terminal that is electrically connected to the second internal electrode layers and disposed on the second surface of the decoupling capacitor.
Ritter, on the other hand teaches
a decoupling capacitor (capacitor embodiment 42, Fig. 4, [0091]) that contains alternating dielectric layers (plurality of dielectric layers 16, Fig. 4, [0091]) and internal electrode layers (plurality of first electrodes 12 and second electrodes 14, Fig. 4, [0091]), the internal electrode layers (plurality of first electrodes 12 and second electrodes 14, Fig. 4) containing first internal electrode layers (first electrodes 12, Fig. 4) and second internal electrode layers (second electrodes 14, Fig. 4), wherein the decoupling capacitor (capacitor embodiment 42, Fig. 4) further contains a first external terminal (termination 18’ on the top left, see first external terminal in Illustrative Fig. 3 which is an annotated version of Ritter’s Fig. 4, [0091]) that is electrically connected to the first internal electrode layers (first electrodes 12, Illustrative Fig. 3, [0091]: “Terminations 18' are then formed along the device periphery such that one termination electrically connects each first electrode 12 and conductive via 44a and one termination electrically connects each second electrode 14 and conductive via 44b.”) and disposed on a first surface (top surface, Illustrative Fig. 3) of the decoupling capacitor (capacitor embodiment 42, Illustrative Fig. 3), a second external
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terminal (second external terminal as shown in Illustrative Fig. 3) that is electrically connected to the first internal electrode layers (first electrodes 12, Illustrative Fig. 3) and disposed on the second surface (bottom surface, Illustrative Fig. 3) of the decoupling capacitor (capacitor embodiment 42, Illustrative Fig. 3), a third external terminal (third external terminal as shown in Illustrative Fig. 3) that is electrically connected to the second internal electrode layers (second electrodes 14, Illustrative Fig. 3) and disposed on the first surface (top surface, Illustrative Fig. 3) of the decoupling capacitor (capacitor embodiment 42, Illustrative Fig. 3), and a fourth external terminal (third external terminal as shown in Illustrative Fig. 3) that is electrically connected to the second internal electrode layers (second electrodes 14, Illustrative Fig. 3) and disposed on the second surface (bottom surface, Illustrative Fig. 3) of the decoupling capacitor (capacitor embodiment 42, Illustrative Fig. 3).
Ritter further teaches that improved component design for decoupling capacitors taught by Ritter results in devices characterized by relatively low cost, low inductance and low Equivalent Series Resistance (ESR) ([0002]), which is also beneficial for the multilayer structure of Bultitude (see [0065] of Bultitude). A person of ordinary skill in the art before the effective filing date of the claimed invention would already realize that the shape of the decoupling capacitor of Ritter is similar to the electronic components in the multilayer structure of Bultitude in that the location of the first, second, third ,and fourth external terminals are similarly located on the top and bottom surfaces of the electronic component in a similar arrangement. Therefore, a person of ordinary skill in the art before the effective filing date of the claimed invention would be motivated to use decoupling capacitors taught by Ritter in the multilayer structure of Bultitude to improve the cost, inductance and ESR of the device. Thus, the combination of Bultitude and Ritter meets all the limitations of claim 16.
Claim 18 is rejected under 35 U.S.C. 103 as being unpatentable over Bultitude (US 2019/0080982 A1) as applied to claims 1-4, 6-15, 17, and 19 above, and further in view of another embodiment of Bultitude (US 2013/0187292 A1, Figs. 10-11).
Regarding claim 18, Bultitude teaches the multilayer structure of claim 1, wherein the plurality of electronic components (electronic component 1, electronic component 2, electronic component 3, and electronic component 4, Fig. 3) includes at least one capacitor (electronic component 3, [0059]: “electronic component 2 is an inductor and electronic components 1 and 3 are MLCC's.”, where MLCC stands for multi-layer ceramic capacitors ([0004]) electrically connected to at least one inductor (electronic component 2, Illustrative Fig. 1, [0054]: electrical component 2 is an inductor) to form a filter (see the Fig. 8 which is a Pi filter ([0059])).
Bultitude, however, does not teach that the at least one capacitor and the at least one inductor are disposed in the same layer of the at least two layers.
Another embodiment of Bultitude (Figs. 10-11), on the other hand, teaches a multilayer structure (Fig. 10-11) wherein a secondary electrical component 5 (Figs. 10-11) electrically mounted in parallel with electrical components 2 and 3 at the external termination (Figs. 10-11) provides a combination of serial and parallel electrical connections without component 5 increasing the surface area of the circuit board. Another embodiment of Bultitude does not limit the type of electrical components 1-5(see Figs. 10-12) and provides the flexibility to select each component from a group consisting of capacitor, resistor, varistor, inductor, diode, fuse, overvoltage discharge device, sensor, switch, electrostatic discharge suppressor, semiconductor and integrated circuit ([0066]).
Therefore, a person of ordinary skill in the art before the effective filing date of the claimed invention who is aiming to form a filter that is in the form of resistor and inductor of Fig. 13 is switched would be motivated to choose electrical component 5 as an inductor such that
the at least one capacitor (electrical component 2, Fig. 10) and the at least one inductor (electrical component 5, Fig. 10) are disposed in the same layer of the at least two layers.
Claim 20 is rejected under 35 U.S.C. 103 as being unpatentable over Kim (US 2018/0240729 A1).
Regarding claim 20, Kim teaches a method (Figs. 1-8 and 20A, [0140]-[0141]) of forming a reduced component structure (semiconductor package, Fig. 21A, [0045]), the method comprising:
disposing a plurality of components (die 200, Figs. 1-2 and 14, [0061]: while the embodiment in Fig. 2 shows only one component, a person of ordinary skill in the art before the effective filing date of the claimed invention would understand that the method is also applicable to a package with two or more components as shown in Fig. 14) adjacent a first sacrificial plate (base substrate 100, Figs. 1-2, [0053]);
applying a resin (resin 130, Fig. 3, [0069]) around the plurality of components (die 200, Figs. 3 and 14);
disposing a second sacrificial plate (redistribution layer 150, Figs. 7 and 14, [0075]) adjacent the plurality of components (die 200, Figs. 7 and 14), the second sacrificial plate (redistribution layer 150, Figs. 7 and 14, [0075]) opposite the first sacrificial plate (base substrate 100, Figs. 7 and 14) along a Z-direction (vertical direction, Figs. 7 and 14) such that the plurality of components (die 200, Figs. 7 and 14) are sandwiched between the first sacrificial plate (base substrate 100, Figs. 7 and 14) and the second sacrificial plate (redistribution layer 150, Figs. 7 and 14);
forming one or more vias (first and second connecting plugs, Figs. 7 and 14, [0054]: while Kim does not explicitly state forming the vias (plugs), a person or ordinary skill in the art before the effective filing date of the claimed invention would understand that the plugs (vias) are formed during manufacturing of the base substrate 100) through at least one of the first sacrificial plate (base substrate 100, Figs. 7 and 14) or the second sacrificial plate;
filling the one or more vias (first and second connecting plugs, Figs. 7 and 14) with a conductive material ([0056]: “the first connecting plug 114, and the second connecting plug 116 may be formed of copper (Cu), aluminum (Al), gold (Au), or the like.”); and
removing at least a portion ([0142]: “A portion depicted by the dotted line of FIG. 20A may be removed from the semiconductor package structure fabricated according to the first exemplary embodiment.”) of at least one of the first sacrificial plate (base substrate 100, Fig. 20A) or the second sacrificial plate along the Z-direction (vertical direction, Fig. 20A).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Kawai (US 2018/0084639 A1) teaches a three-dimensional circuit structure, which is relevant to all claims.
Cain (US 2020/0303127 A1) teaches package structure with a capacitor, which is relevant to claim 19.
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/ILKER NMN OZDEN/Examiner, Art Unit 2812
/William B Partridge/Supervisory Patent Examiner, Art Unit 2812
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