DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 10, and 16-20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding claim 10, the claim recites the limitation “a peripheral transistor on/in the substrate” which is indefinite because it is not clear what structural relationship between the peripheral transistor and the substrate is being claimed.
Regarding claim 16, the claim recites the limitation “a peripheral transistor on or in the substrate” which is indefinite because it is not clear what structural relationship between the peripheral transistor and the substrate is being claimed.
Claims 17-20 depend on claim 16 and arerejected on at least the same basis.
Appropriate correction is required.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 11, 13, and 15 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Choi et al. (US 20190198426 A1) herein after “Choi”.
Regarding claim 11, Figs. 1 and 13 of Choi disclose a semiconductor device (Fig. 1, semiconductor device 100, ¶ [0017]) comprising:
a substrate (Fig. 1, silicon substrate 110, ¶ [0017]);
a first interlayer insulating layer (Fig. 1, lower interlayer insulating film 120, ¶ [0018]) on the substrate (110);
a second interlayer insulating layer (Fig. 13, second insulating layer 143, ¶ [0044]) on the first interlayer insulating layer (120), wherein the second interlayer insulating layer (143) is in direct contact with the first interlayer insulating layer (120);
a first contact (Fig. 1, contact 122, ¶ [0018]) in the first interlayer insulating layer (120);
a through via (Fig. 1, via electrode 134, ¶ [0024]) in the first interlayer insulating layer (120) and the substrate (110);
a first wiring (Fig. 1, metal layer 153 connected to contact 122, ¶ [0026]) in the second interlayer insulating layer (143), wherein the first wiring (153 connected to 122) is in contact with the first contact (122);
a second wiring (Fig. 1, metal layer 153 connected to via electrode 134, ¶ [0026]) in the second interlayer insulating layer (143), wherein the second wiring (153 connected to 134) is in contact with the through via (134);
a polishing stop pattern (Fig. 13, etch stop layer 141, ¶ [0022]) that is in contact with a side surface of the second wiring (153 connected to 134);
and a capping pattern (Fig. 13, first insulating layer 142, ¶ [0044]) on the polishing stop pattern (141), wherein the capping pattern (142) is in contact with the side surface of the second wiring (153 connected to 134), wherein an upper surface of the first interlayer insulating layer (120) includes a protrusion (see Annotation 1, Fig. 13 of Choi, PRO) that extends away from an upper surface of the substrate (110) and is in contact with a lower surface of the polishing stop pattern (141),
wherein the capping pattern (142) and the polishing stop pattern (141) are spaced apart from the first wiring (153 connected to 122),
wherein the first interlayer insulating layer (120) includes a first material that has a first density (“The lower interlayer insulating film 120 may include… silicon nitride (SiN)”, ¶ [0019]),
wherein the second interlayer insulating layer (143) includes a second material that has a second density (“The second insulating layer 143 may be a silicon carbon nitride (SiCN) film”, ¶ [0049]), and
wherein the first density is greater than the second density (Silicon nitride is known to have a greater density than silicon carbon nitride).
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Annotation 1, Fig. 13 of Choi
Regarding claim 13, Figs. 1 and 13 of Choi disclose the semiconductor device of claim 11 as applied above, and Fig. 13 of Choi further discloses wherein a side surface of the capping pattern (142) is aligned with a side surface of the polishing stop pattern (141).
Regarding claim 15, Figs. 1 and 13 of Choi disclose the semiconductor device of claim 11 as applied above, and Fig. 13 of Choi further discloses wherein the capping pattern (142) and the polishing stop pattern (141) include a same material (“The etch stop layer 141 may be an insulating layer made of…, a silicon oxynitride (SiON) film”, “The first insulating layer 142 may be formed by depositing…, a silicon oxynitride (SiON) film”, ¶ [0042] and [0045]).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 2, and 4 are rejected under 35 U.S.C. 103 as being unpatentable over Choi (US 20190198426 A1).
Regarding claim 1, Figs. 1 and 13 of Choi disclose a semiconductor device comprising:
a substrate (110);
a first interlayer insulating layer (120) on the substrate (110), wherein an upper surface of the first interlayer insulating layer (120) is at a first distance from an upper surface of the substrate (110);
a second interlayer insulating layer (143) on the first interlayer insulating layer (120), wherein the second interlayer insulating layer (143) is in direct contact with the first interlayer insulating layer (120);
a first contact (122) in the first interlayer insulating layer (120), wherein an upper surface of the first contact (122) is at a second distance from the upper surface of the substrate (110),
a through via (134) in the first interlayer insulating layer (120) and the substrate (110), wherein an upper surface of the through via (134) is at a third distance from the upper surface of the substrate (110),
a first wiring (153 connected to 122) in the second interlayer insulating layer (143), wherein the first wiring (153 connected to 122) is in contact with the first contact (122), a lower surface of the first wiring (153 connected to 122) is at a fourth distance, and the fourth distance is closer than the first distance to the upper surface of the substrate (110); and
a second wiring (153 connected to 134) in the second interlayer insulating layer (143), wherein the second wiring (153 connected to 134) is in contact with the through via (134), a lower surface of the second wiring (153 connected to 134) is at a fifth distance,
wherein the first interlayer insulating layer (120) includes a first material that has a first density (“The lower interlayer insulating film 120 may include… silicon nitride (SiN)”, ¶ [0019]),
wherein the second interlayer insulating layer (143) includes a second material that has a second density (“The second insulating layer 143 may be a silicon carbon nitride (SiCN) film”, ¶ [0049]), and
wherein the first density is greater than the second density (Silicon nitride is known to have a greater density than silicon carbon nitride).
Choi fails to disclose the second distance is farther than the first distance from the upper surface of the substrate;
the third distance is farther than the second distance from the upper surface of the substrate; and
the fifth distance is closer than the fourth distance to the upper surface of the substrate.
However, it has been held that where the only different between the prior art and the claims was a recitation of relative dimensions of the claimed element, and a device having the claimed relative dimensions would not perform differently than the prior art device, the claimed device was not patentably distinct from the prior art device (MPEP 2144.04).
It would have been obvious to one of ordinary skill in the art before the time of the effective filling date of the invention that a mere change in the height of the contact, via and wiring structure was within the level of ordinary skill in the art and/or because changes in size and shape are prima facie obvious absent persuasive evidence that the particular configuration is significant (MPEP 2144.04(IV)).
Regarding claim 2, Figs. 1 and 13 of Choi disclose the semiconductor device of claim 1 as applied above, and Fig. 1 of Choi further discloses wherein the first wiring (153 connected to 122) has a first width in a first direction that is parallel with the upper surface of the substrate (110),
wherein the second wiring (153 connected to 134) has a second width in the first direction, and
wherein the second width is greater than the first width (shown in Fig. 1).
Regarding claim 4, Figs. 1 and 13 of Choi disclose the semiconductor device of claim 1 as applied above, and Fig. 1 of Choi further discloses wherein the first interlayer insulating layer (120) is free of carbon (“The lower interlayer insulating film 120 may include silicon oxide (SiO2) and/or silicon nitride (SiN)”, ¶ [0019]), and
wherein the second interlayer insulating layer (143) includes carbon (“The second insulating layer 143 may be a silicon carbon nitride (SiCN) film”, ¶ [0049]).
Claim 3 is rejected under 35 U.S.C. 103 as being unpatentable over Choi (US 20190198426 A1) in view of Muranaka (US 20110254165 A1).
Regarding claim 3, Figs. 1 and 13 of Choi disclose the semiconductor device of claim 2 as applied above, but Choi fails to disclose a third wiring in the second interlayer insulating layer,
wherein the third wiring is spaced apart from the first wiring and the second wiring,
wherein the third wiring has the first width in the first direction,
wherein a lower surface of the third wiring is at a sixth distance, and the sixth distance is at a same distance as the fourth distance from the upper surface of the substrate or is closer than the fourth distance to the upper surface of the substrate, and
wherein the sixth distance is farther than the fifth distance from the upper surface of the substrate.
In the similar field of semiconductor interconnect structures, Fig. 35 of Muranaka discloses a third wiring (see Annotation 2, Fig. 35 of Muranaka, W3) in the second interlayer insulating layer (Fig. 35, interlayer insulation film 32a, ¶ [0109]),
wherein the third wiring (W3) is spaced apart from the first wiring (see Annotation 2, Fig. 35 of Muranaka, W1) and the second wiring (see Annotation 2, Fig. 35 of Muranaka, W2),
wherein the third wiring (W3) has the first width in the first direction,
wherein a lower surface of the third wiring (W3) is at a sixth distance, and the sixth distance is at a same distance as the fourth distance from the upper surface of the substrate (Fig. 35, semiconductor substrate 1, ¶ [0107]) or is closer than the fourth distance to the upper surface of the substrate (1), and
wherein the sixth distance is farther than the fifth distance from the upper surface of the substrate (1).
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Annotation 2, Fig. 35 of Muranaka
It would have been obvious to one of ordinary skill in the art before the time of the effective filling date of the invention to modify the semiconductor device of Choi with the additional wiring as disclosed by Muranaka, to provide interconnection to the semiconductor device (see Muranaka, ¶ [0107]).
Claims 10, and 16-18 are rejected under 35 U.S.C. 103 as being unpatentable over Choi (US 20190198426 A1) in view of Kim et al. (US 20190157214 A1) herein after “Kim”.
Regarding claim 10, Figs. 1 and 13 of Choi disclose the semiconductor device of claim 1 as applied above, and Fig. 1 of Choi further discloses wherein the substrate (110) includes a peripheral circuit region (see Annotation 3, Fig. 1 of Choi, PRC), and a through via region (see Annotation 3, Fig. 1 of Choi, TVR),
wherein the first contact (122) is in the peripheral circuit region (PRC),
wherein the through via (134) is in the through via region (TVR), wherein the semiconductor device further includes:
a peripheral structure (121) in the peripheral circuit region (PRC), wherein the first interlayer insulating layer (120) is on the peripheral structure (121); and
wherein the peripheral structure (121) includes:
a peripheral transistor (“The unit devices 121 may be individual devices, and may include a metal-oxide-semiconductor field effect transistor (MOSFET)”, ¶ [0020]) on/in the substrate (110).
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Annotation 3, Fig. 1 of Choi
Choi discloses that the device “may include a memory device such as a dynamic random access memory (DRAM)” (¶ [0080]), but fails to explicitly disclose the substrate includes a cell array region,
a cell structure in the cell array region, wherein the first interlayer insulating layer is on the cell structure,
a peripheral contact that is electrically connected to the peripheral transistor and is between the substrate and the first contact;
wherein the cell structure includes:
a word line in the substrate;
a storage node contact that is in contact with the substrate and is at one side of the word line;
a bit line contact that is in contact with the substrate and is at another side of the word line;
a bit line on the bit line contact, wherein the bit line overlaps the word line; and
a capacitor on the storage node contact.
In the similar field of endeavor of semiconductor devices, Figs. 1-2 of Kim discloses the substrate (Fig. 2, substrate 100, ¶ [0025]) includes a cell array region (Fig. 1, cell array region CAR, ¶ [0025]),
a cell structure (Fig. 2, cell transistor section CS, ¶ [0026]) in the cell array region (CAR), wherein the first interlayer insulating layer (Fig. 2, low-k dielectric layers LK1, ¶ [0030]) is on the cell structure (CS),
a peripheral contact (Fig. 2, first lower contact 111, ¶ [0033]) that is electrically connected to the peripheral transistor (Fig. 2, peripheral transistor section PS, ¶ [0033]) and is between the substrate (100) and the first contact (131);
wherein the cell structure (CS) includes:
a word line (Fig. 1, word line WL, ¶ [0027]) in the substrate (100);
a storage node contact (Fig. 1, node contacts NT, ¶ [0028]) that is in contact with the substrate (100) and is at one side of the word line (WL);
a bit line contact (Fig. 1, “The bit lines BL may intersect the word lines WL to extend in the second direction D2, and may be connected to a plurality of the first active region ACT1”, ¶ [0028]) that is in contact with the substrate (100) and is at another side of the word line (WL);
a bit line (Fig. 1, bit line BL, ¶ [0027]) on the bit line contact, wherein the bit line overlaps the word line (WL); and
a capacitor (“data storage structure DSS may include capacitors”, ¶ [0026]) on the storage node contact (NT).
It would have been obvious to one of ordinary skill in the art before the time of the effective filling date of the invention to modify the semiconductor device of Choi with the cell array region as disclosed by Kim, to include a DRAM device (see Kim, ¶ [0026]) as suggested by Choi (see Choi, ¶ [0080]).
Regarding claim 16, Figs. 1 and 13 of Choi disclose a semiconductor device comprising:
a substrate (110) that includes a peripheral circuit region (PRC), and a through via region (TVR);
a peripheral structure (121) in the peripheral circuit region (PRC);
a first interlayer insulating layer (120) on the peripheral structure (121), and the through via region (TVR);
a second interlayer insulating layer (143) on the first interlayer insulating layer (120), wherein the second interlayer insulating layer (143) is in direct contact with the first interlayer insulating layer (120);
a first contact (122) in the first interlayer insulating layer (120), wherein the first contact (122) is electrically connected to the peripheral structure (121);
a through via (134) in the through via region (TVR), wherein the through via (134) extends in the first interlayer insulating layer (120) and the substrate (110);
a first wiring (153 connected to 122) in the second interlayer insulating layer (143), wherein the first wiring (153 connected to 122) is in contact with the first contact (122); and
a second wiring (153 connected to 134) in the second interlayer insulating layer (143), wherein the second wiring (153 connected to 134) is in contact with the through via (134),
wherein the peripheral structure (121) includes:
a peripheral transistor (“The unit devices 121 may be individual devices, and may include a metal-oxide-semiconductor field effect transistor (MOSFET)”, ¶ [0020]) on or in the substrate (110); and
wherein the first interlayer insulating layer (120) includes a first material that has a first density (“The lower interlayer insulating film 120 may include… silicon nitride (SiN)”, ¶ [0019]),
wherein the second interlayer insulating layer (143) includes a second material that has a second density (“The second insulating layer 143 may be a silicon carbon nitride (SiCN) film”, ¶ [0049]), and
wherein the first density is greater than the second density (Silicon nitride is known to have a greater density than silicon carbon nitride).
Choi discloses that the device “may include a memory device such as a dynamic random access memory (DRAM)” (¶ [0080]), but fails to explicitly disclose the substrate includes a cell array region,
a cell structure in the cell array region,
a first interlayer insulating layer on the cell structure,
a peripheral contact that is electrically connected to the peripheral transistor and is between the substrate and the first contact;
wherein the cell structure includes:
a word line in the substrate;
a storage node contact that is in contact with the substrate and is at one side of the word line;
a bit line contact that is in contact with the substrate and is at another side of the word line;
a bit line on the bit line contact, wherein the bit line overlaps the word line; and
a capacitor on the storage node contact.
In the similar field of endeavor of semiconductor devices, Figs. 1-2 of Kim discloses the substrate (100) includes a cell array region (CAR),
a cell structure (CS) in the cell array region (CAR),
a first interlayer insulating layer (LK1) is on the cell structure (CS),
a peripheral contact (111) that is electrically connected to the peripheral transistor (PS) and is between the substrate (100) and the first contact (131);
wherein the cell structure (CS) includes:
a word line (WL) in the substrate (100);
a storage node contact (NT) that is in contact with the substrate (100) and is at one side of the word line (WL);
a bit line contact (Fig. 1, “The bit lines BL may intersect the word lines WL to extend in the second direction D2, and may be connected to a plurality of the first active region ACT1”, ¶ [0028]) that is in contact with the substrate (100) and is at another side of the word line (WL);
a bit line (BL) on the bit line contact, wherein the bit line overlaps the word line (WL); and
a capacitor (“data storage structure DSS may include capacitors”, ¶ [0026]) on the storage node contact (NT).
It would have been obvious to one of ordinary skill in the art before the time of the effective filling date of the invention to modify the semiconductor device of Choi with the cell array region as disclosed by Kim, to include a DRAM device (see Kim, ¶ [0026]) as suggested by Choi (see Choi, ¶ [0080]).
Regarding claim 17, Choi and Kim together disclose the semiconductor device of claim 16, and Fig. 1 of Choi further discloses wherein an upper surface of the first interlayer insulating layer (120) is at a first distance from an upper surface of the substrate (110),
wherein an upper surface of the first contact (122) is at a second distance from the upper surface of the substrate (110),
wherein an upper surface of the through via (134) is at a third distance from the upper surface of the substrate (110),
wherein a lower surface of the first wiring (153 connected to 122) is at a fourth distance from the upper surface of the substrate (110), and the fourth distance is closer than the first distance to the upper surface of the substrate (110), and
wherein a lower surface of the second wiring (153 connected to 134) is at a fifth distance from the upper surface of the substrate (110).
Choi and Kim fail to disclose the second distance is farther than the first distance from the upper surface of the substrate;
the third distance is farther than the second distance from the upper surface of the substrate; and
the fifth distance is closer than the fourth distance to the upper surface of the substrate.
However, it has been held that where the only different between the prior art and the claims was a recitation of relative dimensions of the claimed element, and a device having the claimed relative dimensions would not perform differently than the prior art device, the claimed device was not patentably distinct from the prior art device (MPEP 2144.04).
It would have been obvious to one of ordinary skill in the art before the time of the effective filling date of the invention that a mere change in the height of the contact, via and wiring structure was within the level of ordinary skill in the art and/or because changes in size and shape are prima facie obvious absent persuasive evidence that the particular configuration is significant (MPEP 2144.04(IV)).
Regarding claim 18, Choi and Kim together disclose the semiconductor device of claim 16 as applied above, and Fig. 1 of Choi further discloses wherein the first interlayer insulating layer (120) is free of carbon (“The lower interlayer insulating film 120 may include silicon oxide (SiO2) and/or silicon nitride (SiN)”, ¶ [0019]), and
wherein the second interlayer insulating layer (143) includes carbon (“The second insulating layer 143 may be a silicon carbon nitride (SiCN) film”, ¶ [0049]).
Allowable Subject Matter
Claims 5-9, 12, and 14 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claims 19-20 would be allowable if rewritten to overcome the rejection(s) under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), 2nd paragraph, set forth in this Office action and to include all of the limitations of the base claim and any intervening claims.
Reasons for Indicating Allowable Subject Matter
The following is a statement of reasons for the indication of allowable subject matter:
Regarding claim 5, Fig. 13 of Choi discloses a polishing stop pattern (141) that is in contact with a side surface of the second wiring (153);
and a capping pattern (142) that is on the polishing stop pattern (141) and in contact with the side surface of the second wiring (153), wherein the upper surface of the first interlayer insulating layer (120) includes a protrusion (PRO) that extends away from the upper surface of the substrate (110) and is in contact with a lower surface of the polishing stop pattern (141).
Choi and other prior art of record, as well as other pertinent prior art Han et al. (US 20180096880 A1), alone or in combination fail to disclose or fairly suggest “wherein the second interlayer insulating layer is on a side surface of the protrusion” in combination with the other limitations of claim 5.
Claims 6-9 depend upon claim 5 and would be allowable for at least the same reasons as claim 5.
Regarding claim 12, Choi and other prior art of record alone or in combination fail to disclose or fairly suggest “wherein the second interlayer insulating layer is on a side surface of the protrusion” in combination with the other limitations of claim 12.
Regarding claim 19, Fig. 13 of Choi discloses a polishing stop pattern (141) that is in contact with a side surface of the second wiring (153);
and a capping pattern (142) that is on the polishing stop pattern (141) and in contact with the side surface of the second wiring (153), wherein the upper surface of the first interlayer insulating layer (120) includes a protrusion (PRO) that extends away from the upper surface of the substrate (110) and is in contact with a lower surface of the polishing stop pattern (141).
Choi and other prior art of record, as well as other pertinent prior art Han et al. (US 20180096880 A1), alone or in combination fail to disclose or fairly suggest “wherein the second interlayer insulating layer is on a side surface of the protrusion” in combination with the other limitations of claim 19.
Claim 20 depends upon claim 19 and would be allowable for at least the same reasons as claim 19.
Conclusion
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/C.A.N./ Examiner, Art Unit 2893
/YARA B GREEN/ Supervisor Patent Examiner, Art Unit 2893
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