DETAILED ACTION
This application, 18/739431, attorney docket P202305698US01, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . The applicant or assignee is IBM corp., and has an effective filing date of 6/11/2024, Claims 1-25 are pending and are considered below. Note that examiner will use numbers in parentheses to indicate numbered elements in prior art figures, and brackets to point to paragraph numbers where quoted material or specific teachings can be found.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
Claims 5 and 15 recite, “… non-conducting fill material is around a metal fill material.” Around can mean “near” or can mean partially, or fully, surrounds” It is not clear how to interpret around in this claim.
Claim 6 and 16 recite, “…backside spacers are formed on a side of a substrate, the first transistor and the second transistor being above the substrate…”. “Above” is a relative which renders the claim indefinite. It is not clear the relationship between “above” and “a side”
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-4, 7, 8,11-14 and 17 and 18 are rejected under 35 U.S.C. 102a1/a2 as being anticipated by Su et al. (U.S.2021/0104616).
As for claims 1 and 11,
Su teaches in figure 2B a semiconductor structure and the method of forming the structure, comprising:
a first transistor (106 on the left) having a gate structure (212A); and
a second transistor (106 center) having the gate structure,
the gate structure (212) comprising an upper portion (Above 142) and a lower portion (surrounding the channels), wherein the upper portion comprises a first bottom surface (over 112) and is outside an active region of the first transistor and the second transistor (over 104, STI), the upper portion being between the first transistor and the second transistor,
wherein the lower portion comprises a second bottom surface and is inside the active region of the first transistor and the second transistor. (above 120).
As for claim 2 and 12,
Su teaches the semiconductor structure of claim 1 and the method of forming the structure, and teaches the first transistor and the second transistor comprise channel regions (122), the second bottom surface extending underneath the channel regions. (Shown in figure 2B.)
As for claim 3 and 13,
Su teaches the semiconductor structure of claim 1 and the method of forming the structure, wherein the first bottom surface is vertically above the second bottom surface. (shown in figure 2B)
As for claim 4 and 14,
Su teaches the semiconductor structure of claim 1 and the method of forming the structure, wherein a non-conducting fill material (dielectric 142 [0044]), is underneath the upper portion, the non-conducting fill material being outside the active region of the first transistor and the second transistor.
As for claim 7 and 17,
Su teaches the semiconductor structure of claim 1 and the method of forming the structure, wherein a non-conducting fill material is formed on an edge of the gate structure so as to be laterally displaced from the upper portion. (displace by dielectric 112)
As for claim 8 and 18,
Su teaches the semiconductor structure of claim 7 and the method of forming the structure, wherein the non-conducting fill material comprises compressive stress or tensile stress. (Dielectric stack 142 can include one or more insulating layers made of any suitable insulating material, such as a silicon oxide, silicon nitride, silicon oxynitride, FSG, any other low-k dielectric material, or a high-k material, can be either compressive or tensile).
Allowable Subject Matter
Claims 5 and 6 and 15 and 16 are objected to as being dependent upon a rejected base claim and rejected under §112b, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims, and rewritten to overcome the indefiniteness rejection.
The following is a statement of reasons for the indication of allowable subject matter: as for claims 5 and 15, the prior art does not teach a dielectric fill that surrounds a metal fill between nanowire transistors.
As for claim 6 and 16, the prior art does not teach the device of claim 1 with backside spacers formed on a side of a substrate a boundary between the upper portion and the lower portion of the gate structure is self-aligned to the backside spacers.
Claims 9 and 10 and 19 and 20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims,
As for claim 9 and 19, the prior art does not teach the first source/drain region and the second source/drain region e self-aligned to first backside spacers.
Claims 10 and 20 depend from claim 9 and includes the same novel limitation.
Claims 21-25 are allowed.
As for claim 21and 22, The prior art does not teach the semiconductor structure that includes a liner formed on an edge of the gate structure so as to be laterally displaced from the non-conducting fill material and a metal fill material formed on the liner such that the first channel region intervenes between the metal fill material and the non-conducting fill material.
As for claim 23,
A semiconductor structure comprising: a first transistor and a second transistor having a gate structure on a substrate, with a non-conducting fill material self-aligned to backside spacers.
Claims 25 and 25 depend from claim 23 and include the same limitations.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JOHN A BODNAR whose telephone number is (571)272-4660. The examiner can normally be reached M-Th and every other Friday 7:30-5:30 Central time.
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/JOHN A BODNAR/ Primary Examiner, Art Unit 2893
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