DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 12/14/2024 was filed after the mailing date of the application on 06/11/2024. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1, 3, 14-15, 17, and 28-30 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lee et al (US Pub. 20210066642) in view of NA et al (US Pub. 20210050405).
Regarding claim 1, Park discloses:
A display panel, (at least fig. 1 and paragraph 56. Describes the display device 1) comprising:
A substrate in which a transmission area, a dummy area surrounding the transmission area, and a display area surrounding the dummy area are defined, (at least fig. 2B-3A and paragraphs 56-57, 73. Describes the second area A2 may correspond to a display area capable of displaying an image. The first area A1 may be a transmission area capable of transmitting light and/or sound that is output from the component to the outside or travels from the outside toward the component. Para. 57, describes: A third area A3 may be disposed between the first area A1 and the second area A2. The third area A3 may be a non-display area in which no pixels are arranged. Para. 73, describes: the display panel 10 includes a display layer 200 disposed on a substrate 100);
A driving circuit disposed in the display area and including a transistor, (at least fig. 3-4 and paragraph 74. Describes each of the plurality of pixels included in the display layer 200 may include a pixel circuit and a display element electrically connected to the pixel circuit. The pixel circuit may include a transistor and a storage capacitor, and the display element may include a light-emitting diode, for example, an organic light-emitting diode (OLED));
A voltage line disposed in the display area and electrically connected to the driving circuit, (at least fig. 4-5 and paragraph 84. Describes the first transistor T1, which is a driving transistor, may be connected to the driving voltage line PL and the capacitor Cst, and may control a driving current flowing from the driving voltage line PL to the organic light-emitting diode OLED);
An insulating layer on the voltage line, (at least fig. 5, 8 and paragraphs 97, 100. Describes for example, the at least one inorganic insulating layer IL may include at least one of a buffer layer 201. Para. 100, describes: The pixel circuit PC may be arranged on the buffer layer 201);
A first pixel electrode disposed on the insulating layer, in the display area, (at least fig. 8, 10 and paragraph 109. Describes the pixel electrode 221 may be disposed on the second organic insulating layer 211);
A bank layer covering an edge of the first pixel electrode, the bank layer defining a first opening overlapping the first pixel electrode, (at least fig. 8, 10 and paragraph 110. Describes the pixel defining layer 215 may be disposed on the pixel electrode 221. The pixel defining layer 215 may include an opening OP via which an upper surface of the pixel electrode 221 is exposed, and may cover an edge of the pixel electrode 221);
An emission layer overlapping the first pixel electrode through the first opening of the bank layer, (at least fig. 8, 10 and paragraph 114. Describes the emission layer 222b may be arranged to overlap the opening OP of the pixel defining layer 215 and/or the pixel electrode 221);
An opposing electrode disposed on the emission layer and overlapping the first pixel electrode and the emission layer, (at least fig. 8, 10 and paragraph 120. Describes the opposite electrode 223 faces the pixel electrode 221, and the emission layer 222b is disposed between the pixel electrode 221 and the opposite electrode 223); and
A dummy electrode layer disposed on the insulating layer, in the dummy area, (at least fig. 14, 16 and paragraph 155, 157. Describes the metal layer 450 may be provided on the second substrate (e.g., the encapsulation member 300) and may overlap the plurality of first spacers SPC1 and the plurality of detouring wires DWL disposed on the first substrate (e.g., the substrate 100), with the metal layer 450 configured to prevent external light incident via the transmission area (e.g., the first area A1) from reaching the plurality of detouring wires DWL. Para. 157, describes: The metal layer 450 may be in a floating state where it is not electrically connected to its surrounding elements, for example, the first and second sensing electrodes 410 and 420 and the dummy electrodes 430. The metal layer 450 may overlap the first spacers SPC1 of the third area A3. According to an exemplary embodiment of the present disclosure, the metal layer 450 may be disposed in at least one of the first insulating layer 43 and the second insulating layer 45)
Wherein the bank layer extends towards the dummy area and defines a plurality of dummy openings overlapping the dummy electrode layer, (at least fig. 8, 10 and paragraphs 110, 124. Describes the pixel defining layer 215 may be disposed on the pixel electrode 221. The pixel defining layer 215 may include an opening OP via which an upper surface of the pixel electrode 221 is exposed, and may cover an edge of the pixel electrode 221. Para. 124, describes: The first spacers SPC1 may surround the first area A1 and may be arranged at regular intervals in the third area A3. For example, the first spacers SPC1 may be located on the insulating layers or the pixel defining layer 215 in the third area A3).
Regarding claim 15, Park discloses:
An electronic apparatus, (at least fig. 1 and paragraph 56. Describes the display device 1) comprising:
A display panel in which a transmission area, a dummy area surrounding the transmission area, and a display area surrounding the dummy area are defined, (at least fig. 2B-3A and paragraphs 56-57, 73. Describes the second area A2 may correspond to a display area capable of displaying an image. The first area A1 may be a transmission area capable of transmitting light and/or sound that is output from the component to the outside or travels from the outside toward the component. Para. 57, describes: A third area A3 may be disposed between the first area A1 and the second area A2. The third area A3 may be a non-display area in which no pixels are arranged. Para. 73, describes: the display panel 10 includes a display layer 200 disposed on a substrate 100) the display panel comprising:
A driving circuit disposed in the display area and including a transistor, (at least fig. 3-4 and paragraph 74. Describes each of the plurality of pixels included in the display layer 200 may include a pixel circuit and a display element electrically connected to the pixel circuit. The pixel circuit may include a transistor and a storage capacitor, and the display element may include a light-emitting diode, for example, an organic light-emitting diode (OLED));
A voltage line disposed in the display area and electrically connected to the driving circuit, (at least fig. 4-5 and paragraph 84. Describes the first transistor T1, which is a driving transistor, may be connected to the driving voltage line PL and the capacitor Cst, and may control a driving current flowing from the driving voltage line PL to the organic light-emitting diode OLED);
An insulating layer on the voltage line, (at least fig. 5, 8 and paragraphs 97, 100. Describes for example, the at least one inorganic insulating layer IL may include at least one of a buffer layer 201. Para. 100, describes: The pixel circuit PC may be arranged on the buffer layer 201);
A first pixel electrode disposed on the insulating layer, in the display area, (at least fig. 8, 10 and paragraph 109. Describes the pixel electrode 221 may be disposed on the second organic insulating layer 211);
A bank layer covering an edge of the first pixel electrode and defining a first opening overlapping the first pixel electrode, (at least fig. 8, 10 and paragraph 110. Describes the pixel defining layer 215 may be disposed on the pixel electrode 221. The pixel defining layer 215 may include an opening OP via which an upper surface of the pixel electrode 221 is exposed, and may cover an edge of the pixel electrode 221);
An emission layer overlapping the first pixel electrode through the first opening of the bank layer, (at least fig. 8, 10 and paragraph 114. Describes the emission layer 222b may be arranged to overlap the opening OP of the pixel defining layer 215 and/or the pixel electrode 221);
An opposing electrode disposed on the emission layer and overlapping the first pixel electrode and the emission layer, (at least fig. 8, 10 and paragraph 120. Describes the opposite electrode 223 faces the pixel electrode 221, and the emission layer 222b is disposed between the pixel electrode 221 and the opposite electrode 223); and
A dummy electrode layer disposed on the insulating layer, in the dummy area, (at least fig. 14, 16 and paragraph 155, 157. Describes the metal layer 450 may be provided on the second substrate (e.g., the encapsulation member 300) and may overlap the plurality of first spacers SPC1 and the plurality of detouring wires DWL disposed on the first substrate (e.g., the substrate 100), with the metal layer 450 configured to prevent external light incident via the transmission area (e.g., the first area A1) from reaching the plurality of detouring wires DWL. Para. 157, describes: The metal layer 450 may be in a floating state where it is not electrically connected to its surrounding elements, for example, the first and second sensing electrodes 410 and 420 and the dummy electrodes 430. The metal layer 450 may overlap the first spacers SPC1 of the third area A3. According to an exemplary embodiment of the present disclosure, the metal layer 450 may be disposed in at least one of the first insulating layer 43 and the second insulating layer 45); and
A component overlapped with the transmission area of the display panel, (at least fig. 2 and paragraphs 69, 162. Describes a component 20 may be located in the first area A1. The component 20 may include an electronic element. For example, the component 20 may be an electronic element that uses light or sounds. For example, the electronic element may include a sensor that receives and outputs light, like an infrared sensor, a camera that receives light and captures an image. Para. 162, describes: Because the first area A1 is capable of transmitting light, a component such as a sensor or a camera CMR arranged in the first area A1 may emit light toward the outside and/or receive external light.)
Wherein the bank layer extends towards the dummy area and further defines a plurality of dummy openings overlapping the dummy electrode layer, (at least fig. 8, 10 and paragraphs 110, 124. Describes the pixel defining layer 215 may be disposed on the pixel electrode 221. The pixel defining layer 215 may include an opening OP via which an upper surface of the pixel electrode 221 is exposed, and may cover an edge of the pixel electrode 221. Para. 124, describes: The first spacers SPC1 may surround the first area A1 and may be arranged at regular intervals in the third area A3. For example, the first spacers SPC1 may be located on the insulating layers or the pixel defining layer 215 in the third area A3).
Regarding claim 3, Park discloses:
Wherein the voltage line extends towards the dummy area and a portion of the voltage line overlaps the dummy electrode layer, and the dummy electrode layer is electrically connected to the voltage line, (at least fig. 16 and paragraph 174. Describes the metal layer 450 may directly contact the upper surface of the encapsulation member 300, and may be formed in a process of forming the input sensing layer 40, for example, a process of forming the first trace lines 415 and first connecting electrodes 411. the first trace lines 415 located in the fourth area A4 and the metal layer 450 located in the third area A3 are arranged directly on the upper surface of the encapsulation member 300. At least one of the trace lines located in the fourth area A4, for example, the first trace lines 415, may overlap the sealant ST).
Regarding claim 6, Park discloses:
Wherein the plurality of dummy openings of the bank layer includes a first dummy opening, a second dummy opening, and a third dummy opening, which overlap different portions of the dummy electrode layer, respectively.
Regarding claim 14, Park discloses:
Wherein the bank layer includes a light-shielding material, (at least fig. 7-8 and paragraph 125. Describes the first spacers SPC1 may include a material the same as that included in the pixel defining layer 215. The pixel defining layer 215 and the first spacers SPC1 may be formed together through a photolithographic process using a halftone mask or the like. The pixel defining layer 215 and the first spacers SPC1 may include polyimide (PI)).
Regarding claim 17, Park discloses:
Wherein the voltage line extends towards the dummy area, and a portion of the voltage line overlaps the dummy electrode layer, and the dummy electrode layer is electrically connected to the voltage line, (at least fig. 16 and paragraph 174. Describes the metal layer 450 may directly contact the upper surface of the encapsulation member 300, and may be formed in a process of forming the input sensing layer 40, for example, a process of forming the first trace lines 415 and first connecting electrodes 411. the first trace lines 415 located in the fourth area A4 and the metal layer 450 located in the third area A3 are arranged directly on the upper surface of the encapsulation member 300. At least one of the trace lines located in the fourth area A4, for example, the first trace lines 415, may overlap the sealant ST).
Regarding claim 28, Park discloses:
Wherein the display panel further comprises: an encapsulation layer on the opposing electrode, (at least fig. 18 and paragraph 160. Describes the encapsulation member 300 may be arranged to cover the display layer 200. The encapsulation member 300 is to encapsulate the display layer 200, and may be a rigid encapsulation substrate); and
A cover window on the encapsulation layer, (at least fig. 18 and paragraph 166. Describes the window 60 may be arranged on the optical functional layer 50 through the optical clear adhesive OCA)
Wherein the cover window includes a light-shielding portion overlapping at least one dummy opening of the plurality of dummy openings defined in the dummy area, and a light-transmitting portion overlapping at least one of remaining dummy openings of the plurality of dummy openings, (at least fig. 18 and paragraphs 67, 178. Describes the optical functional layer 50 may include a lens layer. The lens layer may enhance the emission efficiency or reduce color deviation of light emitted from the display panel 10. Para. 178, describes: The optical functional layer 50 may be arranged to cover a portion of the metal layer 450, and the optical clear adhesive OCA and the window 60 may be arranged on the optical functional layer 50. the optical clear adhesive OCA may include a third hole OCAH by removing a portion corresponding to the first area A1 from the optical clear adhesive OCA. A light-shielding unit 61 may be arranged on the rear surface of the window 60 to cover elements arranged in the fourth area A4, for example, the first trace lines 415).
Regarding claim 29, Park discloses:
Wherein the component comprises a sensor or a camera, (at least fig. 17 and paragraph 162. Describes a component such as a sensor or a camera CMR arranged in the first area A1 may emit light toward the outside and/or receive external light).
Regarding claim 30, Park discloses:
Wherein the bank layer includes a light-shielding material, (at least fig. 7-8 and paragraph 125. Describes the first spacers SPC1 may include a material the same as that included in the pixel defining layer 215. The pixel defining layer 215 and the first spacers SPC1 may be formed together through a photolithographic process using a halftone mask or the like. The pixel defining layer 215 and the first spacers SPC1 may include polyimide (PI)).
Claim(s) 2, 4-5, 16, and 18-19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lee et al (US Pub. 20210066642) in view of NA et al (US Pub. 20210050405).
Regarding claim 2, Park does not disclose:
Further comprising a dummy transistor disposed below the dummy electrode layer, wherein the dummy electrode layer is electrically insulated from the dummy transistor.
NA teaches:
Further comprising a dummy transistor disposed below the dummy electrode layer, wherein the dummy electrode layer is electrically insulated from the dummy transistor, (at least fig. 8-9 and paragraph 135. Describes the dummy area DMA includes a plurality of dummy units DU. Each of the dummy units DU includes a dummy semiconductor layer D10, a first dummy conductive layer D20 and a second dummy conductive layer D30, which at least partially overlap each other with the insulating layers 112, 113, and 115 therebetween).
The two references are analogous art because they are related with the same field of invention of display device.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate opposing voltage lines with same voltage level as taught by NA with the display device as disclose by Park. The motivation to combine the NA reference is to adjust pattern density to reduce process defects.
Regarding claim 4, Park does not disclose:
Wherein the voltage line has a same voltage level as a voltage level of the opposing electrode.
NA teaches:
Wherein the voltage line has a same voltage level as a voltage level of the opposing electrode, (at least fig. 7-8 and paragraphs 129, 133. Describes Each of the load units LU may include a load semiconductor layer L10, a first load conductive layer L20, and a second load conductive layer L30, which at least partially overlap each other with insulating layers 112, 113, and 115 therebetween. Para. 133, describes: the load semiconductor layer L10 may have the same voltage level as the second load conductive layer L30).
The two references are analogous art because they are related with the same field of invention of display device.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate opposing voltage lines with same voltage level as taught by NA with the display device as disclose by Park. The motivation to combine the NA reference is to reduce electrostatic discharge.
Regarding claim 5, Park does not disclose:
Wherein the driving circuit further includes an initialization transistor which is electrically connected to the first pixel electrode and initializes the first pixel electrode, and the voltage line is electrically connected to the initialization transistor.
NA teaches:
Wherein the driving circuit further includes an initialization transistor which is electrically connected to the first pixel electrode and initializes the first pixel electrode, and the voltage line is electrically connected to the initialization transistor, (at least fig. 5B and paragraphs 99, 100. Describes a first initializing TFT T4. Para. 100, describes: The driving voltage line PL transmits a driving voltage ELVDD to the driving TFT T1, and the initializing voltage line VL transmits an initializing voltage Vint that initiates the driving TFT T1 and a pixel electrode of the organic light-emitting diode OLED).
The two references are analogous art because they are related with the same field of invention of display device.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate an initialization transistor as taught by NA with the display device as disclose by Park. The motivation to combine the NA reference is to activate the driving transistor so current can flow to the organic light-emitting diode OLED.
Regarding claim 16, Park does not disclose:
Wherein the display panel further comprises a dummy transistor disposed below the dummy electrode layer, wherein the dummy electrode layer is electrically insulated from the dummy transistor.
NA teaches:
Wherein the display panel further comprises a dummy transistor disposed below the dummy electrode layer, wherein the dummy electrode layer is electrically insulated from the dummy transistor, (at least fig. 8-9 and paragraph 135. Describes the dummy area DMA includes a plurality of dummy units DU. Each of the dummy units DU includes a dummy semiconductor layer D10, a first dummy conductive layer D20 and a second dummy conductive layer D30, which at least partially overlap each other with the insulating layers 112, 113, and 115 therebetween).
Regarding the rejection of claim 16, refer to the motivation of claim 2.
Regarding claim 18, Park does not disclose:
Wherein the voltage line has a same voltage level as a voltage level of the opposing electrode.
NA teaches:
Wherein the voltage line has a same voltage level as a voltage level of the opposing electrode, (at least fig. 7-8 and paragraphs 129, 133. Describes Each of the load units LU may include a load semiconductor layer L10, a first load conductive layer L20, and a second load conductive layer L30, which at least partially overlap each other with insulating layers 112, 113, and 115 therebetween. Para. 133, describes: the load semiconductor layer L10 may have the same voltage level as the second load conductive layer L30).
Regarding the rejection of claim 18, refer to the motivation of claim 4.
Regarding claim 19, Park does not disclose:
Wherein the driving circuit includes an initialization transistor electrically which is connected to the first pixel electrode and initializes the first pixel electrode, and the voltage line is electrically connected to the initialization transistor.
NA teaches:
Wherein the driving circuit includes an initialization transistor electrically which is connected to the first pixel electrode and initializes the first pixel electrode, and the voltage line is electrically connected to the initialization transistor, (at least fig. 5B and paragraphs 99, 100. Describes a first initializing TFT T4. Para. 100, describes: The driving voltage line PL transmits a driving voltage ELVDD to the driving TFT T1, and the initializing voltage line VL transmits an initializing voltage Vint that initiates the driving TFT T1 and a pixel electrode of the organic light-emitting diode OLED).
Regarding the rejection of claim 19, refer to the motivation of claim 5.
Allowable Subject Matter
Claims 6-13 and 20-27 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: Prior art does not suggest or disclose wherein the plurality of dummy openings of the bank layer includes a first dummy opening, a second dummy opening, and a third dummy opening, which overlap different portions of the dummy electrode layer, respectively.
Conclusion
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/IFEDAYO B ILUYOMADE/Primary Examiner, Art Unit 2624 06/25/2026
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