DETAILED ACTION
This action is responsive to the following communication: the response filed 6/23/26. The changes and remarks disclosed therein have been considered.
Claim(s) status: 1-19 pending.
Terminal Disclaimer
The terminal disclaimer filed 6/23/26 disclaiming the terminal portion of any patent granted on this application has been reviewed and is accepted. The terminal disclaimer has been recorded.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-2, 10-13 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Chen et al. (US 2014/0254262 ‒hereinafter Chen).
Regarding claim 1, Chen discloses a memory device comprising:
a memory cell array (400; fig. 4) including a first memory block (block0 - blockM; fig. 5A) connected to a plurality of word-lines (WL0-WL63; fig. 5A); and
a control logic circuit (420; fig. 4) configured to:
receive (i.e. via line(s) 434; fig. 4) a first program command (a command for a program operation; para 0048, 0061), a first address (ADDR; fig. 4, i.e. “memory array 400 is addressable by word lines via row decoders 440A and 440B” para 0048) corresponding to a first word-line (any selected word line, i.e. WLn) among the plurality of word-lines (WL0-WL63), and a plurality of first page data (lower/upper pages of data to be programmed to respective pages of word lines; fig. 10A para 0051) from a controller (444; fig. 4); and
in response to the first program command and the first address (i.e. after receiving the program command and the first address ADDR),
perform (1056/1058, i.e. in a programming sequence; fig. 10A) a first unselection program operation (a program operation on an unselected word line, i.e. WLn-1/WLn+1; fig. 10A) on a second word-line (WLn-1/WLn+1) based on at least one first page data (i.e. “upper page data is programmed into WLn-1” para 0094, “lower page data is programmed into WLn+1” para 0095) among the plurality of first page data (i.e. pages of data),
in response to the first program command and the first address (i.e. after receiving the program command and the first address ADDR), perform (1060, i.e. in the programming sequence; fig. 10A) a first previous page read operation (a read operation on a previous page, i.e. the lower page that was previously programmed 1054 to the first word-line WLn, is performed; fig. 10A para 0096) on the first word-line (WLn) to read at least one previous page data (i.e. read lower page data previously programmed 1054 to WLn), and
in response to the first program command and the first address (i.e. after receiving the program command and the first address ADDR),
perform (1066, i.e. in the programming sequence; fig. 10A) a first selection program operation (a program operation on selected word line WLn; fig. 10A, further TABLE 1) on the first word-line (WLn) based on the at least one previous page data (i.e. the lower page data previously programmed 1054 to WLn) and remaining first page data (i.e. remaining upper page data of WLn; fig. 10A) among the plurality of first page data (i.e. pages of data).
Regarding claim 2, Chen discloses the memory device, wherein the first address corresponds to the first word-line (para 0048), and the second word-line is adjacent to the first word-line (WLn and WLn-1/WLn+1 are considered adjacent; fig. 2A).
Regarding claim 10, Chen discloses the memory device, further comprising: a page buffer (sense block 300; fig. 5B) connected to the memory cell array through a plurality of bit-lines (BL0-BLX; fig. 5B), and wherein the page buffer includes a plurality of data latches (any of latches DL1-DL3; fig. 5B) (further, sense block 300 includes the latches which functions to temporarily store page data for program/read, therefore is equivalent to a page buffer; fig. 10A para 0062-0063).
Regarding claim 11, Chen discloses the memory device, wherein the at least one first page data is stored in at least one data latch among a plurality of data latches during the first unselection program operation (para 0094-0095), and wherein the at least one previous page data is stored in the at least on data latch during the first selection program operation (para 0097).
Regarding claim 12, Chen discloses the memory device, further comprising: an address decoder (424; fig. 4) connected to the memory cell array through the plurality of word-lines (para 0048-0049), and configured to, in response to the first address (ADDR; fig. 4), select the second word-line (WLn-1/WLn+1; fig. 10A) during the first unselection program operation (1054/1056; fig. 10A) and select the first word-line (WLn; fig. 10A) during the first previous page read operation (1060; fig. 10A) and the first selection program operation (1066; fig. 10A).
Regarding claim 13, Chen discloses a storage device comprising:
a memory device (412; fig. 4) including a first memory block (block0 - blockM; fig. 5A) connected to a plurality of word-lines (WL0-WL63; fig. 5A); and
a controller (444; fig. 4) configured to control memory device,
wherein the controller is configured to transmit (i.e. via line(s) 434; fig. 4) a first program command (a command for a program operation; para 0048, 0061), a first address (ADDR; fig. 4, i.e. “memory array 400 is addressable by word lines via row decoders 440A and 440B” para 0048) corresponding to a first word-line (any selected word line, i.e. WLn) among the plurality of word-lines (WL0-WL63), and a plurality of first page data (lower/upper pages of data to be programmed to respective pages of word lines; fig. 10A para 0051) to the memory device (412) for programing (1054, 1066; fig. 10A) the plurality of first page data (i.e. program lower page and upper page on WLn; fig. 10A) in the first word-line (WLn), and
wherein the memory device (412) is configured to: in response to the first program command and the first address (i.e. after receiving the program command and the first address ADDR),
perform (1056/1058; fig. 10A) a first unselection program operation (a program operation on an unselected word line, i.e. WLn-1/WLn+1; fig. 10A) on a second word-line (WLn-1/WLn+1) based on at least one first page data (i.e. “upper page data is programmed into WLn-1” para 0094, “lower page data is programmed into WLn+1” para 0095) among the plurality of first page data (i.e. pages of data),
in response to the first program command and the first address (i.e. after receiving the program command and the first address ADDR),
perform (1060; fig. 10A) a first previous page read operation (a read operation on a previous page, i.e. the lower page that was previously programmed 1054 to the first word-line WLn, is performed; fig. 10A para 0096) on the first word-line (WLn) to read at least one previous page data (i.e. read lower page data previously programmed 1054 to WLn), and
in response to the first program command and the first address (i.e. after receiving the program command and the first address ADDR),
perform (1066; fig. 10A) a first selection program operation (a program operation on selected word line WLn; fig. 10A, further TABLE 1) on the first word-line (WLn) based on the at least one previous page data (i.e. the lower page data previously programmed 1054 to WLn) and remaining first page data (i.e. remaining upper page data of WLn; fig. 10A) among the plurality of first page data (i.e. pages of data).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 8-9 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chen et al. (US 2014/0254262 ‒hereinafter Chen) in view of Shiino (US 2019/0088312).
Regarding claim 8, Chen discloses the memory device, wherein the control logic performs the first selection program operation based on incremental step programming pulse (ISPP) scheme (fig. 6C).
Chen does not expressly disclose a two step incremental step programming pulse (ISPP) scheme.
Shiino discloses a two step incremental step programming pulse (ISPP) scheme (fig. 12).
Therefore, it would have been obvious to one with ordinary skill in the art before the
effective filing date of the invention to recognize that the device of Chen is modifiable as taught by Shiino for the purpose of improving data accessing schemes by reducing error bits in a read operation and improve the reliability of written data (para 0202 of Shiino).
Regarding claim 9, Chen discloses the memory device, wherein the control logic performs the first selection program operation based on incremental step programming pulse (ISPP) scheme (fig. 6C).
Chen does not expressly disclose a dual step incremental step programming pulse (ISPP) scheme.
Shiino discloses a dual step incremental step programming pulse (ISPP) scheme (fig. 12).
Therefore, it would have been obvious to one with ordinary skill in the art before the
effective filing date of the invention to recognize that the device of Chen is modifiable as taught by Shiino for the purpose of improving data accessing schemes by reducing error bits in a read operation and improve the reliability of written data (para 0202 of Shiino).
Allowable Subject Matter
Claim(s) 18-19 are allowed.
The following is an examiner’s statement of reasons for allowance: the prior art made of record and not relied upon is considered pertinent to applicant’s disclosure does not teach or suggest the claimed invention having the following limitation, in combination with the remaining claimed limitations.
With respect to independent claim 18 (and all dependent claim(s) therefrom), the prior art fails to teach or suggest the claimed limitations, namely the controller performs the first read operation using at least one reference voltage, and when the second word-line is not the last word line of the first memory block, the controller performs the first read operation using at least one read voltage different from the at least one reference voltage.
The allowable claims are supported in at least fig. 8A of the instant application.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Claim(s) 3-7, 14-17 is/are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: The prior art of record and considered pertinent to the applicant's disclosure does not teach or suggest the claimed invention having the following limitation, in combination with the remaining claimed limitations.
With respect to dependent claim 3, the prior art fails to teach or suggest the claimed limitations, namely perform a second unselection program operation on a third word-line based on at least one second page data among the plurality of second page data, perform a second previous page read operation on the second word-line to read the at least one first page data, and perform a second selection program operation on the second word-line based on the at least one first page data and remaining second page data among the plurality of second page data, wherein the second address corresponds to the second word-line, and wherein the third word-line is adjacent to the second word-line.
With respect to dependent claim 14 (and all dependent claim(s) therefrom), the prior art fails to teach or suggest the claimed limitations, namely perform a second unselection program operation on a third word-line based on at least one second page data among the plurality of second page data, perform a second previous page read operation on the second word-line to read the at least one first page data, and perform a second selection program operation on the second word-line based on the at least one first page data and remaining second page data among the plurality of second page data.
The allowable claims are supported in at least fig. 8A of the instant application.
Response to Arguments
Applicant's arguments filed 6/23/26 have been fully considered but are not persuasive.
The applicant submits that Chen et al. (US 2014/0254262 ‒hereinafter Chen) fails to disclose "first unselection program operation," "first previous page read operation," and "first selection program operation" are each performed "in response to the first program command and the first address," as recited in amended claims 1 and 13 (on page 11 of the response).
The examiner respectfully disagrees with the arguments. Chen discloses commands and addresses (fig. 4), and further a program sequence (steps 1052-1066; fig. 10A) that is essentially performed in response to commands (i.e. essentially a command for programming) and address corresponding to selected memory block, word-lines, or pages for programming (para 0048, 0061). Each "first unselection program operation," "first previous page read operation," and "first selection program operation" is such that in fig. 10A:
"first unselection program operation,” is any program operation for an unselected word line, as disclosed by Chen (1056/1058): program operation on an unselected word line WLn-1/WLn+1;
"first previous page read operation," is a reading operation on a previously programmed word line, as disclosed by Chen (1060): reading a previously programmed lower page of word line WLn;
and "first selection program operation," is program operation for the word line, as disclosed by Chen (1066): program operation on word line WLn.
Steps 1052-1066, including 1056, 1058, 1060, and 1066, are each and collectively responsive to the program command and the address received in order to be performed. That is, the program sequence is performed, "first unselection program operation," "first previous page read operation," and "first selection program operation" are each performed "in response to the first program command and the first address" at start of the program sequence (fig. 10A).
For at least the aforementioned reasons, the rejection is deemed proper and made final.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to UYEN SMET whose telephone number is (571)272-2267. The examiner can normally be reached M-F, 9 AM-5 PM.
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/UYEN SMET/
Primary Examiner, Art Unit 2824
Prosecution Insights