DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Acknowledgement is made to claim of priority as a continuation of U.S. Patent Application No. 18/484,125 filed on October 10, 2023, which is a continuation of U.S. Patent Application No. 18/318,295 filed on May 16, 2023, which is a continuation of U.S. Patent Application No. 17/449,134 filed on September 28, 2021，which is a divisional of U.S. Patent Application No. 16/853,839 filed on April 21, 2020, which is a bypass continuation of International Application No. PCT/CN2019/127878, filed on December 24, 2019.
Information Disclosure Statement
The information disclosure statements (IDS) submitted on June 11, 2024, September 16, 2025, and April 30, 2026 are being considered by the examiner.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-3 and 9-10 are rejected under 35 U.S.C. 103 as being unpatentable over Lee-551 (US 2017/0256551 A1) in view of Chang (US 2018/0286743 A1) and Yip (US 2015/001613 A1).
With respect to claim 1, Lee-551 teaches:
A semiconductor device (semiconductor device structure 100), comprising:
a stack of word line layers (conductive structures 126) and insulating layers (insulating structure 104) that are stacked alternatingly;
a first array region (first end 130) and a second array region (second end 132) of the stack (para. 45 “The first end 130 and the second, opposing end 132 of the conductive stack structure 124 may each be coupled to other components of a semiconductor device (e.g., a memory device) including the semiconductor device structure 100, such as one or more memory cell arrays (e.g., vertical memory cell arrays)”),
the first array region (130) and the second array region (132) being positioned at opposing sides of the stack along a first direction (right/left direction of Fig. 1F);
a first staircase (staircase structure 114a and 114b) formed between the first array region (130) and the second array region (132);
a second staircase (114c and 114d) formed between the first array region (130) and the second array region (132);
and contact structures (conductive contact structures 134) formed on the first staircase (114A) and the second staircase (114d), wherein the contact structures are connected to the word line layers (para. 53 “The conductive contact structures 134 may be coupled to the conductive structures 126”),
the first staircase comprises first stairs (114a) with a first step-down direction (X) and second stairs (114b) with a second step-down direction (-X),
Lee-551 fails to teach:
and each of all of the first stairs and each of all of the second stairs corresponds to a different one of the word line layers.
channel structures formed in a first array region and a second array region of the stack, the first array region and the second array region being positioned at opposing sides of the stack along a first direction; (Lee-551 teaches in para [0045] that the first and second regions may each be connected to vertical memory cell array but does not explicitly teach that the channel structure is within the first and second region)
Chang teaches in Fig. 2:
and each of all of the first stairs (stairs on left side of Fig. 2) and each of all of the second stairs (stairs on right side of Fig. 2) corresponds to a different one of the word line layers (left stairs correspond to even word line layers, right stairs correspond to odd word line layers).
Lee-551 discloses the claimed invention except for the first stairs and second stairs each corresponding to different wordline layers. Chang teaches that it is known to make the stack asymmetrical so that each side of the valley includes different layers. It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Lee-551 to make an asymmetrical stair structure since Chang states at para. 5 that such a modification would reduce the chip area used for the stair structure. See MPEP 2144.
Yip teaches an analogous structure in which a staircase region includes a memory cell region in which a stair step region 380 is between memory cell regions including vertical memory cells 301 (see Figs. 4 and 5). Yip therefore teaches:
channel structures (vertical strings 301 of memory cells) formed in a first array region (memory array region 370 on left of Fig. 5) and a second array region (memory array region 370 on right of Fig. 5) of the stack, the first array region and the second array region being positioned at opposing sides of the stack along a first direction (see Fig. 5, array regions 370 are on opposing ends of the staircase 380)
Lee-551/Chang discloses the claimed invention except for the regions on either side of the staircase being memory array regions including channels. Yip teaches that it is known to form channels in the opposing regions to create memory array regions. It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify Lee-551/Chang by Yip to include channels in the opposing regions for the purpose of allowing a more densely packed memory array while reducing noise (para [0064] of Yip). See MPEP 2144.
With respect to claim 2, Lee-551 further teaches:
wherein a portion of the stack (middle section 122) is between the first staircase (114a and 114b) and the second staircase (114c and 114d) along a second direction (y) perpendicular to the first direction (x), and the portion of the stack (122) is between the first array region (130) and the second array region (132) along the first direction (X).
With respect to claim 3, Lee-551 further teaches:
wherein the first step-down direction (X) is opposite to the second step-down direction (-X).
With respect to claim 9, Lee-551 further teaches:
the second staircase (114c and 114d) has third stairs (114c) with the first step-down direction (X) and fourth stairs (114d) with the second step-down direction (-X)
With respect to claim 10, Lee-551 further teaches:
wherein one of the word line layers (126) comprises a first portion in the first array region (130) and a second portion in the second array region (132), one of the contact structures (134) is connected to the first portion and the second portion through the portion of the stack between the first staircase and the second staircase (para. [0057] “The continuous conductive paths across the conductive stack structure 124 (e.g., from the first end 130 to the second, opposing end 132) provided by the configurations of the conductive structures 126 may permit an individual (e.g., single) switching device (e.g., transistor) of the string driver device 138 to drive voltages completely across (e.g., from the first end 130 to the second, opposing end 132) and/or in opposing directions across (e.g., toward the first end 130 and toward the second, opposing end 132) an individual tier 108 electrically connected thereto.”)
Claims 4-7 are rejected under 35 U.S.C. 103 as being unpatentable over Lee-551 (US 2017/0256551 A1) in view of Chang (US 2018/0286743 A1) and Yip (US 2015/001613 A1) as applied to independent claim 1 above and further in view of Lee-969 (US 2019/0244969 A1).
With respect to claim 4, Lee-551/Chang/Yip teaches all limitations of claim 1 upon which claim 4 depends. Yip further to teaches:
wherein the connection region (stair step region 380) is between the first array region (370 on left) and the second array region (370 on right).
Lee-551/Chang/Yip fails to teach:
dummy channel structures formed in a connection region of the stack,
Lee-969 teaches in Fig. 3:
dummy channel structures (dummy channel structures DCS2) formed in a connection region (connection region CNR) of the stack,
Lee-551/Chang/Yip discloses the claimed invention except for the dummy channel structure in the connection region. Lee-969 teaches that it is known to include dummy channel regions in the connection region. It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Lee-551/Chang/Yip with the dummy channel regions of Lee-969 because such a modification would provide mechanical support to the stack (para. [0046] of Lee-969). See MPEP 2144.
With respect to claim 5, Lee-969 further teaches:
wherein the dummy channel structures (DCS2) surround the contact structures (contact plugs 171) (see Fig. 3, each contact plug 171 is surrounded by four dummy channel structures DCS2).
It would have been obvious to one having ordinary skill in the effective filing date of the claimed invention to combine Lee-551 in view of Chang, Yip, and Lee-969 as explained above.
With respect to claim 6, Lee-969 further teaches:
wherein the dummy channel structures (DCS2) and the contact structures (171) are arranged in different rows along the first direction (D1) (see Fig. 3).
It would have been obvious to one having ordinary skill in the effective filing date of the claimed invention to combine Lee-551 in view of Chang, Yip, and Lee-969 as explained above.
With respect to claim 7, Lee-969 further teaches:
wherein a size of the contact structures (171) is greater than a size of the dummy channel structures (DCS2) (see Fig. 3).
It would have been obvious to one having ordinary skill in the effective filing date of the claimed invention to combine Lee-551 in view of Chang, Yip, and Lee-969 as explained above.
Claims 8 is rejected under 35 U.S.C. 103 as being unpatentable over Lee-551 (US 2017/0256551 A1) in view of Chang (US 2018/0286743 A1) and Yip (US 2015/001613 A1) as applied to independent claim 1 above and further in view of Kido (US 2014/0027838 A1).
With respect to claim 8, Lee-551/Chang/Yip teaches all limitations of claim 1 upon which claim 8 depends. Lee-551/Chang/Yip fails to teach:
wherein each height of each stair of the first staircase is smaller than each height of each stair of the second staircase, the height of each of the stairs of the first staircase and the second staircase corresponding to a number of the respective word line layers under the respective stair in a direction perpendicular to the stack of word line layers and insulating layers.
Kido teaches an analogous structure in which multiple staircases (80b, 80c, 80d, 80e) each have different word lines exposed. Kido teaches:
wherein each height of each stair (WL24, 25, 26, 27, 28, and 29) of the first staircase (stair array 80e) is smaller than each height of each stair (WL18, 19, 20, 21, 22, 23) of the second staircase (stair array 80d), the height of each of the stairs of the first staircase and the second staircase corresponding to a number of the respective word line layers under the respective stair in a direction perpendicular to the stack of word line layers and insulating layers (para. [0130] “The numbers added to the right of "WL" of the electrode layers WL1 to WL29 indicate where they are located in the order of electrode layers WL on the upper side from the back gate BG”).
Lee-551/Chang/Yip discloses the claimed invention except for the additional steps in a third step down direction. Kido teaches that it is known for each staircase to be arranged such that different word lines are exposed and each step of one staircase is higher than each step of the other staircase. It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify Lee-551/Chang/Yip by Kido to make staircases at the claimed elevations in order to prevent ineffective stairs from being made in which no contact is connected (para. [0173] of Kido) See MPEP 2144.
Claims 11-13 are rejected under 35 U.S.C. 103 as being unpatentable over Lee-551 (US 2017/0256551 A1) in view of Yip (US 2015/0001613 A1), Lee-969 (US 2019/0244969 A1), and Kido (US 2014/0027838 A1).
With respect to claim 11, Lee-551 teaches:A semiconductor device (semiconductor device structure 100), comprising:
a stack of word line layers (conductive structures 126) and insulating layers (insulating structure 104) that are stacked alternatingly;
a first array region (first end 130) and a second array region (second end 132) of the stack (para. 45 “The first end 130 and the second, opposing end 132 of the conductive stack structure 124 may each be coupled to other components of a semiconductor device (e.g., a memory device) including the semiconductor device structure 100, such as one or more memory cell arrays (e.g., vertical memory cell arrays)”),
the first array region (130) and the second array region (132) being positioned at opposing sides of the stack along a first direction (right/left direction of Fig. 1F);
a first staircase (staircase structure 114a and 114b) and a second staircase (staircase structure 114c and 114d) formed in a connection region (staircase structures 114 where contacts are formed), wherein
the connection region (114) is between the first array region (130) and the second array region (132), the first staircase comprises first stairs (114a) with a first step-down direction (X) and second stairs (114b) with a second step-down direction,
Lee-551 fails to teach:
channel structures formed in a first array region and a second array region of the stack, the first array region and the second array region being positioned at opposing sides of the stack along a first direction;
dummy channel structures formed in a connection region of the stack; and
and each of all of the first stairs and each of all of the second stairs corresponds to a different one of the word line layers.
Yip teaches an analogous structure in which a staircase region includes a memory cell region in which a stair step region 380 is between memory cell regions including vertical memory cells 301 (see Figs. 4 and 5). Yip therefore teaches:
channel structures (vertical strings 301 of memory cells) formed in a first array region (memory array region 370 on left of Fig. 5) and a second array region (memory array region 370 on right of Fig. 5) of the stack, the first array region and the second array region being positioned at opposing sides of the stack along a first direction (see Fig. 5, array regions 370 are on opposing ends of the staircase 380)
Lee-551 discloses the claimed invention except for the regions on either side of the staircase being memory array regions including channels. Yip teaches that it is known to form channels in the opposing regions to create memory array regions. It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify Lee-551 by Yip to include channels in the opposing regions for the purpose of allowing a more densely packed memory array while reducing noise (para [0064] of Yip). See MPEP 2144.
Lee-969 teaches in Fig. 3:
dummy channel structures (dummy channel structures DCS2) formed in a connection region (connection region CNR) of the stack,
Lee-551 /Yip discloses the claimed invention except for the dummy channel structure in the connection region. Lee-969 teaches that it is known to include dummy channel regions in the connection region. It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Lee-551 /Yip with the dummy channel regions of Lee-969 because such a modification would provide mechanical support to the stack (para. [0046] of Lee-969). See MPEP 2144.
Kido teaches in Fig. 9A-9B:
and each of all of the first stairs (stairs within portion 61) and each of all of the second stairs (stairs within 62) corresponds to a different one of the word line layers (Fig. 9A shows the WL layer for each stair and all are different).
Lee-551/Yip/Lee-969 discloses the claimed invention except for the additional steps in a third step down direction. Kido teaches that it is known to have each step in opposing parts of the staircase to correspond to different word lines. It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify Lee-551/Yip/Lee-969 by Kido to such that each step corresponds to a different word line for the purpose of reducing the size of the stairstep area (para. [0173] of Kido) See MPEP 2144.
With respect to claim 12, Lee-551 further teaches:
wherein a portion of the stack (middle section 122) is between the first staircase (114a and 114b) and the second staircase (114c and 114d) along a second direction (y) perpendicular to the first direction (x), and the portion of the stack (122) is between the first array region (130) and the second array region (132) along the first direction (X).
With respect to claim 13, Lee-551 further teaches:
wherein the first step-down direction (X) is opposite to the second step-down direction (-X).
With respect to claim 14, Lee-551 further teaches:
further comprising contact structures (contact structures 134) formed on the first staircase (114a and 114b) and the second staircase (114c and 114d), wherein the contact structures are connected to the word line layers (conductive structures 126) (para. [0052] “The conductive contact structures 134 may be coupled to the conductive structures 126”).
With respect to claim 15, Lee-969 further teaches:
wherein the dummy channel structures (DCS2) surround the contact structures (contact plugs 171) (see Fig. 3, each contact plug 171 is surrounded by four dummy channel structures DCS2).
It would have been obvious to one having ordinary skill in the effective filing date of the claimed invention to combine Lee-551 in view of Yip, Lee-969, and Kido as explained above.
With respect to claim 16, Lee-969 further teaches:
wherein a size of the contact structures (171) is greater than a size of the dummy channel structures (DCS2) (see Fig. 3).
It would have been obvious to one having ordinary skill in the effective filing date of the claimed invention to combine Lee-551 in view of Yip, Lee-969, and Kido as explained above.
With respect to claim 17, Kido further teaches:
wherein each height of each stair (WL24, 25, 26, 27, 28, and 29) of the first staircase (stair array 80e) is smaller than each height of each stair (WL18, 19, 20, 21, 22, 23) of the second staircase (stair array 80d), the height of each of the stairs of the first staircase and the second staircase corresponding to a number of the respective word line layers under the respective stair in a direction perpendicular to the stack of word line layers and insulating layers (para. [0130] “The numbers added to the right of "WL" of the electrode layers WL1 to WL29 indicate where they are located in the order of electrode layers WL on the upper side from the back gate BG”).
It would have been obvious to one having ordinary skill in the effective filing date of the claimed invention to combine Lee-551 in view of Yip, Lee-969, and Kido as explained above.
With respect to claim 18, Lee-551 further teaches:
wherein one of the word line layers (126) comprises a first portion in the first array region (130) and a second portion in the second array region (132), one of the contact structures (134) is connected to the first portion and the second portion through the portion of the stack between the first staircase and the second staircase (para. [0057] “The continuous conductive paths across the conductive stack structure 124 (e.g., from the first end 130 to the second, opposing end 132) provided by the configurations of the conductive structures 126 may permit an individual (e.g., single) switching device (e.g., transistor) of the string driver device 138 to drive voltages completely across (e.g., from the first end 130 to the second, opposing end 132) and/or in opposing directions across (e.g., toward the first end 130 and toward the second, opposing end 132) an individual tier 108 electrically connected thereto.”)
Claims 19-20 are rejected under 35 U.S.C. 103 as being unpatentable over Lee-551 (US 2017/0256551 A1) in view of Yip (US 2015/001613 A1) and Kido (US 2014/0027838 A1).
With respect to claim 19, Lee-551 teaches:
A semiconductor device (semiconductor device structure 100), comprising:
a stack of word line layers (conductive structures 126) and insulating layers (insulating structure 104) that are stacked alternatingly;
a first array region (first end 130) and a second array region (second end 132) of the stack (para. 45 “The first end 130 and the second, opposing end 132 of the conductive stack structure 124 may each be coupled to other components of a semiconductor device (e.g., a memory device) including the semiconductor device structure 100, such as one or more memory cell arrays (e.g., vertical memory cell arrays)”),
the first array region (130) and the second array region (132) being positioned at opposing sides of the stack along a first direction (right/left direction of Fig. 1F);
a staircase (staircase structure 114a and 114b) formed between the first array region (130) and the second array region (132);
the staircase comprises first stairs (114a) with a first step-down direction (X) and second stairs (114b) with a second step-down direction (-X), the first step-down direction being opposite to the second step-down direction
Lee-551 fails to teach:
channel structures formed in a first array region and a second array region of the stack, the first array region and the second array region being positioned at opposing sides of the stack,
the first stairs further include multiple groups of stairs, each group of the stairs being along a third step-down direction perpendicular to the first step-down direction, and each group of the stairs is, with respect to a direction perpendicular to the stack of word line layers and insulating layers, above a next neighboring group of the stairs along the first step-down direction.
Yip teaches an analogous structure in which a staircase region includes a memory cell region in which a stair step region 380 is between memory cell regions including vertical memory cells 301 (see Figs. 4 and 5). Yip therefore teaches:
channel structures (vertical strings 301 of memory cells) formed in a first array region (memory array region 370 on left of Fig. 5) and a second array region (memory array region 370 on right of Fig. 5) of the stack, the first array region and the second array region being positioned at opposing sides of the stack along a first direction (see Fig. 5, array regions 370 are on opposing ends of the staircase 380)
Lee-551 discloses the claimed invention except for the regions on either side of the staircase being memory array regions including channels. Yip teaches that it is known to form channels in the opposing regions to create memory array regions. It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify Lee-551 by Yip to include channels in the opposing regions for the purpose of allowing a more densely packed memory array while reducing noise (para [0064] of Yip). See MPEP 2144.
Kido teaches in Fig. 9A-9B:
the first stairs (staircase structure unite 80) further include multiple groups of stairs (80e, 80d, 80c, and 80b), each group of the stairs being along a third step-down direction (Y) perpendicular to the first step-down direction (X), and each group of the stairs is, with respect to a direction perpendicular to the stack of word line layers and insulating layers, above a next neighboring group of the stairs along the first step-down direction (each step in 80e is above a corresponding step in 80d).
Lee-551/Yip discloses the claimed invention except for the additional steps in a third step down direction. Kido teaches that it is known to have an additional set of steps in a second direction that is a step down from the first steps. It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify Lee-551/Yip by Kido to include additional steps in the second direction for the purpose of reducing the size of the stairstep area (para. [0173] of Kido) See MPEP 2144.
With respect to claim 20, Kido further teaches:
wherein corresponding stairs in each group of the stairs have a same stair depth, the stair depth being a height difference between two neighboring stairs in the same group (stairs reduce by 2 in portions 61 and 62 in every group of stairs).
It would have been obvious to one having ordinary skill in the effective filing date of the claimed invention to combine Lee-551 in view of Yip and Kido as explained above.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 1-3 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1 and 15 of U.S. Patent No. 12068250. Although the claims at issue are not identical, they are not patentably distinct from each other because they include similar limitations.
Instant Application
U.S. Patent No. 12068250
Claim 1: A semiconductor device, comprising: a stack of word line layers and insulating layers that are stacked alternatingly; channel structures formed in a first array region and a second array region of the stack, the first array region and the second array region being positioned at opposing sides of the stack along a first direction; a first staircase formed between the first array region and the second array region; a second staircase formed between the first array region and the second array region; and contact structures formed on the first staircase and the second staircase, wherein the contact structures are connected to the word line layers, the first staircase comprises first stairs with a first step-down direction and second stairs with a second step-down direction, and each of all of the first stairs and each of all of the second stairs corresponds to a different one of the word line layers.
Claim 1: A semiconductor device, comprising: a stack of word line layers and insulating layers that are stacked alternatingly; and channel structures formed in a first array region and a second array region of the stack, the first array region and the second array region being positioned at opposing sides of the stack, wherein a first staircase is formed between the first array region and the second array region, a second staircase is formed between the first array region and the second array region, the first staircase has first stairs with a first step-down direction and second stairs with a second step-down direction, the first step-down direction being opposite to the second step- down direction, and each of all of the first stairs and each of all of the second stairs corresponds to a different one of the word line layers
Claim 15: further comprising: first contact structures formed on the first staircase and connected to the word line layers in the first staircase; and second contact structures formed on the second staircase and connected to the word line layers in the second staircase.
Claim 2: wherein a portion of the stack is between the first staircase and the second staircase along a second direction perpendicular to the first direction, and the portion of the stack is between the first array region and the second array region along the first direction.
Claim 1: a portion of the stack is positioned between the first staircase and the second staircase and between the first array region and the second array region,
Claim 3: wherein the first step-down direction is opposite to the second step-down direction.
Claim 1: the first step-down direction being opposite to the second step- down direction
Conclusion
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/A.M.W./Examiner, Art Unit 2897
/JACOB Y CHOI/Supervisory Patent Examiner, Art Unit 2897
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