DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-7, 9-17, and 19-20 are rejected under 35 U.S.C. 103 as being unpatentable over Yun (US 2024/0429151), Hattori et al. (“Hattori” US 2021/0387276), and Chen et al. (“Chen” US 2023/0307268).
Regarding claim 1, Yun discloses a semiconductor package (10), comprising:
a package substrate (100) having a first surface (upper surface) and a second surface (lower surface) opposite to each other, wherein the package substrate (100) includes a plurality of first substrate pads (150) and a plurality of second substrate pads (160) that are exposed from the first surface (upper surface, see Figure 2) and are electrically connected to each other (para. [0031]);
a semiconductor device (200) mounted on the first surface of the package substrate (100) and electrically connected to the plurality of first substrate pads (150);
conductive bumps (320) disposed on the plurality of second substrate pads (160); and
a semiconductor element (300) mounted on the package substrate (100) via the conductive bumps (320) and spaced apart from the semiconductor device (200, see Figure 2).
Yun does not disclose wherein each of the conductive bumps includes a bump body and a conductive member, wherein the bump body has a first melting point, and the conductive member at least partially surrounds the bump body and has a second melting point that is lower than the first melting point, and wherein the semiconductor element has metal oxide barriers that are provided on the conductive members and are provided on a side surface of the semiconductor element.
Hattori discloses in Figure 5, however, conductive bumps (24) wherein each of the conductive bumps (24) includes a bump body (24a) and a conductive member (24c), wherein the bump body has a first melting point, and the conductive member (24c) at least partially surrounds the bump body (24a, see Figure 5) and has a second melting point that is lower than the first melting point (see para. [0041], the material used for the bump body 24a has a higher melting point than the material used for the conductive member 24c).
It would have been obvious to a person having ordinary skill in the art to incorporate the teachings of Hattori into the teachings of Yun to include the conductive bumps as claimed for the purpose of decreasing costs (Hattori, para. [0067]).
Further, Chen discloses in Figure 8, a semiconductor element (107) having metal oxide barriers (120) that are provided on the conductive members (124 and 202) and are provided on a side surface (lateral and lower side surfaces) of the semiconductor element (107, see Figure 8).
It would have been obvious to a person having ordinary skill in the art to incorporate the teachings of Chen into the teachings of Yun and Hattori to include the metal oxide barriers as claimed for the purpose of protecting the die from moisture (Chen, para. [0040]).
Regarding claim 2, Yun discloses wherein a lower surface of the semiconductor element (300) is spaced apart from the first surface of the package substrate (100, upper surface) by a first distance (D1, see Figure 4), and
the first distance (D1) is within a range of about 40 µm to about 60 µm (para. [0049]).
Regarding claim 3, Hattori discloses wherein the conductive bumps (24) include a Cu Core Solder Ball (CCSB) (the core/bump body 24a is made of copper and surrounded by solder/conductive member 24c, see para. [0041]).
Regarding claim 4, Hattori discloses wherein a diameter of each of the bump bodies (24a) is within a range of about 20 µm to about 40 µm (see para. [0047]).
Additionally, the range disclosed by Hattori overlaps the claimed range, and in the case where the claimed ranges “overlap or lie inside ranges disclosed by the prior art,” a prima facie case of obviousness exists (In re Wertheim, 541 F.2d 257, 191 USPQ 90 (CCPA 1976)).
Regarding claim 5, Yun discloses wherein the semiconductor element (300) includes a plurality of elements pads (310) that are disposed on a lower surface of the semiconductor element (200, see Figure 4) and are electrically connected to the conductive bumps (320).
Regarding claim 6, Hattori discloses wherein each of the conductive bumps (24) further includes a seed layer (24b) that is provided between the bump body (24a) and the conductive member (24c, see Figure 5).
Regarding claim 7, Hattori discloses wherein the bump bodies (24a) include at least any one of nickel (Ni), bismuth (Bi), indium (In), aluminum (Al), copper (Cu), lead (Pb), gold (Au), silver (Ag), or polymer (copper, see para. [0041]).
Regarding claim 9, Yun discloses wherein the semiconductor element (300) includes at least one of a passive device, a multi-layer ceramic capacitor (MLCC), a low inductance chip capacitor (LICC), a die side capacitor (DSC), a land side capacitor (LSC), an inductor, and an integrated passive device (IPD) (para. [0044]).
Regarding claim 10, Yun further discloses a sealing member (550) disposed on the package substrate (100) and covering the semiconductor device (200), the conductive bumps (320) and the semiconductor element (300).
Regarding claim 11, Yun discloses a semiconductor package (10), comprising:
a package substrate (100) having a first surface (upper surface) and a second surface (lower surface) opposite to each other, wherein the package substrate (100) includes a plurality of first substrate pads (150) and a plurality of second substrate pads (160) that are exposed from the first surface and are electrically connected to each other (see Figure 2, para. [0031]);
conductive bumps (320) disposed on the plurality of second substrate pads (160); and
a semiconductor element (300) mounted on the package substrate (100) via the conductive bumps (320).
Yun does not disclose wherein each of the conductive bumps includes a bump body and a conductive member, wherein the bump body has a first melting point, and the conductive member at least partially surrounds the bump body and has a second melting point that is lower than the first melting point, and wherein the semiconductor element has metal oxide barriers that are provided on the conductive members and that cover at least a portion of a side surface of the semiconductor element.
Hattori discloses in Figure 5, however, conductive bumps (24) wherein each of the conductive bumps (24) includes a bump body (24a) and a conductive member (24c), wherein the bump body has a first melting point, and the conductive member (24c) at least partially surrounds the bump body (24a, see Figure 5) and has a second melting point that is lower than the first melting point (see para. [0041], the material used for the bump body 24a has a higher melting point than the material used for the conductive member 24c).
It would have been obvious to a person having ordinary skill in the art to incorporate the teachings of Hattori into the teachings of Yun to include the conductive bumps as claimed for the purpose of decreasing costs (Hattori, para. [0067]).
Further, Chen discloses in Figure 8, a semiconductor element (107) having metal oxide barriers (120) that are provided on the conductive members (124 and 202) and cover at least a portion of a side surface (lateral and lower side surfaces) of the semiconductor element (107, see Figure 8).
It would have been obvious to a person having ordinary skill in the art to incorporate the teachings of Chen into the teachings of Yun and Hattori to include the metal oxide barriers as claimed for the purpose of protecting the die from moisture (Chen, para. [0040]).
Regarding claim 12, Yun discloses wherein a lower surface of the semiconductor element (300) is spaced apart from the first surface of the package substrate (100, upper surface) by a first distance (D1, see Figure 4), and
the first distance (D1) is within a range of about 40 µm to about 60 µm (para. [0049]).
Regarding claim 13, Hattori discloses wherein the conductive bumps (24) include a Cu Core Solder Ball (CCSB) (the core/bump body 24a is made of copper and surrounded by solder/conductive member 24c, see para. [0041]).
Regarding claim 14, Hattori discloses wherein a diameter of each of the bump bodies (24a) is within a range of about 20 µm to about 40 µm (see para. [0047]).
Additionally, the range disclosed by Hattori overlaps the claimed range, and in the case where the claimed ranges “overlap or lie inside ranges disclosed by the prior art,” a prima facie case of obviousness exists (In re Wertheim, 541 F.2d 257, 191 USPQ 90 (CCPA 1976)).
Regarding claim 15, Yun discloses wherein the semiconductor element (300) includes a plurality of elements pads (310) that are disposed on a lower surface of the semiconductor element (200, see Figure 4) and are electrically connected to the conductive bumps (320).
Regarding claim 16, Hattori discloses wherein each of the conductive bumps (24) further includes a seed layer (24b) that is provided between the bump body (24a) and the conductive member (24c, see Figure 5).
Regarding claim 17, Hattori discloses wherein the bump bodies (24a) include at least any one of nickel (Ni), bismuth (Bi), indium (In), aluminum (Al), copper (Cu), lead (Pb), gold (Au), silver (Ag), or polymer (copper, see para. [0041]).
Regarding claim 19, Yun discloses a semiconductor device (200) mounted on the first surface of the package substrate (100) to be spaced apart from the semiconductor element (300) and electrically connected to the plurality of first substrate pads (150).
Regarding claim 20, Yun discloses a semiconductor package (10), comprising:
a package substrate (100) having a first surface (upper surface) and a second surface (lower surface) opposite to each other, wherein the package substrate (100) includes a plurality of first substrate pads (150) and a plurality of second substrate pads (160) that are exposed from the first surface (upper surface, see Figure 2) and are electrically connected to each other (para. [0031]);
a semiconductor device (200) mounted on the first surface of the package substrate (100) and electrically connected to the plurality of first substrate pads (150);
conductive bumps (320) disposed on the plurality of second substrate pads (160); and
a semiconductor element (300) mounted on the package substrate (100) via the conductive bumps (320) to be electrically connected to the plurality of second substrate pads (160),
wherein the semiconductor element (300) includes a multi-layer ceramic capacitor (MLCC) (para. [0044]).
Yun does not disclose wherein each of the conductive bumps includes a bump body and a conductive member, wherein the bump body has a first melting point, and the conductive member at least partially surrounds the bump body and has a second melting point that is lower than the first melting point, and wherein the semiconductor element has metal oxide barriers provided on the conductive members and provided on a side surface of the semiconductor element.
Hattori discloses in Figure 5, however, conductive bumps (24) wherein each of the conductive bumps (24) includes a bump body (24a) and a conductive member (24c), wherein the bump body has a first melting point, and the conductive member (24c) at least partially surrounds the bump body (24a, see Figure 5) and has a second melting point that is lower than the first melting point (see para. [0041], the material used for the bump body 24a has a higher melting point than the material used for the conductive member 24c).
It would have been obvious to a person having ordinary skill in the art to incorporate the teachings of Hattori into the teachings of Yun to include the conductive bumps as claimed for the purpose of decreasing costs (Hattori, para. [0067]).
Further, Chen discloses in Figure 8, a semiconductor element (107) having metal oxide barriers (120) that are provided on the conductive members (124 and 202) and are provided on a side surface (lateral and lower side surfaces) of the semiconductor element (107, see Figure 8).
It would have been obvious to a person having ordinary skill in the art to incorporate the teachings of Chen into the teachings of Yun and Hattori to include the metal oxide barriers as claimed for the purpose of protecting the die from moisture (Chen, para. [0040]).
Claims 8 and 18 are rejected under 35 U.S.C. 103 as being unpatentable over Yun, Hattori, and Chen as applied to claims 1 and 11 above, and further in view of Brogan et al. (“Brogan” US 2023/0260834).
Regarding claim 8, Chen does not disclose that the metal oxide barriers include zinc (Zn) or nickel (Ni).
Brogan discloses, however, wherein the metal oxide barriers include zinc (Zn) or nickel (Ni) (see para. [0006]).
It would have been obvious to a person having ordinary skill in the art to use a metal oxide material including Zn or Ni as taught by Brogan because the selection of a known material based on its suitability for its intended use is prima facie obvious. See MPEP 2144.07.
Regarding claim 18, Chen does not disclose that the metal oxide barriers include zinc (Zn) or nickel (Ni).
Brogan discloses, however, wherein the metal oxide barriers include zinc (Zn) or nickel (Ni) (see para. [0006]).
It would have been obvious to a person having ordinary skill in the art to use a metal oxide material including Zn or Ni as taught by Brogan because the selection of a known material based on its suitability for its intended use is prima facie obvious. See MPEP 2144.07.
Conclusion
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/Genevieve G Bullard-Connor/Examiner, Art Unit 2899 /DALE E PAGE/Supervisory Patent Examiner, Art Unit 2899
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