DETAILED ACTION
Notice of Pre-AIA or AIA Status
1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Note by the Examiner
2. For clarity, the reference to specific claim numbers are presented in bold. Cited claim limitations are presented in bold the first time they are associated with a particular prior art disclosing the cited limitations, and subsequent reference to the already disclosed claim limitations are presented un-bolded. Certain elements from prior art which are not required by the claims are also presented un-bolded if they are particularly pertinent to understanding how the references are being combined. Item-to-item matching and Examiner explanations for 102 &/or 103 rejections have been provided in parenthesis.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
3. Claims 1-9, 11, and 13-14 are rejected under 35 U.S.C. 102(a)(1) and (a)(2) as being anticipated by Okamoto et al. (US 2016/0337607 A1), hereinafter as O1
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4. Regarding Claim 1, O1 discloses an electronic device (see Figs. 27A-B, 28B, “Labeled Fig. 27A” above, and [0217-0225], in particular see [0218] “as illustrated in FIG. 28B, they may be transistors each including an active layer 650 formed using a silicon thin film” selected as the transistors of Fig. 28B) having a first region (comprising a vertically overlapped portion with at least element 44) and a second region (comprising a vertically overlapped portion with at least element 43) adjacent to the first region, comprising:
a first substrate (element 600, below element 610, 620, see [0219] “silicon substrate”);
a silicon semiconductor (labeled element “Silicon Semiconductor Layer”, see Fig. 28B silicon fin layer of element 650, see [0218] “as illustrated in FIG. 28B, they may be transistors each including an active layer 650 formed using a silicon thin film”) disposed on the first substrate and in the first region (see “Labeled Fig. 27A” above);
a first oxide semiconductor (labeled element “First Oxide Semiconductor Layer”, oxide semiconductor active layer of element 43, see [0110] “As the transistor with low off-state current, a transistor including an oxide semiconductor in its active layer (hereinafter referred to as OS transistor) can be used, for example.” And see [0116] “some or all of the transistors 43 to 46 are preferably OS transistors”, and see [0223] “oxide semiconductor layer that is the active layer of the transistor 43”) disposed on the first substrate and in the second region (see “Labeled Fig. 27A” above);
a first conductive component (labeled element “First Conductive Component”, wiring element electrically connected to the source/drain electrode of the transistor element 610) disposed on the first substrate and electrically connected to the silicon semiconductor (see “Labeled Fig. 27A” above); and
a second conductive component (labeled element “Second Conductive Component”, conductive layer above the “First Conductive Component”) disposed between the first substrate and the first oxide semiconductor (see “Labeled Fig. 27A” above),
wherein the second conductive component is at least partially overlapped with the first oxide semiconductor and electrically connected to the first conductive component (see “Labeled Fig. 27A” above).
5. Regarding Claim 2, O1 discloses the electronic device of claim 1, further comprising a third conductive component (labeled element “Third Conductive Component” source/drain conductive layer of transistor element 43 directly connected to element 566) disposed on the first conductive component, wherein the third conductive component is electrically connected to the first oxide semiconductor (see “Labeled Fig. 27A” above).
6. Regarding Claim 3, O1 discloses the electronic device of claim 2, wherein the third conductive component is directly connected to the first oxide semiconductor (see “Labeled Fig. 27A” above).
7. Regarding Claim 4, O1 discloses the electronic device of claim 2, further comprising a second oxide semiconductor (labeled element “Second Oxide Semiconductor Layer”, oxide semiconductor active layer of element 44, see [0110, 0116, 0223]) disposed on the first substrate, wherein the second oxide semiconductor is electrically connected to the third conductive component (see “Labeled Fig. 27A” above, when transistors 43, 44 are turned on there is electrical connection between the source, drain, channels of the transistors).
8. Regarding Claim 5, O1 discloses the electronic device of claim 4, wherein the third conductive component is at least partially overlapped with the first conductive component (see “Labeled Fig. 27A” above).
9. Regarding Claim 6, O1 discloses the electronic device of claim 1, wherein the silicon semiconductor is disposed between the first substrate and the first oxide semiconductor (see “Labeled Fig. 27A” above).
10. Regarding Claim 7, O1 discloses the electronic device of claim 1, further comprising a fourth conductive component (labeled element “Fourth Conductive Component, gate electrode wiring connected to the gate electrode of element 610) overlapped with the silicon semiconductor (see “Labeled Fig. 27A” above), wherein the silicon semiconductor is disposed between the first substrate and the fourth conductive component (see “Labeled Fig. 27A” above).
11. Regarding Claim 8, O1 discloses the electronic device of claim 1, further comprising a second substrate (see Fig. 53A element 820, see [0436] “cover glass 820”, and see [0435] “For the image sensor chip, the structure of an imaging device of one embodiment of the present invention can be used”) disposed opposite to the first substrate, wherein the silicon semiconductor and the first oxide semiconductor are disposed between the first substrate and the second substrate (see Fig. 53A and “Labeled Fig. 27A” above).
12. Regarding Claim 9, O1 discloses the electronic device of claim 8, further comprising an organic layer (element 83, see [0178] “an organic insulating film such as an acrylic resin film or a polyimide resin film may be used”) disposed between the first substrate and the second substrate.
13. Regarding Claim 11, O1 discloses the electronic device of claim 1, wherein the first oxide semiconductor is an indium gallium zinc oxide semiconductor (see [0338-0339] “As the oxide semiconductor, for example, any of the following can be used: … an In—Ga—Zn oxide … a film containing the In—Ga—Zn oxide is also referred to as an IGZO film”).
14. Regarding Claim 13, O1 discloses the electronic device of claim 1, wherein the first substrate comprises a flexible substrate (silicon substrate of O1 is the same material as the Applicant’s substrate which has the same flexible inherent material properties).
15. Regarding Claim 14, O1 discloses the electronic device of claim 1, wherein the first region is surrounding the second region (the first region is broadly recited without any associated elements or physical boundaries such that it can be arbitrarily defined to include an area which surrounds the second region).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
16. Claim 10 is rejected under 35 U.S.C. 103 as obvious over Okamoto et al. (US 2016/0337607 A1), hereinafter as Okamoto, in view of Lou et al. (US 2018/0219032 A1), hereinafter as Lou
17. Regarding Claim 10, O1 discloses the electronic device of claim 1.
O1 does not explicitly disclose wherein the silicon semiconductor is a low-temperature polycrystalline silicon semiconductor.
L1 discloses wherein the silicon semiconductor layer is a low-temperature polycrystalline silicon semiconductor layer (see [0032] “the first active layer 12 and the second active layer 13 are made of different materials. Specifically, the first active layer 12 can be made of low-temperature polycrystalline silicon (LTPS, also called Low Temperature Poly-Silicon), and the second active layer 13 can be made of an oxide semiconductor”).
The specific type of silicon of the silicon semiconductor layer as taught by L1 is incorporated as the specific type of silicon semiconductor layer of O1.
It would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to incorporate the teachings of L1 with O1 because the combination provides an active layer material of a transistor which provides low power consumption, high aperture ratio, high resolution (see L1 [0032]), and the combination is simple substitution of one known element for another to obtain predictable results – simple substitution of one known specific silicon active layer material of a similar transistor for another to obtain predictable results.
18. Claim 12 is rejected under 35 U.S.C. 103 as obvious over Okamoto et al. (US 2016/0337607 A1), hereinafter as Okamoto, in view of Yoneda (US 2018/0294349 A1)
[Cho et al. (US 2009/0261389 A1), hereinafter as Cho, and Kurosawa et al. (US 2012/0056861 A1), hereinafter as Kurosawa are utilized herein as evidence]
19. Regarding Claim 12, O1 discloses the electronic device of claim 1.
O1 does not explicitly disclose further comprising a light emitting unit electrically connected to the first oxide semiconductor, wherein the light emitting unit is an organic light-emitting diode.
Y1 discloses (see Figs. 9-10 and [0198] “device having a display function … the use of the semiconductor device including transistors in any of Embodiments 1 to 4”) further comprising a light emitting unit (see [0216] “The light-emitting element includes … an organic EL element”, also see [0242-0244]) electrically connected to the first oxide semiconductor (element 468 see [0226] “the second semiconductor film 468 is an oxide semiconductor film”), wherein the light emitting unit is an organic light-emitting diode (see [0231] “display element includes the pixel electrodes (the first pixel electrode 434 and the second pixel electrode 436), a counter electrode 421” and [0216, 0242-0244] selected as an organic LE display with lower and upper electrodes forming a diode unit).
The display connected to transistors as taught by Y1 is incorporated as a display connected to transistors of O1.
It would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to incorporate the teachings of Y1 with O1 because the combination provides a display which can be used with or as an alternative for image sensors, wherein oxide semiconductor transistors and/or silicon semiconductor transistors can be utilized for either or both types of devices, and the combination is simple substitution of one known element for another to obtain predictable results – simple substitution of one known active element connected to the transistors for another to obtain predictable results (see Okamoto [0444] “An imaging device of one embodiment of the present invention can be used for display devices”; also see evidentiary reference Kurokawa [0173] “using an oxide semiconductor film for the active layers of all the transistors in the display element 321 and the photosensor 301, the manufacturing process of the semiconductor device can be simplified”, and see evidentiary reference Cho [0018] “TFT using the oxide semiconductor thin film as the active layer may be used as a driver device for various display devices and image sensors”).
20. Claim 15 is rejected under 35 U.S.C. 103 as obvious over Okamoto et al. (US 2016/0337607 A1), hereinafter as Okamoto, in view of Sasaki et al. (US 2005/0213173 A1), hereinafter as S1
21. Regarding Claim 15, O1 discloses the electronic device of claim 1.
O1 does not explicitly disclose wherein a driver circuit is disposed in the first region and comprises the silicon semiconductor.
S1 discloses the driver circuit comprises the silicon semiconductor (see [0141] “CMOS thin film transistors composed of polysilicon thin film transistors constitute the driver circuit sections”).
The CMOS thin film transistor comprising silicon semiconductor part of the driver circuit as taught by O1 is incorporated as the CMOS thin film transistor comprising silicon semiconductor part of the driver circuit of S1, the combination discloses wherein a driver circuit is disposed in the first region and comprises the silicon semiconductor.
It would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to incorporate the teachings of S1 with O1 because the combination is simple substitution of one known element for another to obtain predictable results – simple substitution of one known drivers circuit transistor type and location for another in a similar device to obtain predictable results (see S1 [0141]).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SAMUEL PARK whose telephone number is (303)297-4277. The examiner can normally be reached Normal Schedule: M-F Sometime between 6:30 a.m. - 7:00 p.m..
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/SAMUEL PARK/Examiner, Art Unit 2818
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